HOLT HI-8581PQI, HI-8581PJT, HI-8581PJI, HI-8581CJT, HI-8581CJI Datasheet

June2001

HI-8581

GENERALDESCRIPTION

TheHI-8581devicefromHoltIntegratedCircuitsisasilicon
gateCMOSdeviceforinterfacinga16-bitparalleldatabus
directlytotheARINC429serialbus.Thedeviceprovides
tworeceivers,anindependenttransmitterandlinedriver
capabilityinasinglepackage.Thereceiverinputcircuitry
andlogicaredesignedtomeettheARINC429
specificationsforloading,leveldetection,timing,and
protocol.ThetransmittersectionprovidestheARINC429
communicationprotocolandthelinedrivercircuitsprovide
theARINC429outputlevels.

The16-bitparalleldatabusexchangesthe32-bitARINC
datawordintwostepswheneitherloadingthetransmitter
orinterrogatingthereceivers.Thedatabusinterfaceswith
CMOSandTTL.

Timingofallthecircuitrybeginswiththemasterclockinput,
CLK.ForARINC429applications,themasterclock
frequencyis1MHz.

Eachindependentreceivermonitorsthedatastreamwitha
samplingrate10timesthedatarate.Thesamplingrateis
softwareselectableateither1MHzor125KHz.Theresults
ofaparitycheckareavailableasthe32ndARINCbit.The
HI-8581examinesthenullanddatatimingsandwillreject
erroneouspatterns.Forexample,witha125KHzclock
selection,thedatafrequencymustbebetween10.4KHz
and15.6KHz.

FEATURES

!

ARINCspecification429compatible

!

Directreceiverandtransmitterinterfaceto
ARINCbusinasingledevice.

!

16-Bitparalleldatabus.

!

Timingcontrol10timesthedatarate

!

Selectabledataclocks

!

ReceivererrorrejectionperARINC
specification429

!

Automatictransmitterdatatiming

!

Selftestmode

!

Parityfunctions

!

Lowpower

!

Industrial&fullmilitarytemperatureranges

PINCONFIGURATION (TopView)

ThetransmitterhasaFirstIn,FirstOut(FIFO)memoryto
store8ARINCwordsfortransmission.Thedatarateofthe
transmitterissoftwareselectablebydividingthemaster
clock,CLK,byeither10or80.Themasterclockisusedto
setthetimingoftheARINCtransmissionwithintherequired
resolution.

APPLICATIONS

!

Avionicsdatacommunication

!

Serialtoparallelconversion

!

Paralleltoserialconversion

HOLTINTEGRATEDCIRCUITS

33-

429DI2(B)-1

1(DS8581Rev.A)06/01

-2

D/R1

-3

D/R2

SEL-4

-5

EN1

-6

EN2
BD15-7
BD14-8
BD13-9
BD12-10

BD11-11

(Seepage13foradditionalpinconfigurations)

HI-8581PQI

&

HI-8581PQT

ENTX
32-N/C
31-V+
30-TXB(OUT)
29-TXA(OUT)
28-V­27-GND
26-TX/R
25-

PL2
24-

PL1
23-

BD00

HI-8581

SIGNALFUNCTIONDESCRIPTION

VPOWER+5V±5%

CC

V+POWER+9.5Vto+12.6V

V-POWER-9.5Vto-12.6V
429DI1(A)INPUTARINCreceiver1positiveinput
429DI1(B)INPUTARINCreceiver1negativeinput
429DI2(A)INPUTARINCreceiver2positiveinput
429DI2(B)INPUTARINCreceiver2negativeinput

D/R1
D/R2

SELINPUTReceiverdatabyteselection(0=BYTE1)(1=BYTE2)
EN1
EN2EN1

BD15I/ODataBus
BD14I/ODataBus
BD13I/ODataBus
BD12I/ODataBus
BD11I/ODataBus
BD10I/ODataBus
BD09I/ODataBus
BD08I/ODataBus
BD07I/ODataBus
BD06I/ODataBus

GNDPOWER0V
BD05I/ODataBus
BD04I/ODataBus
BD03I/ODataBus
BD02I/ODataBus
BD01I/ODataBus
BD00I/ODataBus

TX/ROUTPUTTransmitterreadyflag.GoeslowwhenARINCwordloadedintoFIFO.Goeshigh

PL1

PL2PL1
TXA(OUT)OUTPUTLinedriveroutput-Aside
TXB(OUT)OUTPUTLinedriveroutput-Bside

ENTXINPUTEnableTransmission

CWSTR

CLKINPUTMasterClockinput

TXCLKOUTPUTTransmitterClockequaltoMasterClock(CLK),dividedbyeither10or80.

MR

OUTPUTReceiver1datareadyflag
OUTPUTReceiver2datareadyflag

INPUTDataBuscontrol,enablesreceiver1datatooutputs
INPUTDataBuscontrol,enablesreceiver2datatooutputsifishigh

AftertransmissionandFIFOempty.
INPUTLatchenableforbyte1enteredfromdatabustotransmitterFIFO.
INPUTLatchenableforbyte2enteredfromdatabustotransmitterFIFO.Mustfollow.

INPUTClockforcontrolwordregister

INPUTMasterReset,activelow

HOLTINTEGRATEDCIRCUITS

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HI-8581

FUNCTIONALDESCRIPTION

CONTROLWORDREGISTER

TheHI-8581contains10dataflipflopswhoseDinputsarecon­nectedtothedatabusandclocksconnectedto.Each
flipflopprovidesoptionstotheuserasfollows:

DATA

BUSFUNCTIONCONTROLDESCRIPTION

PIN

Ifenabled,aninternalconnection

BDO5SELFTEST0=ENABLEismadepassing429DOand

429DO

RECEIVER1Ifenabled,ARINCbits9and,

BDO6DECODER1=ENABLE10mustmatchthenexttwo

IfReceiver1Decoderis

BDO7--enabled,theARINCbit9

IfReceiver1Decoderis

BDO8--enabled,theARINCbit10

RECEIVER2Ifenabled,ARINCbits9and

BDO9DECODER1=ENABLE10mustmatchthenexttwo

IfReceiver2Decoderis

BD10--enabled,thenARINCbit9

IfReceiver2Decoderis

BD11--enabled,thenARINCbit10

INVERTLogic0enablesnormaloddparity

BD12XMTR1=ENABLEandLogic1enablesevenparity

PARITYoutputintransmitter32ndbit

BD13XMTRDATA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainXMTRdataclock

BD14RCVRDTA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainRCVRdataclock

CWSTR

tothereceiverlogicinputs

controlwordbits

mustmatchthisbit

mustmatchthisbit

controlwordbits

mustmatchthisbit

mustmatchthisbit

ARINC429DATAFORMAT

Thefollowingtableshowsthebitpositionsinexchangingdatawith
thereceiverorthetransmitter.ARINCbit1isthefirstbit
transmittedorreceived.

BYTE1

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC13121110931303212345678

BIT

BYTE2

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC29282726252423222120191817161514

BIT

THERECEIVERS

ARINCBUSINTERFACE

Figure1showstheinputcircuitforeachreceiver.TheARINC429
specificationrequiresthefollowingdetectionlevels:

STATEDIFFERENTIALVOLTAGE

ONE+6.5Voltsto+13Volts

NULL+2.5Voltsto-2.5Volts

ZERO-6.5Voltsto-13Volts

TheHI-8581guaranteesrecognitionoftheselevelswithacommon
modeVoltagewithrespecttoGNDlessthan±5Vfortheworstcase
condition(4.75Vsupplyand13Vsignallevel).

Thetolerancesinthedesignguaranteedetectionoftheabove
levels,sotheactualacceptancerangesareslightlylarger.Ifthe
ARINCsignalisoutoftheactualacceptanceranges,includingthe
nulls,thechiprejectsthedata.

HOLTINTEGRATEDCIRCUITS

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HI-8581

FUNCTIONALDESCRIPTION(con't)

RECEIVERLOGICOPERATION

Figure2showsablockdiagramofthelogicsectionofeachreceiver.

BITTIMING

TheARINC429specificationcontainsthefollowingtiming
specificationforthereceiveddata:

HIGHSPEEDLOWSPEED

BITRATE

PULSERISETIME

PULSEFALLTIME

PULSEWIDTH

AgaintheHI-8581acceptssignalsthatmeetthesespecifications
andrejectsoutsidethetolerances.Thewaythelogicoperation
achievesthisisdescribedbelow:

1.Keytotheperformanceofthetimingcheckinglogicisanac­curate1MHzclocksource.Lessthan0.1%errorisrecom­mended.

2.Thesamplingshiftregistersare10bitslongandmustshow
threeconsecutiveOnes,ZerosorNullstobeconsideredvalid
data.Additionally,fordatabits,theOneorZerointheupperbits
ofthesamplingshiftregistersmustbefollowedbyaNullinthe
lowerbitswithinthedatabittime.ForaNullinthewordgap,
threeconsecutiveNullsmustbefoundinboththeupperand
lowerbitsofthesamplingshiftregister.Inthismannerthemini­mumpulsewidthisguaranteed.

100KBPS±1%12K-14.5KBPS

1.5±0.5µsec10±5µsec

1.5±0.5µsec10±5µsec
5µsec±5%34.5to41.7µsec

TOPINS

3.Eachdatabitmustfollowitspredecessorbynotlessthan
8samplesandnomorethan12samples.Inthismannerthe
bitrateischecked.Withexactly1MHzinputclockfrequency,
theacceptabledatabitratesareasfollows:

HIGHSPEEDLOWSPEED

DATABITRATEMIN

DATABITRATEMAX

83KBPS10.4KBPS

125KBPS15.6KBPS

4.TheWordGaptimersamplestheNullshiftregisterevery
10inputclocks(80forlowspeed)afterthelastdatabitofa
Validreception.IftheNullispresent,theWordGapcounter
Isincremented.Acountof3willenablethenextreception.

RECEIVERPARITY

ThereceiverparitycircuitcountsOnesreceived,includingthe
paritybit,ARINCbit32.Iftheresultisodd,then"0"willappearin
the32ndbit.

RETRIEVINGDATA

Once32validbitsarerecognized,thereceiverlogicgeneratesan
EndofSequence(EOS).Ifthereceiverdecoderisenabledand
the9thand10thARINCbitsmatchthecontrolwordprogrambits
orifthereceiverdecoderisdisabled,thenEOSclocksthedata
readyflagflipfloptoa"1",or(orboth)willgolow.The
dataflagforareceiverwillremainlowuntilafterARINCbytes

D/R1D/R2

both
fromthatreceiverareretrieved.Thisisaccomplishedbyfirst
activatingwithSEL,thebyteselector,lowtoretrievethefirst
byteandthenactivatingwithSELhightoretrievethesecond
byte.retrievesdatafromreceiver1andretrievesdata

EN

EN

ENIEN2

fromreceiver2.
IfanotherARINCwordisreceived,andanewEOSoccursbefore

thetwobytesareretrieved,thedataisoverwrittenbythenew
word.

SEL

EN

D/R

DECODER
CONTROL

BITS

/

ONES

NULL

ZEROS

MUX

CONTROL

LATCH

ENABLE

CONTROL

EOS

BITS9&10

SHIFTREGISTER

SHIFTREGISTER

SHIFTREGISTER

32TO16DRIVER

32BITLATCH

32BITSHIFTREGISTER

BITCLOCK

WORDGAP

DATA

START

CONTROL

BITBD14

PARITY
CHECK

WORDGAP

SEQUENCE

CONTROL

DETECTION

TIMER

ERROR

FIGURE2. RECEIVERBLOCKDIAGRAM

HOLTINTEGRATEDCIRCUITS

4

32ND

BIT

CLOCK

OPTION

COUNTER

ENDOF

SEQUENCE

EOS

BITCLOCK

END

ERROR

CLOCK

CLK

CLOCK

BIT

AND

HI-8581

TRANSMITTER

AblockdiagramofthetransmittersectionisshowninFigure3.

FIFOOPERATION

TheFIFOisloadedsequentiallybyfirstpulsingtoloadbyte1
andthentoloadbyte2.Thecontrollogicautomaticallyloads
the31bitwordinthenextavailablepositionoftheFIFO.IfTX/R,
thetransmitterreadyflagishigh(FIFOempty),then8words,
each31bitslong,maybeloaded.IfTX/Rislow,thenonlythe
availablepositionsmaybeloaded.Ifall8positionsarefull,the
FIFOignoresfurtherattemptstoloaddata.

PL2

DATATRANSMISSION

WhenENTXgoeshigh,enablingtransmission,theFIFO
positionsareincrementedwiththetopregisterloading intothe
datatransmissionshiftregister.Within2.5dataclocksthefirst
databitappearsateither429DOor.The31bitsinthe
datatransmissionshiftregisterarepresentedsequentiallytothe
outputsintheARINC429formatwiththefollowingtiming:

ARINCDATABITTIME10Clocks80Clocks

DATABITTIME5Clocks40Clocks
NULLBITTIME5Clocks40Clocks

WORDGAPTIME40Clocks320Clocks

429DO

HIGHSPEEDLOWSPEED

PL1

TRANSMITTERPARITY

TheparitygeneratorcountstheONESinthe31-bitword.Ifthe
BD12controlwordbitissetlow,the32ndbittransmittedwill
makeparityodd.Ifthecontrolbitishigh,theparityiseven.

SELFTEST

IftheBD05controlwordbitissetlow,429DOorbecome
inputstothereceiverbypassingtheinterfacecircuitry.

429DO

SYSTEMOPERATION

Thetworeceiversareindependentofthetransmitter.Therefore,
controlofdataexchangesisstrictlyattheoptionoftheuser.The
onlyrestrictionsare:

1.Thereceiveddatamaybeoverwrittenifnotretrieved
withinoneARINCwordcycle.

2.TheFIFOcanstore8wordsmaximumandignores
attemptstoloadadditiondataiffull.

3.Byte1ofthetransmitterdatamustbeloadedfirst.

4.Eitherbyteofthereceiveddatamayberetrievedfirst.
Bothbytesmustberetrievedtoclearthedatareadyflag.

Thewordcounterdetectswhenallloadedpositionsare
transmittedandsetsthetransmitterreadyflag,TX/R,high.

5.AfterENTX,transmissionenable,goeshighitcannotgo
lowuntilTX/R,transmitterreadyflag,goeshigh.Otherwise,
oneARINCwordislostduringtransmission.

HOLTINTEGRATEDCIRCUITS

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