HOLT HI-8282ACLT, HI-8282ACLM, HI-8282ACLI, HI-8282ACDT, HI-8282ACDI Datasheet

HI-8282A

ARINC429SERIALTRANSMITTERANDDUALRECEIVER

PINCONFIGURATION (TopView)

GENERALDESCRIPTION

TheHI-8282AisasilicongateCMOSdeviceforinterfacing
theARINC429serialdatabustoa16-bitparalleldatabus.
Tworeceiversandanindependenttransmitterare
provided.Thereceiverinputcircuitryandlogicare
designedtomeettheARINC429specificationsforloading,
leveldetection,timing,andprotocol.Thetransmitter
sectionprovidestheARINC429communicationprotocol.
AdditionalinterfacecircuitrysuchastheHoltHI-8585,
HI-8586orHI-3182isrequiredtotranslatethe5voltlogic
outputstoARINC429drivelevels.

The16-bitparalleldatabusexchangesthe32-bi tARINC
datawordintwostepswheneitherloadingthetransmitter
orinterrogatingthereceivers.Thedatabusinterfaceswith
CMOSandTTL.

Timingofallthecircuitrybeginswiththemasterclockinput,
CLK.ForARINC429applications,themasterclock
frequencyis1MHz.

Eachindependentreceivermonitorsthedatastreamwitha
samplingrate10timesthedatarate.Thesamplingrateis
softwareselectableateither1MHzor125KHz.Theresults
ofaparitycheckareavailableasthe32ndARINCbit.The
HI-8282Aexaminesthenullanddatatimingsandwillreject
erroneouspatterns.Forexample ,witha125KHzclock
selection,thedatafrequencymustbebetween10.4KHz
and15.6KHz.

ThetransmitterhasaFirstIn,FirstOut(FIFO)memoryto
store8ARINCwordsfortransmission.Thedatarateofthe
transmitterissoftwareselectablebydividingthemaster
clock,CLK,byeither10or80.Themasterclockisusedto
setthetimingoftheARINCtransmissionwithintherequired
resolution.

APPLICATIONS

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Avionicsdatacommunication
Serialtoparallelconversion
Paralleltoserialconversion

FEATURES

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ARINCspecification429compatible
16-Bitparalleldatabus
DirectreceiverinterfacetoARINCbus
Timingcontrol10timesthedatarate
Selectabledataclocks
ReceivererrorrejectionperARINC

specification429
Automatictransmitterdatatiming
Selftestmode
Parityfunctions
Lowpower,single5voltsupply
Industrial&fullmilitarytemperatureranges

HOLTINTEGRATEDCIRCUITS

1(DS8282ARev.New) 05/01

May2001

44-PinPlasticQuadFlatPack(PQFP)

(Seepage10foradditionalPackagePinConfigurations)

33-N/C
32-N/C
31­30-ENTX
29­28-429DO
27-TX/R
26­25­24-BD00
23-BD01

CWSTRX
429DO

PL2
PL1

N/C-1

-2

-3

SEL-4

-5

-6
BD15-7
BD14-8
BD13-9
BD12-10

BD11-11

D/R1
D/R2

EN1
EN2

HI-8282APQI

&

HI-8282APQT

SYMBOLFUNCTIONDESCRIPTION

VCCPOWER+5V±5%
429DI1(A)INPUTARINCreceiver1positiveinput
429DI1(B)INPUTARINCreceiver1negativeinput
429DI2(A)INPUTARINCreceiver2positiveinput
429DI2(B)INPUTARINCreceiver2negativeinput

OUTPUTReceiver1datareadyflag
OUTPUTReceiver2datareadyflag

SELINPUTReceiverdatabyteselection(0=BYTE1)(1=BYTE2)

INPUTDataBuscontrol,enablesreceiver1datatooutputs

INPUTDataBuscontrol,enablesreceiver2datatooutputsifishigh
BD15I/ODataBus
BD14I/ODataBus
BD13I/ODataBus
BD12I/ODataBus
BD11I/ODataBus
BD10I/ODataBus
BD09I/ODataBus
BD08I/OData Bus
BD07I/ODataBus
BD06I/ODataBus

GNDPOWER0V
BD05I/ODataBus
BD04I/ODataBus
BD03I/ODataBus
BD02I/ODataBus
BD01I/ODataBus
BD00I/ODataBus

INPUTLatchenableforbyte1enteredfromdatabustotransmitterFIFO.
INPUTLatchenableforbyte2enteredfromdatabustotransmitterFIFO.Mustfollow

TX/ROUTPUTTransmitterreadyflag.GoeslowwhenARINCwordloadedintoFIFO.Goeshigh

aftertransmissionandFIFOempty.

429DOOUTPUT"ONES"dataoutputfromtransmitter.

OUTPUT"ZEROES"dataoutputfromtransmitter.

ENTXINPUTEnableTransmission

INPUTClockforcontrolwordregiste r

CLKINPUTMasterClockinput

TXCLKOUTPUTTransmitterClockequaltoMasterClock(CLK),dividedbyeither10or80.

INPUTMasterReset,activelow

D/R1
D/R2

EN1
EN2EN1

PL1
PL2PL1.

429DO

CWSTR

MR

PINDESCRIPTION

HI-8282A

HOLTINTEGRATEDCIRCUITS

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HI-8282A

FUNCTIONALDESCRIPTION

DATA

BUSFUNCTIONCONTROLDESCRIPTION

PIN

Ifenabled,aninternalconnection

BDO5SELFTEST0=ENABLEismadepassing429DOand

tothereceiverlogicinputs

RECEIVER1Ifenabled,ARINCbits9and,

BDO6DECODER1=ENABLE10mustmatchthenexttwo

controlwordbits

IfReceiver1Decoderis

BDO7--enabled,theARINCbit9

mustmatchthisbit

IfReceiver1Decoderis

BDO8--enabled,theARINCbit10

mustmatchthisbit

RECEIVER2Ifenabled,ARINCbits9and

BDO9DECODER1=ENABLE10mustmatchthenexttwo

controlwordbits

IfReceiver2Decoderis

BD10--enabled,thenARINCbit9

mustmatchthisbit

IfReceiver2Decoderis

BD11--enabled,thenARIN Cbit10

mustmatchthisbit

INVERTLogic0enablesnormaloddparity

BD12XMTR1=ENABLEandLogic1enablesevenparity

PARITYoutputintransmitter32ndbit

BD13XMTRDATA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainXMTRdataclock

BD14RCVRDTA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainRCVRdataclock

429DO

CONTROLWORDREGISTER

TheHI-8282Acontains10dataflipflopswhoseDinputsarecon­nectedtothedatabusandclocksconnectedto.Each
flipflopprovidesoptionstotheuserasfollows:

CWSTR

THERECEIVERS

ARINCBUSINTERFACE

Figure1showstheinputcircuitforeachreceiver.TheARINC429
specificationrequiresthefollowingdetectionlevels:

TheHI-8282Aguaranteesrecognitionoftheselevelswithacommon
modeVoltagewithrespecttoGNDlessthan±5Vfortheworstcase
condition(4.75Vsupplyand13vsignallevel).

Thetolerancesinthedesignguaranteedetectionoftheabove
levels,sotheactualacceptancerangesareslightlylarger.Ifthe
ARINCsignalisoutoftheactualacceptanceranges,includingthe
nulls,thechiprejectsthedata.

STATEDIFFERENTIALVOLTAGE

ONE+6.5Voltsto+13Volts

NULL+2.5Voltsto-2.5Volts

ZERO-6.5Voltsto-13Volts

BYTE2

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC29282726252423222120191817161514

BIT

ARINC429DATAFORMAT

Thefollowingtableshowsthebitpositionsinexchangingdatawith
thereceiverorthetransmitter.ARINCbit1isthefirstbit
transmittedorreceived.

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC13121110931303212345678

BIT

BYTE1

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HI-8282A

RECEIVERLOGICOPERATION

BITTIMING

BITRATE

PULSERISETIME

PULSEFALLTIME

PULSEWIDTH

Figure2showsablockdiagramofthelogicsectionofeachreceiver.

TheARINC429specificationcontainsthefollowingtiming
specificationforthereceiveddata:

100KBPS±1%12K-14.5KBPS

1.5±0.5µsec10±5µsec

1.5±0.5µsec10±5µsec
5µsec±5%34.5to41.7µsec

AgaintheHI-8282Aacceptssignalsthatmeetthesespecifications
andrejectsoutsidethetolerances.Thewaythelogicoperation
achievesthisisdescribedbelow:

1.Keytotheperformanceofthetimingcheckinglogicisanac­curate1MHzclocksource.Lessthan0.1%erroris
recommmended.

2.Thesamplingshiftregistersare10b itslongandmustshow
threeconsecutiveOnes,ZerosorNullstobeconsideredvalid
data.Additionally,fordatabits,theOneorZerointheupperbits
ofthesamplingshiftregistersmustbefollowedbyaNullinthe
lowerbitswithinthedatabittime.ForaNullinthewordgap,
threeconsecutiveNullsmustbefoundinboththeupperand
lowerbitsofthesamplingshiftregister.Inthismannerthemini­mumpulsewidthisguaranteed.

HIGHSPEEDLOWSPEED

FUNCTIONALDESCRIPTION(con't)

3.Eachdatabitmustfollowitspredecessorbynotlessthan
8samplesandnomorethan12samples.Inthismannerthe
bitrateischecked.Withexactly1MHzinputclockfrequency,
theacceptabledatabitratesareasfollows:

83KBPS10.4KBPS

125KBPS15.6KBPS

4.TheWordGaptimersamplestheNullshiftregisterevery
10inputclocks(80forlowspeed)afterthelastdatabitofa
validreception.IftheNullispresent,theWordGapcounteris
incremented.Acountof3willenablethenextreception.

ThereceiverparitycircuitcountsOnesreceived,includingthe
paritybit,ARINCbit32.Iftheresu ltisodd,then"0"willappearin
the32ndbit.

HIGHSPEEDLOWSPEED

DATABITRATEMIN

DATABITRATEMAX

RECEIVERPARITY

RETRIEVINGDATA

Once32validbitsarerecognized,thereceiverlogicgeneratesan
EndofSequence(EOS).Ifthereceiverdecoderisenabledand
the9thand10thARINCbitsmatchthecontrolwordprogrambits
orifthereceiverdecoderisdisabled,thenEOSclocksthedata
readyflagflipfloptoa"1",or(orboth)willgolow.The
dataflagforareceiverwillremainlowuntilafterARINC
bytesfromthatreceiverareretrieved.Thisisaccomplishedby
activatingwithSEL,thebyteselector,lowtoretrievethefirst
byteandactivatingwithSELhightoretrievethesecondbyte.

retrievesdatafromreceiver1andret rievesdatafrom

receiver2.
IfanotherARINCwordisreceived,andanewEOSoccursbefore

thetwobytesareretrieved,thedataisoverwrittenbythenew
word.

D/R1D/R2

EN

EN

ENIEN2

both

SEL

EN

D/R

DECODER
CONTROL

BITS

/

MUX

CONTROL

LATCH

ENABLE

CONTROL

32TO16DRIVER

32BITLATCH

32BITSHIFTREGISTER

TOPINS

CONTROL

BITBD14

CLOCK

OPTION

CLOCK

CLK

BIT

COUNTER

AND

ENDOF

SEQUENCE

PARITY
CHECK

32ND

BIT

DATA

BITCLOCK

EOS

WORDGAP

WORDGAP

TIMER

BITCLOCK

END

START

SEQUENCE

CONTROL

ERROR

CLOCK

ERROR

DETECTION

SHIFTREGISTER

SHIFTREGISTER

NULL

ZEROS

SHIFTREGISTER

ONES

EOS

BITS9&10

FIGURE2. RECEIVERBLOCKDIAGRAM

HOLTINTEGRATEDCIRCUITS

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HI-8282A

TRANSMITTER

AblockdiagramofthetransmittersectionisshowninFigure3.

TheFIFOisloadedsequentiallybyfirstpulsingtoloadbyte1
andthentoloadbyte2.Thecontrollogicautomaticallyloads
the31bitwordinthenextavailablepositionoftheFIFO.IfTX/R,
thetransmitterreadyflagishigh(FIFOempty),then8words,
each31bitslong,maybeloaded.IfTX/Rislow,thenonlythe
availablepositionsmaybeloaded.Ifall8positionsarefull,the
FIFOignoresfurtherattemptstoloaddata.

WhenENTXgoeshigh,enablingtransmission,theFIFO
positionsareincrementedwiththetopregisterloading intothe
datatransmissionshiftregister.Within2.5dataclocksthefirst
databitappearsateither429DOor.The31bitsinthe
datatransmissionshiftregisterarepresentedsequentiallytothe
outputsintheARINC429formatwiththefollowingtiming:

ARINCDATABITTIME10Clocks80Clocks

DATABITTIME5Clocks40Clocks
NULLBITTIME5Clocks40Clocks

WORDGAPTIME40Clocks320Clocks

Thewordcounterdetectswhenallloadedpositionsare
transmittedandsetsthetransmitterreadyflag,TX/R,high.

FIFOOPERATION

DATATRANSMISSION

PL1

PL2

429DO

HIGHSPEEDLOWSPEED

TRANSMITTERPARITY

TheparitygeneratorcountstheONESinthe31-bitword.Ifthe
BD12controlwordbitissetlow,the32ndbittransmittedwillmake
parityodd.Ifthecontrolbitishightheparityiseven.

IftheBD05controlwordbitissetlow,429DOorbecome
inputstothereceiverbypassingtheinterfacecircuitry.

Thetworeceiversareindependentofthetransmitter.Therefore,
controlofdataexchangesarestrictlyattheoptionoftheuser.The
onlyrestrictionsare:

1.Thereceiveddatamaybeoverwrittenifnotretrieved
withinoneARINCwordcycle.

2.TheFIFOcanstore8wordsmaximumandignores
attemp tstoloadadditiondataiffull.

3.Byte1ofthetransmitterdatamustbeloadedfirst.

4.Eitherbyteofthereceiveddatamayberetrievedfirst.
Bothbytesmustberetrievedtoclearthedatareadyflag.

5.AfterENTX,transmissionenable,goeshighitcannotgo
lowuntilTX/R,transmitterreadyflag,goeshigh.Otherwise,
oneARINCwordislostduringtransmission.

SELFTEST

SYSTEMOPERATION

429DO

HOLTINTEGRATEDCIRCUITS

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