HOLT HI-8281PJT, HI-8281PJI, HI-8281CJT, HI-8281CJI Datasheet

January2001

HI-8281

GENERALDESCRIPTION

TheHI-8281devicefromHoltIntegratedCircuitsisasilicon
gateCMOSdeviceforinterfacinga16-bitparalleldatabus
directlytotheARINC429serialbus.Thedeviceprovides
tworeceivers,anindependenttransmitterandlinedriver
capabilityinasinglepackage.Thereceiverinputcircuitry
andlogicaredesignedtomeettheARINC429
specificationsforloading,leveldetection,timing,and
protocol.ThetransmittersectionprovidestheARINC429
communicationprotocolandthelinedrivercircuitsprovide
theARINC429outputlevels.

The16-bitparalleldatabusexchangesthe3 2-bitARINC
datawordintwostepswheneitherloadingthetransmitter
orinterrogatingthereceivers.Thedatabusinterfaceswith
CMOSandTTL.

Timingofallthecircuitrybeginswiththemasterclockinput,
CLK.ForARINC429applications,themasterclock
frequencyis1MHz.

Eachindependentreceivermonitorsthedatastreamwitha
samplingrate10timesthedatarate.Thesamplingrateis
softwareselectableateither1MHzor125KHz.Theresults
ofaparitycheckareavailableasthe32ndARINCbit.The
HI-8281examinesthenullanddatatimingsandwillreject
erroneouspatterns.Forexam ple,witha125KHzclock
selection,thedatafrequencymustbebetween10.4KHz
and15.6KHz.

FEATURES

!

ARINCspecification429compatible

!

Directreceiverandtransmitterinterfaceto
ARINCbusinasingledevice.

!

16-Bitparalleldatabus.

!

Timingcontrol10timesthedatarate

!

Selectabledataclocks

!

ReceivererrorrejectionperARINC
specification429

!

Automatictransmitterdatatiming

!

Selftestmode

!

Parityfunctions

!

Lowpower

!

Industrial&fullmilitarytemperatureranges

PINCONFIGURATION (TopView)

ThetransmitterhasaFirstIn,FirstOut(FIFO)memoryto
store8ARINCwordsfortransmission.Thedatarateofthe
transmitterissoftwareselectablebydividingthemaster
clock,CLK,byeither10or80.Themasterclockisusedto
setthetimingoftheARINCtransmissionwithintherequired
resolution.

APPLICATIONS

!

Avionicsdatacommunication

!

Serialtoparallelconversion

!

Paralleltoserialconversion

HOLTINTEGRATEDCIRCUITS

(Seepage4-27foradditionalpinconfiguration)

1(DS8281Rev.A)01/01

HI-8281

SIGNALFUNCTIONDESCRIPTION

VCCPOWER+5V±5%

V+POWER+12V±5%or+15V±10%

V-POWER-12V±5%or-15V±10%
429DI1(A)INPUTARINCreceiver1positiveinput
429DI1(B)INPUTARINCreceiver1negativeinput
429DI2(A)INPUTARINCreceiver2positiveinput
429DI2(B)INPUTARINCreceiver2negativeinput

D/R1
D/R2

SELINPUTReceiverdatabyteselection(0=BYTE1)(1=BYTE2)
EN1

EN2EN1
BD15I/ODataBus
BD14I/ODataBus
BD13I/ODataBus
BD12I/ODataBus
BD11I/ODataBus
BD10I /ODataBus
BD09I/ODataBus
BD08I/ODataBus
BD07I/ODataBus
BD06I/ODataBus

GNDPOWER0V-bothpinsmustbeconnected
BD05I/ODataBus
BD04I/ODataBus
BD03I/ODataBus
BD02I/ODataBus
BD01I/ODataBus
BD00I/ODataBus

TX/ROUTPUTTransmitterreadyflag.GoeslowwhenARINCwordloadedintoFIFO.Goeshigh

PL1

PL2PL1
TXA(OUT)OUTPUTLinedriveroutput-Aside
TXB(OUT)OUTPUTLinedriveroutput-Bside

ENTXINPUTEnableTransmission

CWSTR

CLKINPUTMasterClockinput

TXCLKOUTPUTTransmitterClockequaltoMasterClock(CLK),dividedbyeither10or80.

MR

SLP1.5INPUTLogicinputtocontroltheslopeofthedifferentialoutputsignal.HIGH=1.5s

OUTPUTReceiver1datareadyflag
OUTPUTReceiver2datareadyflag

INPUTDataBuscontrol,enablesreceiver1datatooutputs
INPUTDataBuscontrol,enablesreceiver2datatooutputsifishigh

AftertransmissionandFIFOempty.
INPUTLatchenableforbyte1enteredfromdatabustotransmitterFIFO.
INPUTLatchenableforbyte2enteredfromdatabustotransmitterFIFO.Mustfollow.

INPUTClockforcontrolwordregister

INPUTMasterRes et,activelow

µ

HOLTINTEGRATEDCIRCUITS

2

HI-8281

FUNCTIONALDESCRIPTION

CONTROLWORDREGISTER

TheHI-8282contains10dataflipflopswhoseDinputsarecon­nectedtothedatabusandclocksconnectedto.Each
flipflopprovidesoptionstotheuserasfollows:

DATA

BUSFUNCTIONCONTROLDESCRIPTION

PIN

Ifenabled,aninternalconnection

BDO5SELFTEST0=ENABLEismadepassing429DOand

429DO

RECEIVER1Ifenabled,ARINCbits9and,

BDO6DECODER1=ENABLE10mustmatchthenexttwo

IfReceiver1Decoderis

BDO7--enabled,theARINCbit9

IfReceiver1Decoderis

BDO8--enabled,theARINCbit10

RECEIVER2Ifenabled,ARINCbits9and

BDO9DECODER1=ENABLE10mustmatchthenexttwo

IfReceiver2Decoderis

BD10--enabled,thenARINCbit9

IfReceiver2Decoderis

BD11--enabled,thenARIN Cbit10

INVERTLogic0enablesnormaloddparity

BD12XMTR1=ENABLEandLogic1enablesevenparity

PARITYoutputintransmitter32ndbit

BD13XMTRDATA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainXMTRdataclock

BD14RCVRDTA0=÷10CLKisdividedeitherby10or

CLKSELECT1=÷8080toobtainRCVRdataclock

CWSTR

tothereceiverlogicinputs

controlwordbits

mustmatchthisbit

mustmatchthisbit

controlwordbits

mustmatchthisbit

mustmatchthisbit

ARINC429DATAFORMAT

Thefollowingtableshowsthebitpositionsinexchangingdatawith
thereceiverorthetransmitter.ARINCbit1isthefirstbit
transmittedorreceived.

BYTE1

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC13121110931303212345678

BIT

BYTE2

DATABDBDBDBDBDBDBDBDBDBDBDBDBDBDBDBD

BUS15141312111009080706050403020100

ARINC29282726252423222120191817161514

BIT

THERECEIVERS

ARINCBUSINTERFACE

Figure1showstheinputcircuitforeachreceiver.TheARINC429
specificationrequiresthefollowingdetectionlevels:

STATEDIFFERENTIALVOLTAGE

ONE+6.5Voltsto+13Volts

NULL+2.5Voltsto-2.5Volts

ZERO-6.5Voltsto-13Volts

TheHI-8282guaranteesrecognitionoftheselevelswithacommon
modeVoltagewithrespecttoGNDlessthan±4Vfortheworstcase
condition(4.75Vsupplyand13Vsignallevel).

Thetolerancesinthedesignguaranteedetectionoftheabove
levels,sotheactualacceptancerangesareslightlylarger.Ifthe
ARINCsignalisoutoftheactualacceptanceranges,includingthe
nulls,thechiprejectsthedata.

HOLTINTEGRATEDCIRCUITS

3

HI-8281

FUNCTIONALDESCRIPTION(con't)

RECEIVERLOGICOPERATION

Figure2showsablockdiagramofthelogicsectionofeachreceiver.

BITTIMING

TheARINC429specificationcontainsthefollowingtiming
specificationforthereceiveddata:

HIGHSPEEDLOWSPEED

BITRATE

PULSERISETIME

PULSEFALLTIME

PULSEWIDTH

AgaintheHI-8282acceptssignalsthatmeetthesespecifications
andrejectsoutsidethetolerances.Thewaythelogicoperation
achievesthisisdescribedbelow:

1.Keytotheperformanceofthetimingcheckinglogicisanac­curate1MHzclocksource.Lessthan0.1%errorisrecom­mended.

2.Thesamplingshiftregistersare10bi tslongandmustshow
threeconsecutiveOnes,ZerosorNullstobeconsideredvalid
data.Additionally,fordatabits,theOneorZerointheupperbits
ofthesamplingshiftregistersmustbefollowedbyaNullinthe
lowerbitswithinthedatabittime.ForaNullinthewordgap,
threeconsecutiveNullsmustbefoundinboththeupperand
lowerbitsofthesamplingshiftregister.Inthismannerthemini­mumpulsewidthisguaranteed.

100KBPS±1%12K-14.5KBPS

1.5±0.5µsec10±5µsec

1.5±0.5µsec10±5µsec
5µsec±5%34.5to41.7µsec

TOPINS

3.Eachdatabitmustfollowitspredecessorbynotlessthan
8samplesandnomorethan12samples.Inthismannerthe
bitrateischecked.Withexactly1MHzinputclockfrequency,
theacceptabledatabitratesareasfollows:

HIGHSPEEDLOWSPEED

DATABITRATEMIN

DATABITRATEMAX

83KBPS10.4KBPS

125KBPS15.6KBPS

4.TheWordGaptimersamplestheNullshiftregisterevery
10inputclocks(80forlowspeed)afterthelastdatabitofa
Validreception.IftheNullispresent,theWordGapcounter
Isincremented.Acountof3willenablethenextreception.

RECEIVERPARITY

ThereceiverparitycircuitcountsOnesreceived,includingthe
paritybit,ARINCbit32.Iftheresu ltisodd,then"0"willappearin
the32ndbit.

RETRIEVINGDATA

Once32validbitsarerecognized,thereceiverlogicgeneratesan
EndofSequence(EOS).Ifthereceiverdecoderisenabledand
the9thand10thARINCbitsmatchthecontrolwordprogrambits
orifthereceiverdecoderisdisabled,thenEOSclocksthedata
readyflagflipfloptoa"1",or(orboth)willgolow.The
dataflagforareceiverwillremainlowuntilafterARINCbytes

D/R1D/R2

both
fromthatreceiverareretrieved.Thisisaccomplishedby
activatingwithSEL,thebyteselector,lowtoretrievethefirst
byteandactivatingwithSELhightoretrievethesecondbyte.
ENIEN2

EN

EN

retrievesdatafromreceiver1andret rievesdatafrom

receiver2.
IfanotherARINCwordisreceived,andanewEOSoccursbefore

thetwobytesareretrieved,thedataisoverwrittenbythenew
word.

DECODER
CONTROL

BITS

SEL

EN

D/R

ZEROS

ONES

NULL

MUX

CONTROL

LATCH

ENABLE

/

CONTROL

BITS9&10

EOS

SHIFTREGISTER

SHIFTREGISTER

SHIFTREGISTER

32TO16DRIVER

32BITLATCH

32BITSHIFTREGISTER

DATA

BITCLOCK

WORDGAP

START

CONTROL

BITBD14

PARITY
CHECK

WORDGAP

SEQUENCE

CONTROL

DETECTION

TIMER

ERROR

32ND

CLOCK

OPTION

CLOCK

BIT

COUNTER

AND

BIT

SEQUENCE

EOS

BITCLOCK

END

ERROR

CLOCK

ENDOF

CLK

FIGURE2. RECEIVERBLOCKDIAGRAM

HOLTINTEGRATEDCIRCUITS

4

HI-8281

TRANSMITTER

AblockdiagramofthetransmittersectionisshowninFigure3.

FIFOOPERATION

TheFIFOisloadedsequentiallybyfirstpulsingtoloadbyte1
andthentoloadbyte2.Thecontrollogicautomaticallyloads
the31bitwordinthenextavailablepositionoftheFIFO.IfTX/R,
thetransmitterreadyflagishigh(FIFOempty),then8words,
each31bitslong,maybeloaded.IfTX/Rislow,thenonlythe
availablepositionsmaybeloaded.Ifall8positionsarefull,the
FIFOignoresfurtherattemptstoloaddata.

PL2

DATATRANSMISSION

WhenENTXgoeshigh,enablingtransmission,theFIFO
positionsareincrementedwiththetopregisterloading intothe
datatransmissionshiftregister.Within2.5dataclocksthefirst
databitappearsateither429DOor.The31bitsinthe
datatransmissionshiftregisterarepresentedsequentiallytothe
outputsintheARINC429formatwiththefollowingtiming:

ARINCDATABITTIME10Clocks80Clocks

DATABITTIME5Clocks40Clocks

NULLBITTIME5Clocks40Clocks

WORDGAPTIME40Clocks320Clocks

429DO

HIGHSPEEDLOWSPEED

PL1

TRANSMITTERPARITY

TheparitygeneratorcountstheONESinthe31-bitword.Ifthe
BD12controlwordbitissetlow,the32ndbittransmittedwillmake
parityodd.Ifthecontrolbitishightheparityiseven.

SELFTEST

IftheBD05controlwordbitissetlow,429DOorbecome
inputstothereceiverbypassingtheinterfacecircuitry.

429DO

SYSTEMOPERATION

Thetworeceiversareindependentofthetransmitter.Therefore,
controlofdataexchangesarestrictlyattheoptionoftheuser.The
onlyrestrictionsare:

1.Thereceiveddatamaybeoverwrittenifnotretrieved
withinoneARINCwordcycle.

2.TheFIFOcanstore8wordsmaximumandignores
attemp tstoloadadditiondataiffull.

3.Byte1ofthetransmitterdatamustbeloadedfirst.

4.Eitherbyteofthereceiveddatamayberetrievedfirst.
Bothbytesmustberetrievedtoclearthedatareadyflag.

Thewordcounterdetectswhenallloadedpositionsare
transmittedandsetsthetransmitterreadyflag,TX/R,high.

5.AfterENTX,transmissionenable,goeshighitcannotgo
lowuntilTX/R,transmitterreadyflag,goeshigh.Otherwise,
oneARINCwordislostduringtransmission.

HOLTINTEGRATEDCIRCUITS

5

HI-8281

LINEDRIVEROPERATION

ThelinedriverintheHI-8281isdesignedtodirectlydrivetheARINC
429bus.ThetwoARINCoutputs(TXA(OUT)andTXB(OUT))
provideadifferentialvoltagetoproducea+10voltOne,a-10volt
Zero,anda0voltNull.Thedeviceincorporatesonboardzenersto
translateinternalCMOSlevelstoARINCspecifiedamplitudes.A
logicinput(SLP1.5)isprovidedtocontroltheslopeofthedifferential
outputsignal.Noadditionalhardwareisrequiredtocontrolthe
slope.AHIGHonSLP1.5causesaslopeof1.5sontheARINC
outputs;aLOWonSLP1.5causesaslopeof10s.Timingissetby
on-chipresistor andcapacitorandtestedtobewithinARINC
requirements.TheHI-8281has37.5ohmsinserieswitheachline
driveroutput.

TXA(OUT)

ARINCBIT

TXB(OUT)

DATA

NULL

BIT30

DATA

µ

BIT31

µ

NULL

DATA

REPEATEROPERATION

Repeatermodeofoperationallowsadatawordthathasbeen
receivedbytheHI-8281tobeplaceddirectlyintoitsFIFOfor
transmission.Repeateroperationissimilartonormalreceiver
operation.I nnormaloperation,eitherbyteofareceiveddata
wordmaybereadfromthereceiverlatchesfirstbyuseofSEL
input.Duringrepeateroperationhowever,thelowerbyteofthe
datawordmustbereadfirst.Thisisnecessarybecause,asthe
dataisbeingread,itisalsobeingloadedintotheFIFOandthe
transmitterFIFOisalwaysloadedwiththelowerbyteofthedata
wordfirst.Signalflowforrepeateroperationisshowninthe
TimingDiagramssection.

NULL

BIT32

WORDGAP

BIT1

NEXTWORD

DATABUS

CWSTR

DATABUS

VALID

t

CWSET

t

CWSTR

t

D/R

t

SELEN

t

D/REN

t

ENDATA

t

ENSEL

t

CWHLD

t

DATAEN

t

ENEN

t

ENDATA

t

SELEN

t

END/R

t

EN

t

ENSEL

t

DATAEN

HOLTINTEGRATEDCIRCUITS

6

HI-8281

DATABUS

PL1

PL2

TX/R

PL2

TX/R

ENTX

TXA(OUT)

TXB(OUT)

t

PL2EN

t

ENDAT

t

PL

ARINCBIT

+5V

BYTE1VALID

t

DWSET

DATA

BIT1

t

DWHLD

t

PL12

ARINCBIT

DATA

BIT2

-5V
+5V

t

PL

BYTE2VALID

t

DWSET

t

DWHLD

t

t

PL12

TX/R

t

DTX/R

ARINCBIT

+5V

DATA

BIT32

t

ENTX/R

V

DIFF

(TXA(OUT)-TXB(OUT))

onelevel

-5V

t

+10V

90%

10%

t

rx

fx

zerolevel

-10V

t

rx

nulllevel

t

fx

10%

90%

-5V

+10V

HOLTINTEGRATEDCIRCUITS

7

HI-8281

429DI

D/R

EN

SEL

PL1

PL2

TX/R

ENTX

TXA(OUT)
TXB(OUT)

BIT32

t

D/R

t

DON'TCARE

SELEN

t

D/REN

t

ENPL

t

END/R

t

EN

t

PLEN

t

ENEN

t

ENSEL

t

ENPL

t

EN

t

SELEN

t

TX/REN

t

PLEN

t

TX/R

t

ENSEL

t

ENDAT

DON'TCARE

BIT1 BIT32

t

DTX/R

t

ENTX/R

t

NULL

HOLTINTEGRATEDCIRCUITS

8

HI-8281

SupplyVoltagesVcc-0.3Vto+7V

V+20V

V--20V
Voltageatpins4,5,6and7-29Vto+29V
Voltageatpin38-0.3toV++0.3V
Voltageatanyotherpin-0.3VtoVcc+0.3V

PowerDissipationat25C

PlasticPLCC1.5W,derate10mW/C

CeramicJ-LEADCERQUAD1.0W,derate7mW/
DCCurrentDrainperpin±10mA
StorageTemperatureRange:-65°Cto+150°C
OperatingTemperatureRange:(Industrial)-40°Cto+85°C

(Military)-55°Cto+125°C

NOTE:Stressesabovethoselistedunder"AbsoluteMaximumRatings"maycausepermanentdamagetothedevice.Thesea restressratingsonly.
Functionaloperationofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperationalsection softhespecificationsisnotimplied.
Exposuretoabsolutemaximumratingconditionsforextendedperiodsmayaffectdevicereliability.

Vcc=5V±5%,GND=0V,TA=OperatingTemperatureRange(unlessotherwisespecified).V+=12Vto15V,V-=-12Vto-15V,

LIMITS

PARAMETERCONDITIONSUNITSYMBOL

ARINCINPUTS-Pins4,5,6&7

DifferentialInputVoltage:ONEVPins4to5,6to7:Common6.510.013.0V

ZEROVmodevoltagelessthan±4V-13.0-10.0-6.5V

NULLVwithrespecttoGND-2.502.5V

InputResistance:DifferentialR12K

ToGNDR1227K

ToVccR1227K

IH

IL

NUL

I
G
H

MINTYPMAX

°
°C

InputCurrent:InputSinkI200µA

InputSourceI-450µA

InputCapacitance:DifferentialCPins4to5,6to720pF

(Guaranteedbutnottested)ToGNDC20pF

ToVccC20pF

IH
IL

I
G
H

BI-DIRECTIONALINPUTS-Pins13-22,24-29

InputVoltage:InputVoltageHIV2.1V

InputVoltageLOV0.7V

InputCurrent:InputSinkI1.5µA

InputSourceI-1.5µA

IH

IL

IH
IL

OTHERINPUTS-Pins1,8-12,30,31,39,40&43

InputVoltage:InputVoltageHIV3.5V

InputVoltageLOV0.7V

InputCurrent:InputSinkI10µA

I nputSourceI-20

IH

IL

IH
IL

INPUT-SLP1.5,PIN38

InputVoltageInputVoltageHI2.1-V+V

InputVoltageLOV

InputCurrentInputSink=0V0.1

InputSourceIV=5V0.1µA

V

IH

IL

IVµA

IHIN
ILIN

--0.5V

HOLTINTEGRATEDCIRCUITS

9

HI-8281

Vcc=5V±5%,V+=12Vto15V,V-=-12Vto-15V,GND=0V,TA=OperatingTemperatureRange(unlessotherwisespecified).

PARAMETERCONDITIONSUNITSYMBOL

ARINCOUTPUTS-Pins35&36

ARINCoutputvoltage

OneorzeroVnoloadandmagnitudeatpin4.505.005.50V
NullV-0.250.25V

DOUt

NOUT""""""

LIMITS

MINTYPMAX

ARINCoutputcurrentI80mA

OUT

OTHEROUTPUTS-Pins13-22,24-29,32&34

OutputVoltage:Logic"1"OutputVoltageVI=-1.5mA2.7V

Logic"0"OutputVoltageVI=1.8mA0.4V

OutputCurrent:OutputSinkIV=0.4V3.0mA

(Bi-directionalPins)OutputSourceIV=V-0.4V1.5mA

OutputCurrent:OutputSinkIV=0.4V3.6mA
(AllOtherOutputs)OutputSourceIV=V-0.4V1.5mA

OutputCapacitance:C15pF

OHOH

OLOL

OLOUT

OHOUTCC

OLOUT
OHOUTCC

O

OperatingSupplyCurrent

VCC,Pin3:I20mA
V+,Pin37:I16mA
V-,Pin34:I16mA

CC1

DD1

EE1

HOLTINTEGRATEDCIRCUITS

10

HI-8281

Vcc=5V,V+=12Vto15V,V-=-12Vto-15V,GND=0V,TA=Oper.Temp.Rangeandfclk=1MHz0.1%with60/40dutycycle+

PARAMETERSYMBOLUNITS

LIMITS

MINTYPMAX

CONTROLWORDTIMING

PulseWidth-t130ns

Setup-DATABUSValidtoHIGHt140ns

Hold-HIGHtoDATABUSHi-Zt0ns

CWSTR

CWSTR

CWSTR

CWSTR
CWSET
CWHLD

RECEIVERTIMING

Delay-StartARINC32ndBittoLOW:HighSpeedt16µs

Delay-LOWtoHIGHt200ns

Delay-L0WtoDATABUSValidt200ns

Delay-HIGHtoDATABUSHi-Zt30ns

Spacing-HIGHtonextL0Wt50ns

D/R

LowSpeedt128µs

Delay-LOWtoL0Wt0ns

D/REN

END/R

Setup-SELtoL0Wt20ns

Hold-SELtoHIGHt50ns

EN

EN

EN

EN

PulseWidth-ort240ns

EN1EN2

ENEN

D/R
D/R

D/REN
END/R

SELEN
ENSEL

ENDATA
DATAEN

EN

ENEN

FIFOTIMING

PulseWidth-ort200ns

PL1PL2

PL

Setup-DATABUSValidtoHIGHt110ns

Hold-HIGHtoDATABUSHi-Zt20ns

PL

Spacing-ort0ns

Delay-HIGHtoTX/RLOWt840ns

PL2

PL

PL1PL2

DWSET
DWHLD

PL12

TX/R

TRANSMISSIONTIMING

Spacing-HIGHtoENTXHIGHt0µs

Delay-32ndARINCBittoTX/RHIGHt400ns

Spacing-TX/RHIGH toENTXL0Wt0ns

PL2

PL2EN

DTX/R

ENTX/R

LINEDRIVEROUTPUTTIMING

Delay-ENTXHIGHtoTXA(OUT)orTXB(OUT):HighSpeedt27
Delay-ENTXHIGHtoTXA(OUT)orTXB(OUT):LowSpeedt216

ENDAT
ENDAT

Linedrivertransitiondifferentialtimes:

(HighSpeed,Pin38-Logic1)µs

(LowSpeed,Pin38=Logic0)hightolowt5.01015µs

hightolowt1.01.52.0
lowtohight1.01.52.0

lowtohight5.01015µs

fx

rx

fx

rx

µs
µs

µs

HOLTINTEGRATEDCIRCUITS

11

HI-8281

Vcc=5V,V+=12Vto15V,V-=-12Vto-15V,GND=0V,TA=Oper.Temp.Rangeandfclk=1MHz0.1%with60/40dutycycle+

LIMITS

PARAMETERSYMBOLUNITS

MINTYPMAX

REPEATEROPERATIONTIMING

Delay-LOWtoLOWt0nsENPL ENPL
Hold-HIGHtoHIGHt0ns

PLEN PLEN

Delay-TX/RLOWtoENTXHIGHt0ns

MasterResetPulseWidtht400ns

TX/REN

MR

ARINCDataRateandBitTiming±1%

HOLTINTEGRATEDCIRCUITS

12

HI-8281

ADDITIONALHI-8281PINCONFIGURATION

(Seepage4-23foradditionalpinconfiguration)

ORDERINGINFORMATION

PART
NUMBER

HI-8281PJT

HI-8281CJT 44PINCERQUADJLEAD -55°CTO+125°C

PACKAGE
DESCRIPTION

44PINPLASTICJLEAD
44PINPLASTICJLEAD
44PINCERQUADJLEAD

TEMPERATURE
RANGE

-40°CTO+85°CHI-8281PJI

-55°CTO+125°C

-40°CTO+85°CHI-8281CJI NO SOLDERI

FLOW

BURN

IN

I

T

T

NO
NO

NO SOLDER

LEAD

FINISH

SOLDER
SOLDER

HOLTINTEGRATEDCIRCUITS

13

44-PINPLASTICJ-LEADPLCC

HI-8281PACKAGEDIMENSIONS

inches(millimeters)

ACKAGEYPEPT:

PINNO.1

.045x45°

.690 ± .005

(17.526 ± .127)

SQ.

.172 ± .008

(4.369 ± .203)

(15.494 ± .508)

44-PINCERQUADJ-LEAD

.610 ± .020

PINNO.1IDENT

.653 ± .004

(16.586 ± .102)

SEEDETAIL

.045x45°

.050 ± .005

(1.27 ± .127)

.031 ± .005

SQ.

.017 ± .004

(.432 ± .102)

A

.009
.011

DETAILA

(.787 ± .127)

.015±.002

(.381 ± .051)

.020MIN

(.508 ΜΙΝ )
.025

R

.045

PackageType:

.039 ± .005

(.990 ± .127)

.650 ± .010

(16.510 ± .254)

.019 ± .002

(.483 ± .051)

214443

.688 ± .005

(17.475 ± .127)

MAX.

SQ.

SQ.

.200

MAX.

(5.080)

TYP.

.100 ± .007

(2.540 ± .178)

.050

(1.270)

HOLTINTEGRATEDCIRCUITS

14

.620 ± .012

(15.748 ± .305)