GENERAL DESCRIPTION
The HI-3588 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to an ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, a 32 by 32 Receive FIFO and an analog line
receiver. Receive FIFO status can be monitored using the
programmable external interrupt pin, or by polling the
HI-3588 Status Register. Other features include the ability
to switch the bit-signifiance of ARINC 429 labels. The
ARINC input pins are available with different input resistance values to provide flexibility when adding external
lightning protection circuitry.
The Serial Peripheral Interface minimizes the number of
host interface signals allowing for a small footprint device
which can be interfaced to a wide variety of industrystandard microcontrollers supporting SPI. Alternatively,
the SPI signals may be controlled using just four general
purpose I/O port pins from a microcontroller or custom
FPGA. The SPI and all control signals are CMOS and TTL
compatible and support 3.3V or 5V operation.
The HI-3588 checks received data against ARINC 429
electrical, timing and protocol requirements. ARINC 429
databus timing comes from a 1 MHz clock input,
or an internal counter can derive it from higher clock
frequencies having certain fixed values, possibly the
external host processor clock.
FEATURES
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·
·
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ARINC specification 429 compliant
3.3V or 5.0V logic supply operation
directly to
ARINC 429 bus
Programmable label recognition for 256 labels
32 x 32 Receive Data FIFO
Programmable
High-speed, four-wire Serial Peripheral Interface
Label bit-order control
Parity checking may be disabled to allow 32-bit data
reception
Low power
Industrial & extended temperature ranges
On-chip analog line receiver connects
data rate selection
PIN CONFIGURATIONS (Top View)
HI-3588
July 2009
(DS3588 Rev. C) 07/09
ARINC 429
Receiver with SPI Interface
44 - Pin Plastic 7mm x 7mm
Chip-Scale Package (QFN)
44 - Pin Plastic Quad Flat Pack (PQFP)
HI-3588PCI
HI-3588PCT
44 - N/C
43 - RINA
42 - RINA-40
41 - N/C
40 - VDD
39 - N/C
38 - N/C
37 - N/C
36 - N/C
35 - N/C
34 - N/C
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - N/C
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C-12
N/C-13
N/C-14
SCK-15
N/C-16
GND-17
N/C-18
ACLK - 19
SO-20
N/C-21
N/C-22
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
-9
N/C-10
N/C-11
CS
HI-3588PQI
HI-3588PQT
44 - N/C
43 - RINA
42 - RINA-40
41 - N/C
40 - VDD
39 - N/C
38 - N/C
37 - N/C
36 - N/C
35 - N/C
34 - N/C
N/C - 1
RINB-40 - 2
RINB - 3
N/C - 4
N/C - 5
N/C - 6
MR - 7
SI - 8
-9
N/C - 10
N/C - 11
CS
33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - N/C
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C
N/C - 12
N/C - 13
N/C - 14
SCK - 15
N/C - 16
GND - 17
N/C - 18
ACLK - 19
SO - 20
N/C - 21
N/C - 22
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BLOCK DIAGRAM
PIN DESCRIPTIONS
SIGNAL FUNCTION DESCRIPTION PULL UP / DOWN
RINB INPUT ARINC receiver negative input. Direct connection to ARINC 429 bus
RINB-40 INPUT Alternate ARINC receiver negative input. Requires external 40K ohm resistor
MR INPUT Master Reset. A positive pulse clears the Receiver data FIFO and flags 10K ohm pull-down
SI INPUT SPI interface serial data input 10K ohm pull-down
INPUT Chip select. Data is shifted into SI and out of SO when is low. 10K ohm pull-up
SCK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK 10K ohm pull-down
GND POWER Chip 0V supply. Note BOTH GND pins MUST be connected
ACLK INPUT Master timing source for the ARINC 429 receiver 10K ohm pull-down
SO OUTPUT SPI interface serial data output
RFLAG OUTPUT Goes high when ARINC 429 receiver FIFO is empty (CR15=0), or full (CR15=1)
VDD POWER 3.3V or 5.0V logic power
RINA-40 INPUT Alternate ARINC receiver positive input. Requires external 40K ohm resistor
RINA INPUT ARINC receiver positive input. Direct connection to ARINC 429 bus
CS CS
VDD
SPI
Interface
Control Register
Status Register
ARINC 429
Received
Data FIFO
Label
Filter
ARINC 429
Valid word
Checker
ARINC 429
Line Receiver
Label
Filter
Bit Map
Memory
RINA-40
RINA
RINB
RINB-40
SCK
CS
SI
SO
RFLAG
ACLK
GND
40 Kohm
40 Kohm
ARINC
Clock
Divider
HI-3588
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Example:
one SPI Instruction
op code 07hex data field 02hex
MSB LSB MSB LSB
CS
SCK
SI
TABLE 1. DEFINED INSTRUCTION OP CODES
OP CODE
Hex
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
DATA FIELD
None
None
None
None
8 bits
8 bits
256 bits
8 bits
32 bits
variable
8 bits
16 bits
8 bits
256 bits
None
None
16 bits
DESCRIPTION
No instruction implemented
After the 8th op-code bit is received, perform Master Reset (MR)
, reset all label selections
, set all the label selections
Reset label at address specified in data field
Set label at address specified in data field
Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and
FC hex and reset label FE hex.
Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver operates from the divided ACLK clock. Allowable
values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in
no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock.
Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros
Dump the Receive FIFO. No framing. If held low after last word, the data will
be zeros.
Read the Status Register
Read the Control Register
Read the ACLK divide value programmed previously using op code 07 hex
Read the Label look-up memory table consecutively starting with address FF hex
No instruction implemented
Write the Control Register
After the 8th op-code bit is received
After the 8th op-code bit is received
No instruction implemented
CS
HI-3588
INSTRUCTIONS
Instruction op codes are used to read, write and configure the HI3588A. When goes low, the next 8 clocks at the SCK pin shift
an instruction op code into the decoder, starting with the first
positive edge. The opcodeis fed into the SIpin, most significant bit
first.
For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.
CS
For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
data field bit-length varies with read instructiontype.
Table 1 lists all instructions. Instructions that perform a reset or set
are executed after the last SI bitis received while is still low.CS
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FUNCTIONAL DESCRIPTION
HI-3588
SR
Bit
FUNCTION STATE DESCRIPTION
SR0 Receive FIFO 0
1 Receiver FIFO is empty
Receiver FIFO contains valid data
(LSB) Empty Sets to One when all data has
been read. RFLAG pin reflects the
state of this bit when CR15=”0”
SR1 Receive FIFO 0 Receiver FIFO holds less than 16
Half Full words
1 Receiver FIFO holds at least 16
words
SR2 Receive FIFO 0 Receiver FIFO not full. RFLAG pin
Full reflects the state of this bit when
CR15=”1”
1 Receiver FIFO full. To avoid data
loss, the FIFO must be read within
one ARINC word period
SR3 Not used X Undefined
SR4 Not used X Undefined
SR5 Not used X Undefined
SR6 Not used 0 Always “0”
SR7 Not used 0 Always “0”
(MSB)
CR
Bit
FUNCTION STATE DESCRIPTION
CR0 Receiver 0 Data rate = CLK/10
1 Data rate = CLK/80
(ARINC 429 High-Speed)
(LSB) Data Rate
Select (ARINC 429 Low-Speed)
CR1 ARINC Clock 0 ARINC CLK = ACLK input frequency
Source Select
1 ARINC CLK = ACLK divided by the value
programmed with SPI Instruction 07 hex
CR2 Enable Label 0 Label recognition disabled
Recognition
1 Label recognition enabled
CR3 - X Not used
CR4 Receiver 0 Receiver parity check disabled
Parity Check
Enable 1 Receiver odd parity check enabled
CR5 Receiver 0 Disable receiver. The HI-3588 ignores
Enable all ARINC 429 data bus traffic
1 Normal operation
CR6 Receiver 0 Receiver decoder disabled
Decoder
1 ARINC bits 10 and 9 must match CR7 and CR8
CR7 - - If receiver decoder is enabled,
the ARINC bit 10 must match this bit
CR8 - - If receiver decoder is enabled,
the ARINC bit 9 must match this bit
CR9 - X Not used
CR10 - X Not used
CR11 ARINC Label 0 Label bit order reversed (SeeTable 2)
Bit Order
1 Label bit order same as received
(See Table 2)
CR12 - X Not used
CR13 - X Not used
CR14 - X Not used
CR15 RFLAG 0 FLAG goes high when receive FIFO is empty
(MSB) Definition
1 RFLAG goes high when receive FIFO is full
CONTROL WORD REGISTER
The HI-3588 contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction
0B hex. Each bit of the Control Register has the following function:
STATUS REGISTER
The HI-3588 contains an 8-bit Status Register which can be
interrogated to determine status of the ARINC Receive FIFO. The
Status Register is read using SPI instruction 0A hex. Unused bits
are undefined and may be read as either “1” or “0”. The following
table defines the Status Register bits.
Parity
SDI
Label
Label (LSB)
Label (MSB)
Label
Label
Label
Label
Label
SDI
Parity
SDI
Label
Label (MSB)
Label (LSB)
Label
Label
Label
Label
Label
SDI
ARINC 429 DATA FORMAT
Control Register bit CR11 controls how individual bits in the
received ARINC word are mapped to the HI-3588 SPI data word bits
during data read or write operations. The following table describes
this mapping:
Table 2. SPI / ARINC bit-mapping
SPI
1 2-22 23242526272829303132
Order
. ARINC bit 32 31 - 11 10 912345678
CR11=0 Data
ARINC bit 32 31 - 11 10 987654321
CR11=1 Data
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