HOLT HI-3588 User Manual

GENERAL DESCRIPTION

The HI-3588 from Holt Integrated Circuits is a silicon gate
CMOS device for interfacing a Serial Peripheral Interface
(SPI) enabled microcontroller to an ARINC 429 serial bus.
The device provides one receiver with user-programmable
label recognition for any combination of 256 possible
labels, a 32 by 32 Receive FIFO and an analog line
receiver. Receive FIFO status can be monitored using the
programmable external interrupt pin, or by polling the
HI-3588 Status Register. Other features include the ability
to switch the bit-signifiance of ARINC 429 labels. The
ARINC input pins are available with different input resis­tance values to provide flexibility when adding external
lightning protection circuitry.

The Serial Peripheral Interface minimizes the number of
host interface signals allowing for a small footprint device
which can be interfaced to a wide variety of industry­standard microcontrollers supporting SPI. Alternatively,
the SPI signals may be controlled using just four general
purpose I/O port pins from a microcontroller or custom
FPGA. The SPI and all control signals are CMOS and TTL
compatible and support 3.3V or 5V operation.

The HI-3588 checks received data against ARINC 429
electrical, timing and protocol requirements. ARINC 429
databus timing comes from a 1 MHz clock input,
or an internal counter can derive it from higher clock
frequencies having certain fixed values, possibly the
external host processor clock.

FEATURES

·

·

·

·

·

·

·

·

·

·

·

ARINC specification 429 compliant

3.3V or 5.0V logic supply operation

directly to

ARINC 429 bus
Programmable label recognition for 256 labels

32 x 32 Receive Data FIFO

Programmable

High-speed, four-wire Serial Peripheral Interface

Label bit-order control

Parity checking may be disabled to allow 32-bit data
reception

Low power

Industrial & extended temperature ranges

On-chip analog line receiver connects

data rate selection

PIN CONFIGURATIONS (Top View)

HI-3588

July 2009

(DS3588 Rev. C) 07/09

ARINC 429

Receiver with SPI Interface

44 - Pin Plastic 7mm x 7mm

Chip-Scale Package (QFN)

44 - Pin Plastic Quad Flat Pack (PQFP)

HI-3588PCI

HI-3588PCT

44 - N/C

43 - RINA

42 - RINA-40

41 - N/C

40 - VDD

39 - N/C

38 - N/C

37 - N/C

36 - N/C

35 - N/C

34 - N/C

33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - N/C
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C

N/C-12

N/C-13

N/C-14

SCK-15

N/C-16

GND-17

N/C-18

ACLK - 19

SO-20

N/C-21

N/C-22

N/C - 1

RINB-40 - 2

RINB - 3

N/C - 4
N/C - 5
N/C - 6

MR - 7

SI - 8

-9
N/C-10
N/C-11

CS

HI-3588PQI

HI-3588PQT

44 - N/C

43 - RINA

42 - RINA-40

41 - N/C

40 - VDD

39 - N/C

38 - N/C

37 - N/C

36 - N/C

35 - N/C

34 - N/C

N/C - 1

RINB-40 - 2

RINB - 3

N/C - 4
N/C - 5
N/C - 6

MR - 7

SI - 8

-9
N/C - 10
N/C - 11

CS

33 - N/C
32 - N/C
31 - N/C
30 - GND
29 - N/C
28 - N/C
27 - N/C
26 - N/C
25 - RFLAG
24 - N/C
23 - N/C

N/C - 12

N/C - 13

N/C - 14

SCK - 15

N/C - 16

GND - 17

N/C - 18

ACLK - 19

SO - 20

N/C - 21

N/C - 22

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BLOCK DIAGRAM

PIN DESCRIPTIONS

SIGNAL FUNCTION DESCRIPTION PULL UP / DOWN

RINB INPUT ARINC receiver negative input. Direct connection to ARINC 429 bus

RINB-40 INPUT Alternate ARINC receiver negative input. Requires external 40K ohm resistor

MR INPUT Master Reset. A positive pulse clears the Receiver data FIFO and flags 10K ohm pull-down

SI INPUT SPI interface serial data input 10K ohm pull-down

INPUT Chip select. Data is shifted into SI and out of SO when is low. 10K ohm pull-up

SCK INPUT SPI Clock. Data is shifted into or out of the SPI interface using SCK 10K ohm pull-down

GND POWER Chip 0V supply. Note BOTH GND pins MUST be connected

ACLK INPUT Master timing source for the ARINC 429 receiver 10K ohm pull-down

SO OUTPUT SPI interface serial data output

RFLAG OUTPUT Goes high when ARINC 429 receiver FIFO is empty (CR15=0), or full (CR15=1)

VDD POWER 3.3V or 5.0V logic power

RINA-40 INPUT Alternate ARINC receiver positive input. Requires external 40K ohm resistor

RINA INPUT ARINC receiver positive input. Direct connection to ARINC 429 bus

CS CS

VDD

SPI

Interface

Control Register

Status Register

ARINC 429

Received
Data FIFO

Label
Filter

ARINC 429
Valid word

Checker

ARINC 429

Line Receiver

Label

Filter
Bit Map
Memory

RINA-40

RINA

RINB

RINB-40

SCK

CS

SI

SO

RFLAG

ACLK

GND

40 Kohm

40 Kohm

ARINC

Clock

Divider

HI-3588

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Example:

one SPI Instruction

op code 07hex data field 02hex

MSB LSB MSB LSB

CS

SCK

SI

TABLE 1. DEFINED INSTRUCTION OP CODES

OP CODE

Hex

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

DATA FIELD

None

None

None

None

8 bits

8 bits

256 bits

8 bits

32 bits

variable

8 bits

16 bits

8 bits

256 bits

None

None

16 bits

DESCRIPTION

No instruction implemented

After the 8th op-code bit is received, perform Master Reset (MR)

, reset all label selections

, set all the label selections

Reset label at address specified in data field

Set label at address specified in data field

Starting with label FF hex, consecutively set or reset each label in descending order
For example, a Data Field pattern starting with 1011 will set labels FF, FD, and
FC hex and reset label FE hex.

Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control
Register bit CR1 is set, the ARINC receiver operates from the divided ACLK clock. Allowable
values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in
no clock. Note: ACLK input frequency and division ratio must result in 1 MHz clock.

Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros

Dump the Receive FIFO. No framing. If held low after last word, the data will
be zeros.

Read the Status Register

Read the Control Register

Read the ACLK divide value programmed previously using op code 07 hex

Read the Label look-up memory table consecutively starting with address FF hex

No instruction implemented

Write the Control Register

After the 8th op-code bit is received

After the 8th op-code bit is received

No instruction implemented

CS

HI-3588

INSTRUCTIONS

Instruction op codes are used to read, write and configure the HI­3588A. When goes low, the next 8 clocks at the SCK pin shift
an instruction op code into the decoder, starting with the first
positive edge. The opcodeis fed into the SIpin, most significant bit
first.

For write instructions, the most significant bit of the data word must
immediately follow the instruction op code and is clocked into its
register on the next rising SCK edge. Data word length varies
depending on word type written: 16-bit writes to Control Register,
32-bit ARINC word writes to transmit FIFO or 256-bit writes to the
label-matching enable/disable table.

CS

For read instructions, the most significant bit of the requested data
word appears at the SO pin after the last op code bit is clocked into
the decoder, at the next falling SCK edge. As in write instructions,
data field bit-length varies with read instructiontype.

Table 1 lists all instructions. Instructions that perform a reset or set
are executed after the last SI bitis received while is still low.CS

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FUNCTIONAL DESCRIPTION

HI-3588

SR
Bit

FUNCTION STATE DESCRIPTION

SR0 Receive FIFO 0

1 Receiver FIFO is empty

Receiver FIFO contains valid data

(LSB) Empty Sets to One when all data has

been read. RFLAG pin reflects the
state of this bit when CR15=”0”

SR1 Receive FIFO 0 Receiver FIFO holds less than 16

Half Full words

1 Receiver FIFO holds at least 16

words

SR2 Receive FIFO 0 Receiver FIFO not full. RFLAG pin

Full reflects the state of this bit when

CR15=”1”

1 Receiver FIFO full. To avoid data

loss, the FIFO must be read within
one ARINC word period

SR3 Not used X Undefined

SR4 Not used X Undefined

SR5 Not used X Undefined

SR6 Not used 0 Always “0”

SR7 Not used 0 Always “0”

(MSB)

CR
Bit

FUNCTION STATE DESCRIPTION

CR0 Receiver 0 Data rate = CLK/10

1 Data rate = CLK/80

(ARINC 429 High-Speed)

(LSB) Data Rate

Select (ARINC 429 Low-Speed)

CR1 ARINC Clock 0 ARINC CLK = ACLK input frequency

Source Select

1 ARINC CLK = ACLK divided by the value

programmed with SPI Instruction 07 hex

CR2 Enable Label 0 Label recognition disabled

Recognition

1 Label recognition enabled

CR3 - X Not used

CR4 Receiver 0 Receiver parity check disabled

Parity Check

Enable 1 Receiver odd parity check enabled

CR5 Receiver 0 Disable receiver. The HI-3588 ignores

Enable all ARINC 429 data bus traffic

1 Normal operation

CR6 Receiver 0 Receiver decoder disabled

Decoder

1 ARINC bits 10 and 9 must match CR7 and CR8

CR7 - - If receiver decoder is enabled,

the ARINC bit 10 must match this bit

CR8 - - If receiver decoder is enabled,

the ARINC bit 9 must match this bit

CR9 - X Not used

CR10 - X Not used

CR11 ARINC Label 0 Label bit order reversed (SeeTable 2)

Bit Order

1 Label bit order same as received

(See Table 2)

CR12 - X Not used

CR13 - X Not used

CR14 - X Not used

CR15 RFLAG 0 FLAG goes high when receive FIFO is empty

(MSB) Definition

1 RFLAG goes high when receive FIFO is full

CONTROL WORD REGISTER

The HI-3588 contains a 16-bit Control Register which is used to
configure the device. Control Register bits CR15 - CR0 are loaded
from a 16-bit data value appended to SPI instruction 10 hex. The
Control Register contents may be read using SPI instruction
0B hex. Each bit of the Control Register has the following function:

STATUS REGISTER

The HI-3588 contains an 8-bit Status Register which can be
interrogated to determine status of the ARINC Receive FIFO. The
Status Register is read using SPI instruction 0A hex. Unused bits
are undefined and may be read as either “1” or “0”. The following
table defines the Status Register bits.

Parity

SDI

Label

Label (LSB)

Label (MSB)

Label

Label

Label

Label

Label

SDI

Parity

SDI

Label

Label (MSB)

Label (LSB)

Label

Label

Label

Label

Label

SDI

ARINC 429 DATA FORMAT

Control Register bit CR11 controls how individual bits in the
received ARINC word are mapped to the HI-3588 SPI data word bits
during data read or write operations. The following table describes
this mapping:

Table 2. SPI / ARINC bit-mapping

SPI

1 2-22 23242526272829303132

Order

. ARINC bit 32 31 - 11 10 912345678

CR11=0 Data

ARINC bit 32 31 - 11 10 987654321

CR11=1 Data

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ister, a low bit is clocked. Only one shift register can clock a
high bit for any given sample. All three registers clock low
bits if the differential input voltage is between defined state
voltage bands.

Valid data bits require at least three consecutive One or Zero
samples (three high bits) in the upper half of the Ones or Ze­ros sampling shift register, and at least three consecutive Null
samples (three high bits) in the lower half of the Null sampling
shift register within the data bit interval.

A word gap Null requires at least three consecutive Null sam­ples (three high bits) in the upper half of the Null sampling
shift register and at least three consecutive Null samples
(three high bits) in the lower half of the Null sampling shift reg­ister. This guarantees the minimum pulse width.

3. To validate the receive data bit rate, each bit must follow
its preceding bit by not less than 8 samples and not more
than 12 samples. With exactly 1MHz input clock frequency,
the acceptable data bit rates are:

83K BPS 10.4K BPS

125K BPS 15.6K BPS

4. Following the last data bit of a valid reception, the Word
Gap timer samples the Null shift register every 10 input
clocks (every 80 clocks for low speed). If a Null is present,
the Word Gap counter is incremented. A Word Gap count of 3
enables the next reception.

The receiver parity circuit counts Ones received, including the parity
bit. If the result is odd, a "0" appears in the 32nd bit.

Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). Depending on the state of Control
Register bits CR2, and CR6 through CR8, the received 32-bit
ARINC word is then checked for correct decoding and label match
before it is loaded into the 32 x 32 Receive FIFO. ARINC words that
do not match required 9th and 10th ARINC bit and do not have a
label match are ignored and are not loaded into the Receive FIFO.
The table below describes this operation.

DATA BIT RATE MIN

DATA BIT RATE MAX

HIGH SPEED LOW SPEED

RECEIVER PARITY

RETRIEVING DATA

FUNCTIONAL DESCRIPTION (cont.)

HI-3588

The HI-3588 guarantees recognition of these levels with a common
mode voltage with respect to GND less than ±30V for the worst case
condition (3.15V supply and 13V signal level). Design tolerances
guarantee detection of the above levels, so the actual acceptance
ranges are slightly larger. If the ARINC signal (including nulls) is
outside the differential voltage ranges, the HI-3588 receiver rejects
the data.

Figure 2 is a block diagram showing receiver logic.

The ARINC 429 specification defines the following timing toler­ances for received data:

100K BPS ± 1% 12K -14.5K BPS

1.5 ± 0.5 µsec 10 ± 5 µsec

1.5 ± 0.5 µsec 10 ± 5 µsec
5 µsec ± 5% 34.5 to 41.7 µsec

The HI-3588 accepts signals within these tolerances and rejects
signals outside these tolerances. Receiver logic achieves this as
described below:

1. An accurate 1MHz clock source is required to validate the
receive signal timing. Less than 0.1% error is recommended.

2. The receiver uses three separate 10-bit sampling shift reg­isters for Ones detection, Zeros detection and Null detection.
When the input signal is within the differential voltage range
for any shift register’s state (One Zero or Null) sampling
clocks a high bit into that register. When the receive signal is
outside the differential voltage range defined for any shift reg-

RECEIVER LOGIC OPERATION

BIT TIMING

BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH

HIGH SPEED LOW SPEED

0 X 0 X Load FIFO

1 No 0 X Ignore data

1 Yes 0 X Load FIFO

0 X 1 No Ignore data

0 X 1 Yes Load FIFO

1 Yes 1 No Ignore data

1 No 1 Yes Ignore data

1 No 1 No Ignore data

1 Yes 1 Yes Load FIFO

CR2 ARINC word CR6 ARINC word FIFO

matches bits 10, 9

Enabled match

CR7,8label

ARINC 429 RECEIVER

ARINC BUS INTERFACE

Figure 1 shows the input circuit for the ARINC 429 line receiver. The
ARINC 429 specification requires the following detectionlevels:

ONE +6.5 Volts to +13 Volts

NULL +2.5 Volts to -2.5 Volts

ZERO -6.5Volts to -13 Volts

STATE DIFFERENTIAL VOLTAGE

DIFFERENTIAL

AMPLIFIERS

COMPARATORS

FIGURE 1. ARINC RECEIVER INPUT

RINA-40

RINA

RINB

RINB-40

VDD

GND

VDD

GND

ONE

NULL

ZERO

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HI-3588

FIFO

LOAD

CONTROL

CONTROL BITS

CR2, CR6-8

/

SPI INTERFACE

32 BIT SHIFT REGISTER

CONTROL BITS

CR0, CR1

CLOCK

OPTION

CLOCK

BIT

COUNTER

AND

END OF

SEQUENCE

PARITY
CHECK

32ND

BIT

DATA

BIT CLOCK

WORD GAP

WORD GAP

TIMER

BIT CLOCK

END

START

SEQUENCE

CONTROL

ERROR

CLOCK

ERROR

DETECTION

SHIFT REGISTER

SHIFT REGISTER

NULL

ZEROS

SHIFT REGISTER

ONES

EOS

LABEL /

DECODE

COMPARE

256-BIT

LABEL

LOOK-UP

TABLE

32X32

FIFO

RFLAG

SCK

CS

SI

SO

ACLK

FIGURE 2. RECEIVER BLOCK DIAGRAM

Once a valid ARINC word is loaded into the FIFO, the EOS signal
clocks the Data Ready flip-flop to a "1" and Status Register bit 0
(SR0) to a “0”. The SR0 bit remains low until the Receive FIFO is
empty.Each received ARINC word is retrieved via the SPI interface
using SPI instruction 08 hex to read a single word, or 09 hex to
empty the entire Receive FIFO.

Up to 32 ARINC words may be held in the Receive FIFO. Status
register bit 2 (SR2) goes high when the Receive FIFO is full.
Failure to unload the Receive FIFO when full causes additional
received valid ARINC words to overwrite Receive FIFO location 32.

A FIFO half-full flag (SR1) is high when the Receive FIFO contains
16 or moreARINC words. SR1 may be interrogated by the system’s
external microprocessor, allowing a 16 word data retrieval routine
to be performed.

LABEL RECOGNITION

The user loads the 256-bit label look-up table to specify which 8-bit
incoming ARINC labels are captured by the receiver, and which are
discarded. Setting a “1” in the look-up table enables processing of
received ARINC words containing the corresponding label. A “0” in
the look-up table causes discard of received ARINC words
containing the label. The 256-bit look-up table is loaded using SPI
op codes 02 hex, 03 hex or 06 hex, as described in Table 1. After
the look-up table is initialized, set Control Register bit CR2 to
enable label recognition.

Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
line drivers and line receivers.

If label recognition is enabled, the receiver compares the label in
each new ARINC word against the stored look-up table. If a label
match is found, the received word is processed. If no match

occurs, the new ARINC word is discarded and no indicators of
receivedARINC data are presented.

The contents of the Label Look-up table may be read via the SPI
interface using instruction 0D hex as describedin Table1.

The HI-3588 has two sets of Line Receiver input pins, RINA/B
and RINA/B-40. Only one pair may be used to connect to the
ARINC 429 bus. The unused pair must be left floating. The
RINA/B pins may be connected directly to the ARINC 429 bus.
The RINA/B-40 pins require external 40K ohm resistors in series
with each ARINC input. These do not affect the ARINC receiver
thresholds. By keeping excessive voltage outside the device, this
option is helpful in applications where lightning protection is re­quired.

When using the RINA/B-40 pins, each side of the ARINC bus
must be connected through a 40K ohm series resistor in order for
the chip to detect the correct ARINC levels. The typical 10 Volt dif­ferential signal is translated and input to a window comparator
and latch. The comparator levels are set so that with the external
40K ohm resistors, they are just below the standard 6.5 volt mini­mum ARINC data threshold and just above the standard 2.5 volt
maximum ARINC null threshold.

READING THE LABELLOOK-UP TABLE

LINE RECEIVER INPUT PINS

FUNCTIONAL DESCRIPTION (cont.)

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HI-3588

MASTER RESET (MR)

Assertion of Master Reset causes immediate termination of data
reception. The receive FIFO, Status Register FIFO flags and the
FIFO status RFLAG pin is also cleared. The Control Register is
not affected by Master Reset.

TIMING DIAGRAMS

SERIAL OUTPUT TIMING DIAGRAM

CS

SCK

SO

CHZ

t

Hi Impedance

SCKH

t

t

DV

LSB

CPH

t

t

SCKL

MSB

Hi Impedance

SERIAL INPUT TIMING DIAGRAM

CS

SCK

SI

CHH

t

CEH

t

MSB

CES

t

DS

tt

DH

LSB

CPH

t

SCKR

t

SCKF

t

DATA RATE - EXAMPLE PATTERN

TXAOUT

ARINC BIT

TXBOUT

NULL

DATA

DATA

DATA

NULL

NULL

WORD GAP

BIT 1

NEXT WORD

BIT 32

BIT 31

BIT 30

RECEIVER OPERATION

RFLAG

ARINC DATA

CS

SI

BIT 31

BIT 32

RFLG

t

ARINC

WORD 1

SPIF

t

SO

SPI INSTRUCTION 08h, (or 09h)

(ARINC

WORD 2)

(ARINC

WORD 3)

RXR

t

FUNCTIONAL DESCRIPTION (cont.)

CYC

t

CYC

t

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DC ELECTRICAL CHARACTERISTICS

V = 3.3V or 5.0V , GND = 0V, TA = Operating Temperature Range (unless otherwise specified).DD

HI-3588

ABSOLUTE MAXIMUM RATINGS

Supply Voltages V ......................................... -0.3V to +7.0V

Voltage at pins RIN1A, RIN1B, RIN2A, RIN2B ..... -29V to +29V

Voltage at any other pin ............................... -0.3V to V +0.3V

Solder temperature (Leads) .................... 280 for 10 seconds

(Package) .......................................... 220

DD

DD

°C

°C

Power Dissipation at 25°C

Plastic Quad Flat Pack ..................1.5 W, derate 10mW/ C

DC Current Drain per pin .............................................. ±10mA

Operating Temperature Range (Industrial): .... -40°C to +85°C

(Hi-Temp): .....-55°C to +125°C

°

Storage Temperature Range ........................ -65°C to +150°C

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

µ

LOGIC OUTPUTS

Operating Voltage Range

Operating Supply Current

Output Voltage: Logic "1" Output Voltage V I = -100 A V

Logic "0" Output Voltage V I = 1.0mA V

Output Current: Output Sink I V = 0.4V 1.6 mA

(All Outputs & Bi-directional Pins) Output Source I V = V - 0.4V -1.0 mA

Output Capacitance: C 15 pF

VDD 3.15 5.25 V

VDD I 2.5 7 mA

OH OH

OL OL

OL OUT

OH OUT DD

O

DD

90%VDD

10% VDD

LIMITS

PARAMETER CONDITIONS UNIT

SYMBOL

Differential Input Voltage: ONE V Common mode voltages 6.5 10.0 13.0 V
(RIN1A to RIN1B, RIN2A to RIN2B) ZERO V less than ±30V with -13.0 -10.0 -6.5 V

NULL V respect to GND -2.5 0 2.5 V

Input Resistance: Differential R - 140 - K

To GND R - 140 - K

To V R - 100 - K

Input Current: Input Sink I 200 µA

Input Source I -450 µA

Input Capacitance: Differential C 20 pF

(Guaranteed but not tested) To GND C 20 pF

To V C 20 pF

Input Voltage: Input Voltage HI V V

Input Voltage LO V V

Input Current: Input Sink I 1.5 µA

Input Source I -1.5 A

MIN TYP MAX

ARINC INPUTS - Pins RINA, RINB, RINA-40 (with external 40KOhms), RINB-40 (with external 40KOhms)

LOGIC INPUTS

IH

IL

NUL

I

G

DD H

IH

IL

I

G

DD H

IH

IL

IH

IL

W
W
W

(RINA to RINB)

µ

Pull-down Current (MR, SI, SCK, ACLK pins) I 250 600 µA

Pull-up Current ( Pin) I -600 -300 µA

80% VDD

20% VDD

PD

PU

CS

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AC ELECTRICAL CHARACTERISTICS

HI-3588

ORDERING INFORMATION

HI - 3588 xx x x

PACKAGE
DESCRIPTION

44 PIN PLASTIC CHIP-SCALE, QFN (44PCS)

PART
NUMBER

PC

44 PIN PLASTIC QUAD FLAT PACK, PQFP (44PTQS)

PQ

LEAD
FINISH

PART
NUMBER

100% Matte Tin (Pb-free, RoHS compliant)

F

Tin / Lead (Sn / Pb) Solder

Blank

TEMPERATURE
RANGE

BURN

IN

-40°C TO +85°C No

-55°C TO +125°C

No

T

PART
NUMBER

T

I

FLOW

I

The HI-3588PCI and HI-3588PCT use a 44-pin plastic
chip-scale package. This package has a metal heat sink
pad on its bottom surface that is electrically connected to
the die. For the HI-3588, the primary advantage of this
package is its small size; heat sinking provides little benefit

because HI-3588 dissipation is low. If connected, the heat
bottom sink pad should be connected to VDD.

Do not connect heat sink pad to GND.

HEAT SINK - CHIP-SCALE PACKAGE ONLY

LIMITS

PARAMETER SYMBOL UNITS

MIN TYP MAX

SPI INTERFACE TIMING

RECEIVER TIMING

SCK clock period

active after last SCK rising edge t 20 ns

setup time to first SCK rising edge t 10 ns

hold time after last SCK falling edge t 40 ns

inactive between SPI instructions t

Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed t 16 µs

Received data available to SPI interface. RFLAG to active

SPI receiver read or clear FIFO instruction to RFLAG t

t 200 ns

35 ns

SPI SI Data set-up time to SCK rising edge t 30 ns

SPI SI Data hold time after SCK rising edge t 30 ns

SCK rise time t 10 ns

SCK fall ime t 10 ns

SCK pulse width high t 90 ns

SCK pulse width low t 80 ns

SO valid after SCK falling edge t 130 ns

SO high-impedance after SCK falling edge t 100 ns

Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed t 126 µs

t0 ns

155 ns

CYC

CPH

DS

DH

SCKR

SCKF

SCKH

SCKL

DV

CHZ

RFLG

RXR

CS

CS

CS

CS

CS

CHH

CES

CEH

RFLG

SPIF

VDD = 3.3V or 5.0V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz 0.1% with 60/40 duty cycle+

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REVISION HISTORY

Revision Date Description of Change

DS3588, Rev. NEW 05/08/08 Initial Release

Rev. A 10/10/08 Revised AC Electrical Characteristics
Rev. B 05/22/09 Clarified relationship between SPI bit order and ARINC 429 bit order
Rev. C 07/02/09 Removed references to V+, V-, which are not connected on this device

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HI-3588 PACKAGE DIMENSIONS

44-PIN PLASTIC CHIP-SCALE PACKAGE (QFN)

Package Type: 44PCS

BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)

.203 ± .006

(5.15 ± .15)

.016 ± .002
(0.40 ± .05)

.010

(0.25)

.020

(0.50)

.008

(0.2)

.039

(1.00)

.276

(7.00)

BSC

.203 ± .006

(5.15 ± .15)

typ

typ

Bottom

View

Top View

BSC

.276

(7.00)

BSC

max

inches (millimeters)

Heat sink pad on bottom of package.

Heat sink must be left floating or

connected to VDD.

DO NOT connect to GND.

Package Type:

0° £ Q £ 7°

Detail A

See Detail A

SQ.

44PTQS

44-PIN PLASTIC QUAD FLAT PACK (PQFP)

.006

(.15)

.547 ± .010

(13.90 ± .25)

.394 ± .004
(10.0 ± .10)

SQ.

MAX.

.014 ± ..002

(.35 ± .05)

.035 .006±

(.88 .15)±

.005

(.13)

R MIN.

.012

(.30)

R MAX.

.055 .002±

(1.4 .05)±

.063

(1.6)

MAX.

.0315

(.80)

inches (millimeters)

BSC

BSC = “Basic Spacing between Centers”
is theoretical true position dimension and
has no tolerance. (JEDEC Standard 95)

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