HOLT ADK-620x3 User Manual

AN-62003 Rev. A Holt Integrated Circuits

ADK-620x3 User’s Guide:

Evaluation Board for

HI-62003 BC/RT/MT &

HI-62023 RT only Devices

December 2018

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REVISION HISTORY

Revision

Date

Description of Change

AN-62003, Rev. New

12-02-18

Initial Release

AN-62003, Rev. A

12-12-18

Update Kit Contents

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Introduction

The Holt H-620x3 Evaluation board demonstrates the broad feature set of Holt’s MIL-STD-1553 HI-620x3
family, consisting of:

HI-62023 Remote Terminal device

HI-62003 Remote Terminal, Bus Controller and Monitor device

The H-620x3 family is a set of MIL-STD-1553B bus communication devices containing protocol
management and physical bus interface circuitry. The 2-board assembly and C project reference design
provides a ready-to-run evaluation platform demonstrating operation of Bus Controller, Bus Monitor
and Remote Terminal. For convenience, this kit includes IAR Systems Embedded Workbench® for ARM,
and a fully integrated debug interface for the ARM Cortex M3 microcontroller. Note that in this ADK­620x3 guide, the HI-62003 is used as the reference device because it contains all available features; the
HI-62023 is an RT-only device, so the BC and MT functions in the menu are not applicable in this case.

This guide describes how to set up and run the board. Additional support material and all required
project software are found in the included Holt USB drive. A version of the demonstration software is
already programmed into the microcontroller flash; the board is operational right out of the box without
installing or running the provided software development tools.

Figure 1 HI-620x3 Evaluation Board, mounted on the ARM Cortex MCU Board.

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Evaluation Kit Contents

This User Guide.

Holt HI-620x3TM Project Software and Documentation on USB drive.

Installation for IAR Systems Embedded Workbench® for ARM (32KB KickStart.), on USB drive.

2x USB interface cables.

2-board assembly comprised of:

Upper DUT board with 620x3

TM

device and dual transformer-coupled MIL-STD-1553 bus interfaces.

Numerous DIP switches configure board operation.

Lower MCU board with ARM Cortex M3 16-/32-bit microprocessor, debug interface and regulated

3.3VDC power supply.

Hardware Block Diagram

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Default Switch Settings (620x3 board)

RT ADDRESS (SW1)

SWITCH

POSITION

DESCRIPTION

SW1, 5-1

00011
(ON = 0)

Sets the RT address, default is set to 03

SW1, 6

OFF

OFF = RT address parity bit ‘1’, must be odd parity or

device will not work

CONFIG 1 (SW2)

SWITCH

DEFAULT

DESCRIPTION

SW2, 1

OFF

RSTBITEN: OFF , internal self test enabled on reset

ON – Internal self test disabled

SW2, 2

OFF

nSSFLAG/EXT_TRIG: ON, 1553 SSFLAG bit is not set

OFF, SSFLAG bit is set

Note: If External trigger is used SW2,2 should be OFF

SW2, 3

OFF

MSCLR: ON , Hardware reset

SW2, 4

ON

TXINHA: OFF, inhibits transmission on BUSA

SW2, 5

ON

TXINHB: OFF, inhibits transmission on BUSB

SW2, 6

OFF

nRTB: ON, nRTBOOT pin = 0, 1760 mode

OFF, nRTBOOT= 1 (open)

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Default Jumper Settings

HI-620x3 Board

JUMPER

POSITION

DESCRIPTION

JP1

OFF

Link to send clock to ARM board (not normally used).

JP2

ON

Ground BUSA negative line.

JP3

ON

Grounds TEST pin (disables test mode)

JP4

ON

Ground BUSB negative line.

JP5

OFF

BENDI: ON, Little Endian Data

OFF, Big Endian Data

JP6

ON

WPOL: ON, WAIT pin is active low

OFF, WAIT pin is active high

JP7

OFF

BWIDE: ON, Bus width is set to 8 bits

OFF, , Bus width is set to 16 bits

JP8

OFF

BTYPE: ON, Motorola type data bus

OFF, Intel type data bus

JP9

ON

BUSB LOAD: ON, 70Ω Load connected

OFF, 70Ω Load disconnected

JP10

ON

BUSA LOAD: ON, 70Ω Load connected

OFF, 70Ω Load disconnected

JP11, JP13

ON

Transformer 1:2.5 ratio selected

JP12, JP14

OFF

Transformer unused option

J7

OFF

Connect to disable on board oscillator (use when an
external clock is connected to J4)

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Test Points

TEST POINT

DESCRIPTION

TP1

nSSFLAG output or input for external trigger

TP2

Positive connection for 1553 Bus A

TP3

Negative connection for 1553 Bus A

TP4

nINCMD, a ‘0’ indicates 620x3 activity (default)

nMCRST, mode code 8 reset output (when enabled)

TP5

Positive connection for 1553 Bus B

TP6

HI-620x3 input clock

TP7

Negative connection for 1553 Bus B

TP8

Monitor HI-620x3 input clock

TP9

Input for TAG clock

TP10

3.3V supply for HI-620x3 (supplied from ARM board)

TP11/12

Ground connection

ARM Board

Jumpers

JUMPER

POSITION

DESCRIPTION

JP1

OFF

Link for Mode Code 8 to reset board.

JP2

ON

Link for using NonZero Wait type interface Used.

JP3

OFF

Link for using Zero Wait type interface.

JP4

OFF

Not Used.

J1

OFF

Link for external ARM clock.

J6

OFF

Link to enable supply from USB 5V, make sure this is
disconnected if using bench supply

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LEDs

LED #

DESCRIPTION

LED1

Software defined LED.

LED2

Software defined LED.

LED3

Software defined LED.

Hardware Design Overview

Refer to the end of this guide for separate schematic diagrams and bills of material for the upper
DUT board and lower MCU board.

The detachable DUT board can be separated from the provided MCU board for connection to a
user-supplied alternate microprocessor or FPGA board. The inter-board headers are located on

0.1” (2.54 mm) grid for compatibility with generic prototyping boards. All host interface signals

go through the inter-board headers. Several configuration pins including the Remote Terminal
address setting pins are controlled by two DIP switches on the upper DUT board; these signals
are not available on the inter-board headers.

The lower ARM Cortex M3 board is based on the flash-programmable Atmel AT91SAM3U-EK
microprocessor. A 16 bit data/address bus from the ARM connects to the DUT. A USB serial port
provides console I/O (optional). A RESET pushbutton resets the ARM microprocessor, which in
turn controls the DUT Master Reset signal.

The ARM Cortex M3 board includes “J-Link On Board” debug interface, licensed from
www.segger.com, providing out-of-box readiness without having to buy a costly JTAG debug

cable. The kit includes a simple USB cable for connecting the board’s debug interface to your

computer.

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620x3 Host Interface

HI-620x3 features a 16 bit parallel data bus and has 64K x 16 word SRAM address space. It is offered in
an 80 pin QFP or QFN package.

The 620x3 has data transfer speeds that depend on which of the four available clock frequencies is
selected. The board is supplied with a 50MHz XTAL oscillator module, so by default the software will set
up 50MHz operation. However an external clock can be input through SMA connector J4, if this is done
jumper J7 should be connected. The device will run on a 50, 40, 20 or 16MHz clock, but the appropriate
register setting must be sent to register 0x18.

Control Switches

SW2 has six control functions that affect operation of the HI-620x3, these are explained in the

configuration section, please check they are in the default position before continuing.

RT address set up

The RT terminal address is set using DIP switches, before applying power. RT addresses 3 and 4
are utilized by the preprogrammed Bus Controller message repertoire. The 6-position DIP switch
SW1 should already be set with the address value 03, plus odd parity.

1760 Mode (all devices)

In this mode, the RT device responds with the Status Word’s Busy bit set within 2ms of Master

Reset pin rising edge. To test this feature, the device can be powered up without the software
running (for example by using SW1 RESET switch to hold the MCU in reset). If the MSCLR switch
is toggled on the ADK (SW2/3) the device can quickly respond to a BC command with the ‘Busy’
bit set.

1553 Bus Interface

Note 1: Connecting Bus Negative to ground is strictly a bench test convenience feature. Most

performance characteristics of transmitted and received 1553 signals are specified using
differential line-to-line measurements at the bus stub, Bus Positive minus Bus Negative. This

corresponds to the red and black “BUS” test points adjacent to the transformers on the right

side of the upper circuit board. While two oscilloscope probes connected to red and black may
be used in conjunction with scope’s Ch1-Ch2 math function, a single probe connected to Bus
Positive provides the same signal display when Bus Negative is grounded. This frees up scope
probes for other purposes. The nINCMD (TP4) signal can be used to trigger the scope as shown
in magenta trace on plots from the next page, this signal goes low during 1553 activity.

Do not include a provision for grounding Bus Negative in your production design.

Note 2: For stand-alone testing (without connection to a conventional MIL-STD 1553 bus) the hardware

provides on-board 70Ω termination resistors. This is strictly a bench test convenience feature

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that supports demonstration of BC and RT without external 1553 bus connections. When using
the RT/MT mode the RT can fully transact messages, with or without the bus monitor.

On-board termination resistors are not used when connecting to a properly terminated MIL-

STD-1553 bus. Do not include a provision for termination resistors in your production design.

BusA 1553 output and nINCMD signal, in BC mode generating bus command

BusA 1553 output and nINCMD signal, in RT mode, responding to TxData command