Hitachi SH7750, SH7750R, SH7750S Hardware Manual

Hitachi SuperH RISC engine

SH7750 Series

SH7750, SH7750S, SH7750R

Hardware Manual

ADE-602-124E

Rev. 6.0 7/10/2002 Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high qua lity and reliability or where its failure or malfunction m a y dir ectly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no respon sib ility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Preface

The SH-4 (SH7750 Series: SH7750, SH7750S, SH7750R) microprocessor incorporates the 32-bit SH-4 CPU and is also equipped with peripheral functions necessary for configuring a user system.

The SH7750 Series is built in with a variety of peripheral functions such as cache memory, memory management unit (MMU), interrupt controller, timers, two serial communication interfaces (SCI, SCIF), real-time clock (RTC), user break controller (UBC), bus state controller (BSC) and smart card interface. This series can be used in a wide range of multimedia equipment. The bus controller is compatible with ROM, SRAM, DRAM, synchronous DRAM and PCMCIA, as well as 64-bit synchronous DRAM 4-bank system and 64-bit data bus.

Target Readers:

This manual is designed for use by people who design application systems using the SH7750, SH7750S, or SH7750R. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required.

Purpose:

This manual provides the information of the hardware functions and electrical characteristics of the SH7750, SH7750S, and SH7750R. The SH-4 Programming Manual contains detailed information of executable instructions. Please read the Programming Manual together with th is m a nual.

How to Use the Book:

• To understand general functions

→ Read the manual from the beginning.

The manual explains the CPU, system control functions, peripheral functions and electrical characteristics in that order.

• To understanding CPU functions

→ Refer to the separate SH-4 Programming Manual.

Explanatory Note:

List of Related Documents:

Bit sequence: upper bit at left, and lower bit at right

The latest documents are available on our Web site. Please make sure that you have the latest version. (http://www.hitachisemiconductor.com/)

• User manuals for SH7750, SH7750S, and SH7750R

Name of Document Document No.

SH7750 Series Hardware Manual This manual SH-4 Programming Manual ADE-602-156

Rev. 6.0, 07/02, page iii of I

• User manuals for development tools

Name of Document Document No.

C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-246 Simulator/Debugger User’s Manual ADE-702-186 Hitachi Embedded Workshop User’s Manual ADE-702-201

Rev. 6.0, 07/02, page iv of I

List of Items Revised or Added for This Version

Section Page Item Description

1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features

1 Description amended

and added

4 to 8 Table 1.1 SH7750 Series

Features

Description added for LSI, and description and Note added for Clock pulse generator (CPG)

SH7750 and SH7750S added to cache memory

Cache memory [SH7750R] added to table

Description added for Direct memory access controller (DMAC) and Timer unit (TMU)

SH7750R table added to Product lineup

Notes 1, 2, 3 added

1.2 Block Diagram 9 Figure 1.1 Block Diagram of

SH7750 Series Functions

1.3 Pin Arrangement 10 to 12 Figure 1.2 to 1.4 SH7750R added, and

1.4 Pin Functions 13 to 40 Table 1.2 to 1.4 Table and note

2.7 Processor Modes 55 Description deleted

3.2 Register Descriptions 61 Figure 3.2 MMU-Related

Registers

62 3. Page table entry

assistance register (PTEA)

62 1. Page table entry high

6. MMU control register (MMUCR)

I cache 8 KB and 0 cache 16 KB deleted from table

description amended

amended

Amended

SH7750R added after SH7750S

Description added

3.3.1 Physical Address Space

64 to 67 Description added

Rev. 6.0, 07/02, page v of I

Section Page Item Description

3.3.3 Virtual Address Space 68, 69 Description changed

3.3.4 On-Chip RAM Space 69 Description changed

3.3.7 Address Space

70 Note added

Identifier (ASID)

4.1.1 Features Completely revised 95 Table 4.1 Cache Features

Completely revised

(SH7750, SH7750S)

95 Table 4.2 Cache Features

Newly added

(SH7750R)

96 Table 4.3 Features of Store

Description added

Queues

4.2 Register Descriptions 97 Figure 4.1 Cache and Store

Queue Control Registers

97 (1) Cache Control Register

(CCR)

Figure changed and Note added

Description added and amended

4.3.1 Configuration Description added 101 Figure 4.3 Configuration of

Newly added

Operand Cache (SH7750R)

4.3.6 RAM Mode 106 to 107

Description amended and added

4.3.7 OC Index Mode 107 Description added

4.4.1 Configuration 109 Figure 4.5 amended to

figure 4.6, description added and amended

110 Figure 4.7 Configuration of

Newly added

Instruction Cache (SH7750R)

4.6 Memory-Mapped Cache

116 Newly added

Configuration (SH7750R)

4.7 Store Queues 122 Description amended

and added

4.7.3 Transfer to External

122, 123 Description added

Memory

4.7.4 SQ Protection 124 Description added

4.7.5 Reading the SQs

124 Newly added

(SH7750R Only)

4.7.6 SQ Usage Notes 125 Newly added

5.2 Register Descriptions 128 Description amended

5.4 Exception Types and

Priorities

Rev. 6.0, 07/02, page vi of I

130 to 132

Table 5.2 Exceptions Description and note

added

Section Page Item Description

5.6.3 Interrupts 157 (3) Peripheral Module

Description changed

Interrupts

7.3 Instruction Set 186 Table 7.7 Branch Instructions Description added

8.3 Execution Cycles and Pipeline Stalling

204 to 206

Description amended

Note changed9.1.1 Types of Power-Down

Modes

222 Table 9.1 Status of CPU and

Peripheral Modules in PowerDown Modes

Hardware standby (SH7750S, SH7750R) added to table, description amended

9.1.2 Register Configuration 223 Table 9.2 Power-Down Mode Registers

9.1.3 Pin Configuration 223 Table 9.3 Power-Down Mode Pins

Description and Note added to table

Description added to Function in table and amended

9.2.2 Peripheral Module Pin

226 Other information Description amended

High Impedance Control

9.2.3 Peripheral Module Pin

Pull-Up Control

9.2.4 Standby Control

9.2.5 Clock-Stop Register 00

(CLKSTP00) (SH7750R Only)

9.2.6 Clock-Stop Clear

9.4.1 Transition to Deep

Sleep Mode

9.5.2 Exit from Standby

Mode

9.6.1 Transition to Module

Standby Function

226 Other Information Added

227 Bit table Bit 6 amended to STHZ

and bit 1 to MSTP6,

note added 227 Bit 6, Bits 1 and 0 Description added 228, 229 Newly added

229 Added

230 Description amended,

Note added 232 Exit by Interrupt Note added

234 Text amended

Table description and

note added

9.6.2 Exit from Module Standby Function

9.7 Hardware Standby Mode (SH7750S, SH7750R Only)

234 Description amended

Note deleted 235 SH7750R added

Rev. 6.0, 07/02, page vii of I

Section Page Item Description

9.8.5 Hardware Standby Mode Timing (SH7750S,

244 to 246

Figures 9.12, 9.13, 9.15 Figures changed

Notes added

SH7750R Only)

10.2.1 Block Diagram of CPG

249 Figure 10.1 (1) Block

Diagram of CPG (SH7750,

Amended

SH7750S)

250 Figure 10.1 (2) Block

Newly added

Diagram of CPG (SH7750R)

10.2.2 CPG Pin Configuration

10.2.3 CPG Register

252 Table 10.1 CPG Pins Table and Note

amended

252 Table 10.2 CPG Register Description added

Configuration

10.3 Clock Operating Modes Description added and amended

253 Table 10.3 (1) Clock

Operating Modes (SH7750, SH7750S)

253 Table 10.3 (2) Clock

Table amended and Note amended and added

Newly added

Operating Modes (SH7750R)

254 Table 10.4 FRQCR Settings

and Internal Clock

Table and Note amended

Frequencies

10.8.2 Watchdog Timer

261 Description amended Control/Status Register (WTCSR)

10.10 Notes on Board Design

265 When Using a PLL Oscillator

Circuit

266 Figure 10.5 Points for

Description amended

Amended Attention when Using PLL Oscillator Circuit

11.1.1 Features 267 Description added for Alarm interrupts

11.1.2 Block Diagram 268 Figure 11.1 Block Diagram

of RTC

Figure amended and Note added

11.1.3 Pin Configuration 269 Table 11.1 RTC Pins Table amended

11.1.4 Register Configuration 270 Table 11.2 RTC Registers RTC control register 3 and Year alarm register added to table, and Note added

Rev. 6.0, 07/02, page viii of I

Section Page Item Description

11.2.2 Second Counter

271 Description amended

(RSECCNT)

11.2.17 RTC Control

283 Newly added Register 3 (RCR3) and YearAlarm Register (RYRAR) (SH7750R Only)

11.3.3 Alarm Function 288 Description added

11.5.2 Carry Flag and

289 Added Interrupt Flag in Standby Mode

11.5.3 Crystal Oscillator Circuit

290 Figure 11.5 Example of

Crystal Oscillator Circuit

Note amended

Connection

12.1.1 Features 291 Description amended

and added

12.1.2 Block Diagram 292 Figure 12.1 Block Diagram of TMU,

amended

12.1.4 Register Configuration 293,

294

Table 12.2 TMU Registers Description and Note

added

12.2.3 Timer Start Register

297 Added 2 (TSTR2)

12.2.4 Timer Constant Registers (TCOR)

12.2.5 Timer Counters (TCNT)

12.2.6 Timer Control Registers (TCR)

298 Description amended

and added

298,

299

Description amended and added

299 Description amended

and added

12.3.1 Counter Operation 304 Description added

12.4 Interrupts 308 Description amended

and added

309 Table 12.3 TMU Interrupt

Sources

Channels 3 and 4 added to table

Note added

13.1.1 Features 312 Burst ROM interface Description amended

and added, and Note added

13.1.2 Block Diagram 313 Figure 13.1 Block Diagram

of BSC

Figure amended and add Note added

Rev. 6.0, 07/02, page ix of I

Section Page Item Description

13.1.4 Register Configuration 318 Table 13.2 BSC Registers Bus control register 3 and 4 added to table, and Note added

13.1.5 Overview of Areas 320 Table 13.3 External Memory

Space Map

added to Area 0, 5, 6 Settable Bus Widths, and Note 7 added

319 Space Divisions Description amended

13.2.1 Bus Control Register 1 (BCR1)

13.2.2 Bus Control Register 2 (BCR2)

320 Table 13.3 External Memory

Space Map

Table amended, and Notes amended and added

321, 322 Memory Bus Width Description added 326 Bit table Bit 18 amended and

note added

327 Bit 31, Bit 30, Bit 29 Description added 328 Bit 26 330 Bit 16

Description and notes added

330 Bit 15, Bit 14 Description amended 331 Bits 13 to 11 332 Bits 10 to 8

Table amended and note added

333 Bits 7 to 5 334 Bit 0 Description amended 335 Bits 15, 14 Description added

3 (BCR3) (SH7750R Only)

13.2.4 Bus Control Register 4 (BCR4)

13.2.5 Wait Control Register 1 (WCR1)

13.2.6 Wait Control Register 2 (WCR2)

13.2.7 Wait Control Register 3 (WCR3)

337 Newly added13.2.3 Bus Control Register 338 Bits 12 to 1—Reserved Description added 338,

Newly added

339 342 Note amended

344 to 349

Bits 31 to 29, Bits 25 to 23, Bits 19 to 17, Bits 15 to 13,

Description added and amended

Bits 11 to 9, Bits 8 to 6, Bits 5 to 3, and Bits 2 to 0

351 Bit table Bits 19 and 7 changed,

and Note added

351 Description added

Rev. 6.0, 07/02, page x of I

Section Page Item Description

13.2.8 Memory Control Register (MCR)

355 Bits 15 to 13—Write

Precharge Delay (TRWL2–

Description added

TRWL0)

13.2.10 Synchronous DRAM Mode Register (SDMR)

358 For Synchronous DRAM

Interface

362 to 364

AMX6 description and Notes amended

Description amended, and Note added

370 Description amended13.3.1 Endian/Access Size

and Data Alignment

371 Data Configuration Quadword partially

amended

13.3.2 Areas 382 Area 0, Area 1 Description added and amended

13.3.3 SRAM Interface 387 Basic interface changed to SRAM interface

387 Basic Timing Description amended 388, 393

Figures 13.6, 13.11 to 13.13 Notes added

to 395 395 Read-Strobe Negate Timing

(Setting Only Possible in the

Description added and amended

SH7750R)

13.3.4 DRAM Interface 400 to 408 Figures 13.17 to 13.22 Notes added

13.3.5 Synchronous DRAM

Interface

413 Connection of Synchronous

DRAM

Description added

415 Address Multiplexing Description amended 417 to

Figure 13.28 to 13.37 Note added

428 435 Power-On Sequence Newly added

438 Notes on Changing the Burst

Newly added

Length (Variation Only Possible in the SH7750R)

440 Connecting a 128-Mbit/256-

Newly added

Mbit Synchronous DRAM with 64-bit Bus Width

13.3.6 Burst ROM Interface 441, 442 Description amended

442 to 444 Figure 13.46 to 13.48 Notes added

Rev. 6.0, 07/02, page xi of I

Section Page Item Description

13.3.7 PCMCIA Interface 444, 445 Description amended and added

446 Table 13.18 Relationship

Table amended

between Address and CE when Using PCMCIA Interface

449, 452

Figures 13.50, 13.53 to 13.55 Notes added

to 454 450 Figure 13.51 Wait Timing for

PCMCIA Memory Card

SH7750R added to Note

Interface

451 Figure 13.52 PCMCIA Space

Amended

Allocation

13.3.8 MPX Interface 455 Description added and amended

471 Figure 13.71 MPX Interface

Amended

Timing 7 457 to 472 Figures 13.57 to 13.72 Notes added 473 Description amended13.3.9 Byte Control SRAM

Interface

475 to 477 Figures 13.74 to 13.76 Notes added

13.3.10 Waits between Access Cycles

479 Figure 13.77 Waits between

Access Cycles

Replaced

13.3.11 Bus Arbitration 480, 481 Description added and amended

13.3.16 Notes on Usage 487 Refresh, Bus Arbitration Description amended

487 Synchronous DRAM Mode

Newly added

14.1 Overview 489 Description added and amended

14.1.1 Features 489 to 491 Description amended

492 Title amended14.1.2 Block Diagram

(SH7750, SH7750S)

492 Figure 14.1 Block Diagram

Amended

of DMAC

14.2 Register Descriptions

496 Title amended

(SH7750, SH7750S)

Rev. 6.0, 07/02, page xii of I

Section Page Item Description

14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)

14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)

14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0– DMATCR3)

14.2.4 DMA Channel Control Registers 0–3 (CHCR0– CHCR3)

14.2.5 DMA Operation Register (DMAOR)

14.3.2 DMA Transfer Requests

496 Description amended

497 Description amended

498 Description amended

499 Description of DDT

mode added 502, 503 Bits 19 to 16 Initial value changed 503 Bits 15, 14 and Bits 13, 12 Description amended 505 Bits 6 to 4 Description added 508 Bit 4 Description amended

513 • External Request

Description added

Acceptance Conditions

14.3.4 Types of DMA Transfer

526 Table 14.9 External Request

Transfer Sources and Destinations in DDT Mode

525 (a) Normal DMA Mode Description amendment

14.3.5 Number of Bus Cycle States and DREQ Pin

533 to 535

Figure 14.15 to 14.17 Figure description

Sampling Timing

14.5 On-Demand Data

545 Description

Transfer Mode (DDT Mode)

14.5.2 Pins in DDT Mode 547 BAVL: Data bus D63–D0 release signal

551, 552 Figures 14.26, 14.27 Title amended14.5.3 Transfer Request

Acceptance on Each Channel

553 Figure 14.28 Newly added 554 Figure 14.29 Amended 554, 555 Figure 14.30, 14.31 Errors corrected

14.5.4 Notes on Use of DDT

Module

572 c. of 3. Handshake protocol

using the data bus (valid on channel 0 only)

Usable DMAC channels changed

added

amendments Description added

Description amended

573 b. of 8. Data transfer end

request

573 12. Confirming DMA transfer

requests and number of transfers executed

Rev. 6.0, 07/02, page xiii of I

Added

Description amended

Section Page Item Description

14.6 Configuration of the

574 Newly added

DMAC (SH7750R)

14.7 Register Descriptions

579 Newly added

(SH7750R)

14.8 Operation (SH7750R) 586 Added

14.9 Usage Notes 591 4. Description amended 592 9. Newly added

15.2.8 Serial Port Register

609 Bit 7 Description amended

(SCSPTR1)

16.1.2 Block Diagram 659 Figure 16.1 Block Diagram

Amended

of SCIF

16.1.3 Pin Configuration 660 Table 16.1 SCIF Pins Note changed

16.2.6 Serial Control

667 Bit 1 Description amended

16.2.7 Serial Status Register

(SCFSR2)

669 Bit 7—Receive Error (ER) Note description

changed 672 Bit 3—Framing Error (FER) Description changed 672 Bit 2—Parity Error (PER) Description changed

16.2.9 FIFO Control Register

676 Bits 10 to 8 SH7750R added

(SCFCR2)

16.2.11 Serial Port Register (SCSPTR2)

16.3.2 Serial Operation 689 Figure 16.6 Sample SCIF

Figure 16.6 MRESET/SCK2 Pin

Deleted

Amended

Initialization Flowchart

696 Serial Data Reception Description added to 5.

17.1 Overview 703 Description amended

17.3.2 Pin Connections 711 Description deleted

18.1.3 Pin Configuration 740 Table 18.3 SCIF I/O Port

Amended

Pins

19.1.2 Block Diagram 752 Figure 19.1 Block Diagram

Amended

of INTC

19.1.4 Register Configuration 753 Table 19.2 INTC Registers Description added to table, Notes added and amended

19.2.3 On-Chip Peripheral

Module Interrupts

Rev. 6.0, 07/02, page xiv of I

757, 758 Description added and

amended

Section Page Item Description

19.2.4 Interrupt Exception Handling and Priority

19.3.1 Interrupt Priority Registers A to D (IPRA– IPRD)

19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00)

19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only)

19.3.5 Interrupt Mask Register 00 (INTMSK00) (SH7750R Only)

19.3.6 Interrupt Mask Clear Register 00 (INTMSKCLR00) (SH7750R Only)

758 Description added 759 to

761

762 Table 19.6 Interrupt Request

Table 19.5 Interrupt Exception Handling Sources and Priority Order

Sources and IPRA–IPRD

Description added to table, Notes added and amended

SH7750R added to Note 3

Registers

764 Newly added

765 Newly added

766 Newly added

767 Newly added

19.3.7 Bit Assignments of

767 19.3.4 moved to 19.3.7 INTREQ00, INTMSK00, and INTMSKCLR00 (SH7750R Only)

19.4.1 Interrupt Operation

768 Note 3 added Sequence

19.5 Interrupt Response

771 Note amended Time

20.2.4 Break Address Mask

778, 779 Bit 2, and Bits 3, 1, and 0 Description added Register (BAMRA)

20.2.10 Break Data Mask

783 Bits 31 to 0 Description added Register B (BDMRB)

20.3.7 Program Counter (PC) Value Saved

20.4 User Break Debug Support Function

791 20.3.7 Program Counter

(PC) Value Saved

794 Figure 20.2 User Break

Debug Support Function

4. Description added

Amended

Flowchart

21.1.1 Features 799 Description amended

21.1.2 Block Diagram 800 Figure 21.1 Block Diagram

of H-UDI Circuit

Figure changed and Note added

Rev. 6.0, 07/02, page xv of I

Section Page Item Description

21.1.3 Pin Configuration 801 Table 21.1 H-UDI Pins Table amended and Note 3 added

21.1.4 Register Configuration 802 Table 21.2 H-UDI Registers Description added to table and Notes 3 and 4 added

21.2.1 Instruction Register

(SDIR)

21.2.4 Interrupt Source

804 [SH7750R] description

added

806 Newly added

21.2.5 Boundary Scan

806 Newly added

808, 809 Table 21.3 Configuration of

Newly added

the Boundary Scan Register (2), (3)

21.3.3 H-UDI Interrupt 811 Description changed

21.3.4 BYPASS Deleted

21.3.4 Boundary Scan

812 Newly added (EXTEST, SAMPLE/ PRELOAD, BYPASS)

21.4 Usage Notes 812 5. Description added

22.1 Absolute Maximum Ratings

813 Table 22.1 Absolute

Maximum Rat ings

Table amended and notes amended

22.2 DC Characteristics 814, 815 Table 22.2

DC Characteristics (HD6417750RBP240)

816, 817 Table 22.3

DC Characteristics (HD6417750RF240)

818, 819 Table 22.4

DC Characteristics (HD6417750RBP200)

820, 821 Table 22.5

DC Characteristics (HD6417750RF200)

822, 823 Table 22.6

DC Characteristics (HD6417750SBP200)

826, 827 Table 22.8

DC Characteristics (HD6417750BP200M)

Newly added

Amended

Rev. 6.0, 07/02, page xvi of I

Section Page Item Description

22.2 DC Characteristics 836, 837 Table 22.13 DC Characteristics (HD6417750SVF133)

838, 839 Table 22.14

DC Characteristics (HD6417750SVBT133)

840, 841 Table 22.15

DC Characteristics (HD6417750VF128)

22.3 AC Characteristics 842 Table 22.17 Clock Timing (HD6417750RBP240)

842 Table 22.18 Clock Timing

(HD6417750RF240)

842 Table 22.19 Clock Timing

(HD6417750BP200M, HD6417750SBP200, HD6417750RBP200)

842 Table 22.20 Clock Timing

(HD6417750RF200)

Amended

Newly added

HD6417750RBP200 clock timing added

Newly added

22.3.1 Clock and Control

Signal Timing

842 Table 22.21 Clock Timing

(HD6417750SF200)

843 Table 22.22 Clock Timing

(HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I)

843 Table 22.23 Clock Timing

(HD6417750SVF133, HD6417750SVBT133)

843 Table 22.24 Clock Timing

(HD6417750VF128)

844, 845 Table 22.25 Clock and

Control Signal Timing (HD6417750RBP240)

846, 847 Table 22.26 Clock and

Control Signal Timing (HD6417750RF240)

Amended

Newly added

848, 849 Table 22.27 Clock and

Control Signal Timing (HD6417750RBP200)

Newly added

Rev. 6.0, 07/02, page xvii of I

Section Page Item Description

22.3.1 Clock and Control Signal Timing

850, 851 Table 22.28 Clock and

Control Signal Timing (HD6417750RF200)

852, 853 Table 22.29 Clock and

Control Signal Timing (HD6417750BP200M, HD6417750SBP200)

854, 855 Table 22.30 Clock and

Control Signal Timing (HD6417750SF200)

856, 857 Table 22.31 Clock and

Control Signal Timing (HD6417750F167, HD6417750F167I, HD6417750SF167, HD6417750SF167I)

858, 859 Table 22.32 Clock and

Control Signal Timing (HD6417750SVF133, HD6417750SVBT133)

Newly added

Amended

860, 861 Table 22.33 Clock and

Control Signal Timing (HD6417750VF128)

864 Figure 22.6 Standby Return

Oscillation Settling Time (Return by RESET)

865 Figure 22.8 Standby Return

Oscillation Settling Time (Return by IRL3–IRL0)

866 Figure 22.10 PLL

Synchronization Settling Time in Case of IRL Interrupt

22.3.2 Control Signal Timing 868 Table 22.34 Control Signal Timing (1)

22.3.3 Bus Timing 880 Figure 22.18 SRAM Bus Cycle: Basic Bus Cycle (No Wait, Address Setup/Hold Time Insertion, AnS = 1, AnH = 1)

Amended

Table newly added

Figure changed and Note added

Rev. 6.0, 07/02, page xviii of I

881 Figure 22.19 Burst ROM

Amended

Bus Cycle (No Wait)

871, 872 Table 22.35 Bus Timing (1) Table newly added

Section Page Item Description

22.3.4 Peripheral Module

924, 925 Table 22.36 Peripheral

Signal Timing

900 to 921, 923

930 Figure 22.62 RTC Oscillation

932 Figure 22.66(b) DBREQ/TR

Appendix A Address List 937 to

942

Appendix B Package

943, 944 Figure B.1 Package

Dimensions

Table newly added

Module Signal Timing (1) Figures 22.37 to 22.58,

Titles amended

Figure 22.60

Amended

Settling Time at Power-On

Newly added Input Timing and BAVL Output Timing

Table A.1 Address List BCR4, RCR3, RYRAR,

SDINT and Notes

added

BCR3 area 7 address

amended

DMAC, INTC, CPG,

TMU table added

Amended Dimensions (256-Pin BGA)

Appendix C Mode Pin

946 Clock Modes Table 10.3 (1), (2)

Settings

947 Area 0 Bus Width Area 0 memory type

Appendix D CKIO2ENB Pin

948 Figure D.1 CKIO2ENB Pin

Configuration Appendix E Pin Functions 950 to

952

Appendix F Synchronous

970, 971 (17) BUS 64 DRAM Address Multiplexing Tables

Figure B.2 Package Dimensions (208-Pin QFP)

Configuration Table E.1 Pin States in

Reset, Power-Down State, and Bus-Released State

(128M: 4M × 8b × 4) × 8 (SH7750R only)

(18) BUS 64 (256M: 4M × 16b × 4) × 4 (SH7750R only)

inserted

deleted and data integrated into area 0 bus width table

Amended

Sleep row deleted D40–D51 deleted Notes added Newly added

Rev. 6.0, 07/02, page xix of I

Section Page Item Description

Appendix F Synchronous DRAM Address Multiplexing Tables

Appendix H Power-On and Power-Off Procedures

Appendix I Product Code Lineup

972, 973 (19) BUS 32

(128M: 4M × 8b × 4) × 4 (SH7750S and SH7750R only)

(20) BUS 32 (256M: 4M × 16b × 4) × 2 (SH7750S and SH7750R only)

977 to 979

980 Table I.1 SH7750 Series

Product Code Lineup

SH7750R added

Newly added

SH7750R added

Rev. 6.0, 07/02, page xx of I

Contents

Section 1 Overview

1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features................................................. 1

1.2 Block Diagram.................................................................................................................. 9

1.3 Pin Arrangement............................................................................................................... 10

1.4 Pin Functions .................................................................................................................... 13

1.4.1 Pin Functions (256-Pin BGA).............................................................................. 13

1.4.2 Pin Functions (208-Pin QFP)............................................................................... 23

1.4.3 Pin Functions (264-Pin CSP)............................................................................... 31

Section 2 Programming Model

2.1 Data Formats..................................................................................................................... 41

2.2 Register Configuration...................................................................................................... 42

2.2.1 Privileged Mode and Banks................................................................................. 42

2.2.2 General Registers................................................................................................. 45

2.2.3 Floating-Point Registers....................................................................................... 47

2.2.4 Control Registers................................................................................................. 49

2.2.5 System Registers.................................................................................................. 50

........................................................................................................... 1

..................................................................................... 41

2.3 Memory-Mapped Registers............................................................................................... 52

2.4 Data Format in Registers................................................................................................... 53

2.5 Data Formats in Memory.................................................................................................. 53

2.6 Processor States ................................................................................................................ 54

2.7 Processor Modes............................................................................................................... 55

Section 3 Memory Management Unit (MMU)

3.1 Overview........................................................................................................................... 57

3.1.1 Features................................................................................................................ 57

3.1.2 Role of the MMU................................................................................................. 57

3.1.3 Register Configuration......................................................................................... 60

3.1.4 Caution................................................................................................................. 60

3.2 Register Descriptions........................................................................................................61

3.3 Address Space............................................................................................................... .... 64

3.3.1 Physical Address Space....................................................................................... 64

3.3.2 External Memory Space....................................................................................... 67

3.3.3 Virtual Address Space.......................................................................................... 68

......................................................... 57

3.3.4 On-Chip RAM Space........................................................................................... 69

3.3.5 Address Translation............................................................................................. 69

3.3.6 Single Virtual Memory Mode and Multiple Virtual Memory Mode................... 70

3.3.7 Address Space Identifier (ASID)......................................................................... 70

3.4 TLB Functions.................................................................................................................. 71

Rev. 6.0, 07/02, page xxi of I

3.4.1 Unified TLB (UTLB) Configuration................................................................... 71

3.4.2 Instruction TLB (ITLB) Configuration................................................................ 75

3.4.3 Address Translation Method................................................................................ 75

3.5 MMU Functions................................................................................................................78

3.5.1 MMU Hardware Management............................................................................. 78

3.5.2 MMU Software Management.............................................................................. 78

3.5.3 MMU Instruction (LDTLB)................................................................................. 78

3.5.4 Hardware ITLB Miss Handling........................................................................... 79

3.5.5 Avoiding Synonym Problems.............................................................................. 80

3.6 MMU Exceptions.............................................................................................................. 81

3.6.1 Instruction TLB Multiple Hit Exception.............................................................. 81

3.6.2 Instruction TLB Miss Exception.......................................................................... 82

3.6.3 Instruction TLB Protection Violation Exception................................................. 83

3.6.4 Data TLB Multiple Hit Exception ....................................................................... 84

3.6.5 Data TLB Miss Exception ................................................................................... 84

3.6.6 Data TLB Protection Violation Exception........................................................... 85

3.6.7 Initial Page Write Exception................................................................................ 86

3.7 Memory-Mapped TLB Configuration............................................................................... 87

3.7.1 ITLB Address Array............................................................................................ 88

3.7.2 ITLB Data Array 1............................................................................................... 89

3.7.3 ITLB Data Array 2............................................................................................... 90

3.7.4 UTLB Address Array........................................................................................... 90

3.7.5 UTLB Data Array 1............................................................................................. 92

3.7.6 UTLB Data Array 2............................................................................................. 93

Section 4 Caches

................................................................................................................ 95

4.1 Overview........................................................................................................................... 95

4.1.1 Features................................................................................................................ 95

4.1.2 Register Configuration......................................................................................... 96

4.2 Register Descriptions........................................................................................................97

4.3 Operand Cache (OC)......................................................................................................... 99

4.3.1 Configuration....................................................................................................... 99

4.3.2 Read Operation.................................................................................................... 103

4.3.3 Write Operation ................................................................................................... 104

4.3.4 Write-Back Buffer ............................................................................................... 105

4.3.5 Write-Through Buffer.......................................................................................... 105

4.3.6 RAM Mode.......................................................................................................... 106

4.3.7 OC Index Mode ................................................................................................... 107

4.3.8 Coherency between Cache and External Memory............................................... 107

4.3.9 Prefetch Operation............................................................................................... 108

4.4 Instruction Cache (IC)....................................................................................................... 108

4.4.1 Configuration....................................................................................................... 108

4.4.2 Read Operation.................................................................................................... 111

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4.4.3 IC Index Mode..................................................................................................... 111

4.5 Memory-Mapped Cache Configuration (SH7750, SH7750S).......................................... 112

4.5.1 IC Address Array................................................................................................. 112

4.5.2 IC Data Array....................................................................................................... 113

4.5.3 OC Address Array ............................................................................................... 114

4.5.4 OC Data Array..................................................................................................... 115

4.6 Memory-Mapped Cache Configuration (SH7750R)......................................................... 116

4.6.1 IC Address Array................................................................................................. 117

4.6.2 IC Data Array....................................................................................................... 118

4.6.3 OC Address Array ............................................................................................... 119

4.6.4 OC Data Array..................................................................................................... 120

4.6.5 Summary of the Memory-Mapping of the OC..................................................... 121

4.7 Store Queues................................................................................................................ ..... 122

4.7.1 SQ Configuration................................................................................................. 122

4.7.2 SQ Writes............................................................................................................. 122

4.7.3 Transfer to External Memory............................................................................... 122

4.7.4 SQ Protection....................................................................................................... 124

4.7.5 Reading the SQs (SH7750R Only)...................................................................... 124

4.7.6 SQ Usage Notes................................................................................................... 125

Section 5 Exceptions

........................................................................................................ 127

5.1 Overview........................................................................................................................... 127

5.1.1 Features................................................................................................................ 127

5.1.2 Register Configuration......................................................................................... 127

5.2 Register Descriptions........................................................................................................ 128

5.3 Exception Handling Functions.......................................................................................... 129

5.3.1 Exception Handling Flow.................................................................................... 129

5.3.2 Exception Handling Vector Addresses................................................................ 129

5.4 Exception Types and Priorities......................................................................................... 130

5.5 Exception Flow................................................................................................................. 132

5.5.1 Exception Flow.................................................................................................... 132

5.5.2 Exception Source Acceptance.............................................................................. 133

5.5.3 Exception Requests and BL Bit........................................................................... 135

5.5.4 Return from Exception Handling......................................................................... 135

5.6 Description of Exceptions................................................................................................. 135

5.6.1 Resets................................................................................................................... 136

5.6.2 General Exceptions.............................................................................................. 141

5.6.3 Interrupts.............................................................................................................. 155

5.6.4 Priority Order with Multiple Exceptions ............................................................. 158

5.7 Usage Notes...................................................................................................................... 159

5.8 Restrictions ....................................................................................................................... 160

Rev. 6.0, 07/02, page xxiii of I

Section 6 Floating-Point Unit

6.1 Overview........................................................................................................................... 161

6.2 Data Formats..................................................................................................................... 161

6.2.1 Floating-Point Format.......................................................................................... 161

6.2.2 Non-Numbers (NaN) ........................................................................................... 163

6.2.3 Denormalized Numbers....................................................................................... 164

6.3 Registers............................................................................................................................ 165

6.3.1 Floating-Point Registers....................................................................................... 165

6.3.2 Floating-Point Status/Control Register (FPSCR)................................................. 167

6.3.3 Floating-Point Communication Register (FPUL)................................................ 168

6.4 Rounding........................................................................................................................... 168

6.5 Floating-Point Exceptions................................................................................................. 169

6.6 Graphics Support Functions.............................................................................................. 170

6.6.1 Geometric Operation Instructions ........................................................................ 170

6.6.2 Pair Single-Precision Data Transfer..................................................................... 172

........................................................................................ 161

Section 7 Instruction Set

7.1 Execution Environment .................................................................................................... 173

7.2 Addressing Modes............................................................................................................ 175

7.3 Instruction Set................................................................................................................... 179

Section 8 Pipelining

8.1 Pipelines............................................................................................................................ 193

8.2 Parallel-Executability........................................................................................................ 200

8.3 Execution Cycles and Pipeline Stalling ............................................................................ 204

Section 9 Power-Down Modes

9.1 Overview........................................................................................................................... 221

9.1.1 Types of Power-Down Modes............................................................................. 221

9.1.2 Register Configuration......................................................................................... 223

9.1.3 Pin Configuration................................................................................................. 223

9.2 Register Descriptions........................................................................................................ 224

9.2.1 Standby Control Register (STBCR)..................................................................... 224

................................................................................................. 173

.......................................................................................................... 193

...................................................................................... 221

9.2.2 Peripheral Module Pin High Impedance Control................................................. 226

9.2.3 Peripheral Module Pin Pull-Up Control............................................................... 226

9.2.4 Standby Control Register 2 (STBCR2)................................................................ 227

9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) ..................................... 228

9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only).................... 229

9.3 Sleep Mode....................................................................................................................... 230

9.3.1 Transition to Sleep Mode..................................................................................... 230

9.3.2 Exit from Sleep Mode.......................................................................................... 230

9.4 Deep Sleep Mode.............................................................................................................. 230

9.4.1 Transition to Deep Sleep Mode ........................................................................... 230

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9.4.2 Exit from Deep Sleep Mode ................................................................................ 231

9.5 Standby Mode................................................................................................................... 231

9.5.1 Transition to Standby Mode................................................................................. 231

9.5.2 Exit from Standby Mode...................................................................................... 232

9.5.3 Clock Pause Function .......................................................................................... 232

9.6 Module Standby Function................................................................................................. 233

9.6.1 Transition to Module Standby Function .............................................................. 233

9.6.2 Exit from Module Standby Function ................................................................... 234

9.7 Hardware Standby Mode (SH7750S, SH7750R Only)..................................................... 235

9.7.1 Transition to Hardware Standby Mode................................................................ 235

9.7.2 Exit from Hardware Standby Mode..................................................................... 235

9.7.3 Usage Notes......................................................................................................... 235

9.8 STATUS Pin Change Timing........................................................................................... 236

9.8.1 In Reset................................................................................................................ 237

9.8.2 In Exit from Standby Mode................................................................................. 238

9.8.3 In Exit from Sleep Mode...................................................................................... 240

9.8.4 In Exit from Deep Sleep Mode............................................................................ 242

9.8.5 Hardware Standby Mode Timing (SH7750S, SH7750R Only)........................... 244

Section 10 Clock Oscillation Circuits

........................................................................... 247

10.1 Overview........................................................................................................................... 247

10.1.1 Features................................................................................................................ 247

10.2 Overview of CPG.............................................................................................................. 249

10.2.1 Block Diagram of CPG........................................................................................ 249

10.2.2 CPG Pin Configuration........................................................................................ 252

10.2.3 CPG Register Configuration................................................................................ 252

10.3 Clock Operating Modes.................................................................................................... 253

10.4 CPG Register Description................................................................................................. 254

10.4.1 Frequency Control Register (FRQCR)................................................................. 254

10.5 Changing the Frequency ................................................................................................... 257

10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is Off) ........... 257

10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 is On)............ 257

10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 is On)...................... 258

10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 is Off)...................... 258

10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ............................... 258

10.6 Output Clock Control........................................................................................................ 258

10.7 Overview of Watchdog Timer.......................................................................................... 259

10.7.1 Block Diagram..................................................................................................... 259

10.7.2 Register Configuration......................................................................................... 260

10.8 WDT Register Descriptions.............................................................................................. 260

10.8.1 Watchdog Timer Counter (WTCNT)................................................................... 260

10.8.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 261

10.8.3 Notes on Register Access..................................................................................... 263

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10.9 Using the WDT................................................................................................................. 263

10.9.1 Standby Clearing Procedure................................................................................ 263

10.9.2 Frequency Changing Procedure........................................................................... 264

10.9.3 Using Watchdog Timer Mode ............................................................................. 264

10.9.4 Using Interval Timer Mode ................................................................................. 265

10.10 Notes on Board Design ..................................................................................................... 265

Section 11 Realtime Clock (RTC)

.................................................................................. 267

11.1 Overview........................................................................................................................... 267

11.1.1 Features................................................................................................................ 267

11.1.2 Block Diagram..................................................................................................... 268

11.1.3 Pin Configuration................................................................................................. 269

11.1.4 Register Configuration......................................................................................... 269

11.2 Register Descriptions........................................................................................................ 271

11.2.1 64 Hz Counter (R64CNT).................................................................................... 271

11.2.2 Second Counter (RSECCNT) .............................................................................. 271

11.2.3 Minute Counter (RMINCNT).............................................................................. 272

11.2.4 Hour Counter (RHRCNT).................................................................................... 272

11.2.5 Day-of-Week Counter (RWKCNT)..................................................................... 273

11.2.6 Day Counter (RDAYCNT).................................................................................. 274

11.2.7 Month Counter (RMONCNT) ............................................................................. 274

11.2.8 Year Counter (RYRCNT).................................................................................... 275

11.2.9 Second Alarm Register (RSECAR)..................................................................... 276

11.2.10 Minute Alarm Register (RMINAR)..................................................................... 276

11.2.11 Hour Alarm Register (RHRAR) .......................................................................... 277

11.2.12 Day-of-Week Alarm Register (RWKAR)............................................................ 277

11.2.13 Day Alarm Register (RDAYAR)......................................................................... 278

11.2.14 Month Alarm Register (RMONAR).................................................................... 279

11.2.15 RTC Control Register 1 (RCR1).......................................................................... 279

11.2.16 RTC Control Register 2 (RCR2).......................................................................... 281

11.2.17 RTC Control Register 3 (RCR3) and Year-Alarm Regi ster (RYRAR)

(SH7750R Only).................................................................................................. 283

11.3 Operation .......................................................................................................................... 285

11.3.1 Time Setting Procedures...................................................................................... 285

11.3.2 Time Reading Procedures.................................................................................... 286

11.3.3 Alarm Function.................................................................................................... 288

11.4 Interrupts........................................................................................................................... 289

11.5 Usage Notes...................................................................................................................... 289

11.5.1 Register Initialization........................................................................................... 289

11.5.2 Carry Flag and Interrupt Flag in Standby Mode.................................................. 289

11.5.3 Crystal Oscillator Circuit..................................................................................... 289

Rev. 6.0, 07/02, page xxvi of I

Section 12 Timer Unit (TMU)

......................................................................................... 291

12.1 Overview........................................................................................................................... 291

12.1.1 Features................................................................................................................ 291

12.1.2 Block Diagram..................................................................................................... 292

12.1.3 Pin Configuration................................................................................................. 292

12.1.4 Register Configuration......................................................................................... 293

12.2 Register Descriptions........................................................................................................ 295

12.2.1 Timer Output Control Register (TOCR).............................................................. 295

12.2.2 Timer Start Register (TSTR)................................................................................ 296

12.2.3 Timer Start Register 2 (TSTR2) (SH7750R Only).............................................. 297

12.2.4 Timer Constant Registers (TCOR) ...................................................................... 298

12.2.5 Timer Counters (TCNT)...................................................................................... 298

12.2.6 Timer Control Registers (TCR)........................................................................... 299

12.2.7 Input Capture Register (TCPR2).......................................................................... 303

12.3 Operation .......................................................................................................................... 304

12.3.1 Counter Operation................................................................................................ 304

12.3.2 Input Capture Function........................................................................................ 307

12.4 Interrupts........................................................................................................................... 308

12.5 Usage Notes...................................................................................................................... 309

12.5.1 Register Writes .................................................................................................... 309

12.5.2 TCNT Register Reads.......................................................................................... 309

12.5.3 Resetting the RTC Frequency Divider................................................................. 309

12.5.4 External Clock Frequency.................................................................................... 309

Section 13 Bus State Controller (BSC)

......................................................................... 311

13.1 Overview........................................................................................................................... 311

13.1.1 Features................................................................................................................ 311

13.1.2 Block Diagram..................................................................................................... 313

13.1.3 Pin Configuration................................................................................................. 314

13.1.4 Register Configuration......................................................................................... 318

13.1.5 Overview of Areas............................................................................................... 319

13.1.6 PCMCIA Support ................................................................................................ 322

13.2 Register Descriptions........................................................................................................ 326

13.2.1 Bus Control Register 1 (BCR1)........................................................................... 326

13.2.2 Bus Control Register 2 (BCR2)........................................................................... 335

13.2.3 Bus Control Register 3 (BCR3) (SH7750R Only)............................................... 337

13.2.4 Bus Control Register 4 (BCR4) (SH7750R Only)............................................... 338

13.2.5 Wait Control Register 1 (WCR1)......................................................................... 340

13.2.6 Wait Control Register 2 (WCR2)......................................................................... 343

13.2.7 Wait Control Register 3 (WCR3)......................................................................... 351

13.2.8 Memory Control Register (MCR)........................................................................ 352

13.2.9 PCMCIA Control Register (PCR)........................................................................ 359

13.2.10 Synchronous DRAM Mode Register (SDMR).................................................... 362

Rev. 6.0, 07/02, page xxvii of I

13.2.11 Refresh Timer Control/Status Register (RTCSR)................................................ 364

13.2.12 Refresh Timer Counter (RTCNT)........................................................................ 367

13.2.13 Refresh Time Constant Register (RTCOR) ......................................................... 368

13.2.14 Refresh Count Register (RFCR).......................................................................... 369

13.2.15 Notes on Accessing Refresh Control Registers.................................................... 369

13.3 Operation .......................................................................................................................... 370

13.3.1 Endian/Access Size and Data Alignment............................................................. 370

13.3.2 Areas.................................................................................................................... 382

13.3.3 SRAM Interface................................................................................................... 387

13.3.4 DRAM Interface.................................................................................................. 395

13.3.5 Synchronous DRAM Interface ............................................................................ 413

13.3.6 Burst ROM Interface............................................................................................ 441

13.3.7 PCMCIA Interface............................................................................................... 444

13.3.8 MPX Interface...................................................................................................... 455

13.3.9 Byte Control SRAM Interface............................................................................. 473

13.3.10 Waits between Access Cycles.............................................................................. 478

13.3.11 Bus Arbitration .................................................................................................... 480

13.3.12 Master Mode........................................................................................................ 483

13.3.13 Slave Mode.......................................................................................................... 484

13.3.14 Partial-Sharing Master Mode............................................................................... 485

13.3.15 Cooperation between Master and Slave............................................................... 486

13.3.16 Notes on Usage.................................................................................................... 487

Section 14 Direct Memory Access Controller (DMAC)

.......................................... 489

14.1 Overview........................................................................................................................... 489

14.1.1 Features................................................................................................................ 489

14.1.2 Block Diagram (SH7750, SH7750S)................................................................... 492

14.1.3 Pin Configuration (SH7750, SH7750S)............................................................... 493

14.1.4 Register Configuration (SH7750, SH7750S) ....................................................... 494

14.2 Register Descriptions (SH7750, SH7750S)...................................................................... 496

14.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3).......................................... 496

14.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3).................................. 497

14.2.3 DMA Transfer Count Registers 0–3 (DMATCR0–DMATCR3)......................... 498

14.2.4 DMA Channel Control Registers 0–3 (CHCR0–CHCR3)................................... 499

14.2.5 DMA Operation Register (DMAOR)................................................................... 507

14.3 Operation .......................................................................................................................... 510

14.3.1 DMA Transfer Procedure .................................................................................... 510

14.3.2 DMA Transfer Requests...................................................................................... 512

14.3.3 Channel Priorities ................................................................................................ 515

14.3.4 Types of DMA Transfer....................................................................................... 518

14.3.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 527

14.3.6 Ending DMA Transfer......................................................................................... 541

14.4 Examples of Use............................................................................................................... 544

Rev. 6.0, 07/02, page xxviii of I

14.4.1 Examples of Transfer between External Memory and an External Device

with DACK.......................................................................................................... 544

14.5 On-Demand Data Transfer Mode (DDT Mode) ............................................................... 545

14.5.1 Operation ............................................................................................................. 545

14.5.2 Pins in DDT Mode............................................................................................... 547

14.5.3 Transfer Request Acceptance on Each Channel.................................................. 550

14.5.4 Notes on Use of DDT Module............................................................................. 571

14.6 Configuration of the DMAC (SH7750R).......................................................................... 574

14.6.1 Block Diagram of the DMAC.............................................................................. 574

14.6.2 Pin Configuration (SH7750R)............................................................................. 575

14.6.3 Register Configuration (SH7750R) ..................................................................... 576

14.7 Register Descriptions (SH7750R)..................................................................................... 579

14.7.1 DMA Source Address Registers 0–7 (SAR0–SAR7).......................................... 579

14.7.2 DMA Destination Address Registers 0–7 (DAR0–DAR7).................................. 579

14.7.3 DMA Transfer Count Registers 0–7 (DMATCR0–DMATCR7)......................... 580

14.7.4 DMA Channel Control Registers 0–7 (CHCR0–CHCR7)................................... 580

14.7.5 DMA Operation Register (DMAOR)................................................................... 583

14.8 Operation (SH7750R)....................................................................................................... 586

14.8.1 Channel Specification for a Normal DMA Transfer............................................ 586

14.8.2 Channel Specification for DDT-Mode DMA Transfer........................................ 586

14.8.3 Transfer Channel Notification in DDT Mode...................................................... 586

14.8.4 Clearing Request Queues by DTR Format........................................................... 587

14.8.5 Interrupt-Request Codes...................................................................................... 588

14.9 Usage Notes...................................................................................................................... 591

Section 15 Serial Communication Interface (SCI)

.................................................... 593

15.1 Overview........................................................................................................................... 593

15.1.1 Features................................................................................................................ 593

15.1.2 Block Diagram..................................................................................................... 595

15.1.3 Pin Configuration................................................................................................. 596

15.1.4 Register Configuration......................................................................................... 596

15.2 Register Descriptions........................................................................................................ 597

15.2.1 Receive Shift Register (SCRSR1)........................................................................ 597

15.2.2 Receive Data Register (SCRDR1)....................................................................... 597

15.2.3 Transmit Shift Register (SCTSR1)...................................................................... 598

15.2.4 Transmit Data Register (SCTDR1)...................................................................... 598

15.2.5 Serial Mode Register (SCSMR1)......................................................................... 599

15.2.6 Serial Control Register (SCSCR1)....................................................................... 601

15.2.7 Serial Status Register (SCSSR1).......................................................................... 605

15.2.8 Serial Port Register (SCSPTR1).......................................................................... 609

15.2.9 Bit Rate Register (SCBRR1)................................................................................ 613

15.3 Operation .......................................................................................................................... 621

15.3.1 Overview.............................................................................................................. 621

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15.3.2 Operation in Asynchronous Mode....................................................................... 623

15.3.3 Multiprocessor Communication Function ........................................................... 634

15.3.4 Operation in Synchronous Mode ......................................................................... 642

15.4 SCI Interrupt Sources and DMAC.................................................................................... 651

15.5 Usage Notes...................................................................................................................... 652

Section 16 Serial Communication Interface with FIFO (SCIF)

............................. 657

16.1 Overview........................................................................................................................... 657

16.1.1 Features................................................................................................................ 657

16.1.2 Block Diagram..................................................................................................... 659

16.1.3 Pin Configuration................................................................................................. 660

16.1.4 Register Configuration......................................................................................... 661

16.2 Register Descriptions........................................................................................................ 661

16.2.1 Receive Shift Register (SCRSR2)........................................................................ 661

16.2.2 Receive FIFO Data Register (SCFRDR2) ........................................................... 662

16.2.3 Transmit Shift Register (SCTSR2)...................................................................... 662

16.2.4 Transmit FIFO Data Register (SCFTDR2).......................................................... 663

16.2.5 Serial Mode Register (SCSMR2)......................................................................... 663

16.2.6 Serial Control Register (SCSCR2)....................................................................... 665

16.2.7 Serial Status Register (SCFSR2).......................................................................... 668

16.2.8 Bit Rate Register (SCBRR2)................................................................................ 674

16.2.9 FIFO Control Register (SCFCR2)....................................................................... 675

16.2.10 FIFO Data Count Register (SCFDR2)................................................................. 678

16.2.11 Serial Port Register (SCSPTR2).......................................................................... 679

16.2.12 Line Status Register (SCLSR2)........................................................................... 684

16.3 Operation .......................................................................................................................... 685

16.3.1 Overview.............................................................................................................. 685

16.3.2 Serial Operation................................................................................................... 686

16.4 SCIF Interrupt Sources and the DMAC............................................................................ 697

16.5 Usage Notes...................................................................................................................... 698

Section 17 Smart Card Interface

..................................................................................... 703

17.1 Overview........................................................................................................................... 703

17.1.1 Features................................................................................................................ 703

17.1.2 Block Diagram..................................................................................................... 704

17.1.3 Pin Configuration................................................................................................. 705

17.1.4 Register Configuration......................................................................................... 705

17.2 Register Descriptions........................................................................................................ 706

17.2.1 Smart Card Mode Register (SCSCMR1)............................................................. 706

17.2.2 Serial Mode Register (SCSMR1)......................................................................... 707

17.2.3 Serial Control Register (SCSCR1)....................................................................... 708

17.2.4 Serial Status Register (SCSSR1).......................................................................... 709

17.3 Operation .......................................................................................................................... 710

Rev. 6.0, 07/02, page xxx of I

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Hitachi SH7750, SH7750R, SH7750S Hardware Manual

Specifications and Main Features

Frequently Asked Questions

User Manual