Hitachi L19DP04U Schematic

SERVICE MANUAL MANUEL D'ENTRETIEN WARTUNGSHANDBUCH

CAUTION:

Before servicing this chassis, it is important that the service technician read the “Safety Precautions” and “Product Safety Notices” in this service manual.

No. 0257

L19DP04U

L19HP04E

L19HP04U L22DP04E L22DP04U L22DP04UA L22HP04E

L22HP04U

D a t a c o n t a i n e d w i t h i n t h i s S e r v i c e manual is subject to alteration for improvement.

ATTENTION:

Avant d’effectuer l’entretien du châssis, le technicien doit lire les «Précautions de sécurité» et les «Notices de sécurité du produit» présentés dans le présent manuel.

VORSICHT:

Vor Öffnen des Gehäuses hat der Service-Ingenieur die „Sicherheitshinweise“ und „Hinweise zur Produktsicherheit“ in diesem Wartungshandbuch zu lesen.

FOR ALL PARTS PLEASE MAKE

CONTACT WITH ASWO.

FOR YOUR LOCAL OUTLET GO TO

Les données fournies dans le présent manuel d’entretien peuvent faire l’objet de modifications en vue de perfectionner le produit.

D i e i n d i e s e m Wa r t u n g s h a n d b u c h enthaltenen Spezifikationen können sich zwecks Verbesserungen ändern.

www.aswo.com

SPECIFICATIONSANDPARTSARESUBJECTTOCHANGEFORIMPROVEMENT

Colour Television

August 2009

THIS PAGE INTENTIONALLY

LEFT BLANK

1 INTRODUCTION.............................................................................................................. 5

2 TUNER............................................................................................................................... 5

2.1 General description of TDTC-G101D: ........................................................................ 5

2.2 Features of TDTC-G101D: .......................................................................................... 6

2.3 Pin Configuration: ........................................................................................................ 7

3 SAW FILTER ......................................................................................................................... 7

3.1 IF Filter for Audio Applications – Epcos K9656M ..................................................... 7

3.1.1 Standarts .................................................................................................................... 7

3.1.2 Features ..................................................................................................................... 7

3.1.3 Pin Configuration ...................................................................................................... 7

3.1.4 Frequency Response.................................................................................................. 8

3.2 IF Filter for Video Applications – Epcos K3958M................................................... 9

3.2.1 Standarts .................................................................................................................... 9

3.2.2 Features ..................................................................................................................... 9

3.2.3 Pin Configuration ...................................................................................................... 9

3.2.4 Frequency Response.................................................................................................. 9

4 AUDIO AMPLIFIER STAGE WITH PT2333.................................................................... 10

4.1 General Description of PT2333: ................................................................................ 10

4.2 Features of PT2333: .................................................................................................. 10

4.3 Pin Configuration of PT2333: ................................................................................... 11

5 MICROCONTROLLER (MSTAR)..................................................................................... 11

5.1 Genaral Description.................................................................................................... 11

5.2 Features ...................................................................................................................... 12

6 INTEGRATED DVB-T RECEIVER (CHEERTEK) ........................................................... 13

6.1 General Description.................................................................................................... 13

6.2 Features ...................................................................................................................... 13

7. 4MX16 BIT SYNCHRONOUS DRAM ( DIGITAL SIDE SDRAM) ................................ 16

7.1 General Description.................................................................................................... 16

7.2 Features ...................................................................................................................... 16

7.3 Pin Configuration ....................................................................................................... 17

8 S25FL016A - 16 Megabit Cmos 3.0 Volt Flash Memory with 50-Mhz (Serial Peripheral Interface)Bus………………………………………………………………………………….18

8.1 General Description.................................................................................................... 18

8.2 Distinctive Characteristics.......................................................................................... 18

9 4M x 16 bit Synchronous DRAM (ANALOG SIDE SDRAM)............................................ 20

9.1 General Description................................................................................................... 20

9.2 Features ...................................................................................................................... 20

9.3 Pinning ....................................................................................................................... 21

10 POWER STAGE ................................................................................................................. 22

10.1 IPS 15 Option ........................................................................................................... 22

11 IC SPECIFICATIONS ........................................................................................................ 23

11.1 8K Smart Serial EEPROM – 24C64 ....................................................................... 23

11.2 TL062 ...................................................................................................................... 24

11.3 FSA3157.................................................................................................................. 25

11.4 FDS8878.................................................................................................................. 26

11.5 ST24LC21 (Optional) ............................................................................................. 26

11.6 TDA1308T .............................................................................................................. 27

11.7 STMP2161 .............................................................................................................. 28

11.8 AZ1045....................................................................................................................30

11.9 MP1583 ................................................................................................................... 31

11.10 LM1117................................................................................................................. 33

11.11 MP2109 ................................................................................................................. 34

11.12 FDC642P............................................................................................................... 35

11.13 XC5000 (Optional)................................................................................................ 36

12 BLOCK DIAGRAMS ......................................................................................................... 39

12.1 General Block Diagram.......................................................................................... 39

12.2 Integrated DVB-T Receiver Block Diagram.......................................................... 41

12.3 17MB45 Analog Front-End ................................................................................... 42

12.4 17MB45 Digital Front-End .................................................................................... 42

12.5 17MB45 Digital CI ve Smart Card Interface ......................................................... 43

12.6 17MB45 HDMI Inputs ........................................................................................... 43

12.7 17MB45 Analog Interface “ MSTAR IC “ ............................................................ 44

12.8 17MB45 Analog Input / Output ............................................................................ 45

12.9 17MB45 LVDS Output .......................................................................................... 45

12.10 17MB45 Power ...................................................................................................... 46

1 INTRODUCTION

17MB45-2 mainboard is based on MSTAR concept IC. This IC is capable of handling audio processing, video processing, scaling-display processing, 2D comb filter, OSD and text processing, 8 bit dual LVDS transmitter.

TV supports PAL, SECAM, NTSC colour standards and multiple transmission standards as B/G, D/K, I/I’, and L/L’ including German and NICAM stereo.

Sound system is able to supply 2x2.5W (10%THD) audio output power for stereo speakers. Supported peripherals are:

The analog part of the moard can support DVD module which is connected to mainboard through a cable. The USB feature is supported through digital part of the mainboard.

1 RF input VHF1, VHF3, UHF @ 75Ohm(Common) 1 Side AV (CVBS, R/L_Audio) (Common) 1 SCART socket(Common) 1 PC input(Common) 1 Headphone(Optional) 1 Common interface(Optional) 1 Digital USB(Optional) 1 HDMI (Optional)

2 TUNER

A horizontal mounted and Digital Half-Nim tuner is used in the product, which covers 3 Bands(From 48MHz to 862MHz for COFDM, from 45.25MHz to 863.25MHz for CCIR CH). The tuning is available through the digitally controlled I2C bus (PLL). Below you will find info on the Tuner in use.

2.1 General description of TDTC-G101D:

The Tuner covers 3 Bands(from 48MHz to 862MHz for COFDM, from 45.25MHz to

863.25MHz for CCIR CH). Band selection and Tuning are performed digitally via the I2C bus.

Tuner and Main IC connections for analog:

2.2 Features of TDTC-G101D:

x Digital Half-NIM tuner for COFDM x Covers 3 Bands(From 48MHz to 862MHz for COFDM, x From 45.25MHz to 863.25MHz for CCIR CH) x Including IF AGC with SAW Filter x Bandwidth Switching (7/8 MHz) possible x DC/DC Converter built in for Tuning Voltage x Internal(or External) RF AGC, Antenna Power Optional

2.3 Pin Configuration:

3 SAW FILTER

3.1 IF Filter for Audio Applications – Epcos K9656M

3.1.1 Standarts

x B/G x D/K x I x L/L’

3.1.2 Features

x TV IF audio filter with two channels x Channel 1 (L’) with one pass band for sound carriers at 40,40 MHz (L’) and 39,75

MHz (L’- NICAM)

x Channel 2 (B/G,D/K,L,I) with one pass band for sound carriers between 32,35 MHz

and 33,40 MHz

3.1.3 Pin Configuration

1 Input 2 Switching input 3 Chip carrier - ground 4 Output 5 Output

3.1.4 Frequency Response

Frequency Response of Channel 1:

Frequency Response of Channel 2:

3.2 IF Filter for Video Applications – Epcos K3958M

3.2.1 Standarts

x B/G x D/K x I x L/L’

3.2.2 Features

x TV IF filter with Nyquist slopes at 33.90 MHz and 38.90 MHz x Constant group delay

3.2.3 Pin Configuration

1 Input 2 Input - ground 3 Chip - carrier ground 4 Output 5 Output

3.2.4 Frequency Response

4 AUDIO AMPLIFIER STAGE WITH PT2333

4.1 General Description of PT2333:

The PT2333 is a Class-D power amplifier designed for audio equipments, maximum output power can reach up to 2.5W (VDD=5V5/ ȍ7+' 7KH37FRPSRVHG of exclusively designed Class-D circuitry (patented) by PTC, along with the most advanced semi-conductor technology. When compared to the traditional Class-AB amplifiers, the PT2333’s has a much higher efficiency (>80%), low heat dissipation, and produces superior audio quality. PT2333’s external circuitry is simple and easily accessible, and consists of flawless self-protection capabilities. The chip’s packaging is small, thus it occupies an insignificant amount of space on the circuit board; therefore, making it the predominant choice when it comes to audio amplifiers.

4.2 Features of PT2333:

• CMOS technology

• Operating voltage range from 2.7V up to 5.5V

• Differential analog input

• Maximum outSXWSRZHU:ȍ#7+' 

• Output low-pass LC filter is not required.

• Voltage gain determinate by the external resister

• Contains shutdown function

• POP noises free in shutdown and power ON/OFF period

• Built-in short circuit protection

• Built-in overheat protection

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• Available in MSOP 10-pin and WLCSP 9-pin miniature packages

4.3 Pin Configuration of PT2333:

WLCSP-9 PACKAGE:

5 MICROCONTROLLER (MSTAR)

5.1 Genaral Description

The MST9WB6JS is a high performance and fully integrated IC for multi-function LCD monitor/TV with resolutions up to UXGA (1600*1200)/WSXGA+ (1680*1050). It is configured with an integrated DVI/HDCP/HDMI receiver, a multi standard TV video and audio decoder, a video deinterlacer, a scaling engine, the MSTARACE-3 color engine, an onscreen display controller and a built in output panel interface. By use of external frame buffer, PIP/POP is provided for multimedia applications. Furthermore, 3D video decoding and processing are fulfilled for high-quality TV applications. To further reduce system costs, the MST9WB6JS also integrates intelligent power management control capability for green-mode requirements and spread spectrum support for EMI management.

5.2 Features

x Single Display LCD TV controller with PC

& multimedia display functions

x Input supports up to UXGA & 1080p x Panel supports up to UXGA (1600x1200) /

WSXGA+ (1680x1050)

x TV decoder with comb filter x Multi-standard TV sound demodulator and

decoder

x 10-bit triple-ADC for TV and RGB/YPbP x 10-bit video data processing

x Integrated DVI/HDCP/HDMI compliant

receiver

x High-quality dual scaling engines & dual 2-

D video de-interlacers

x 3-D video noise reduction x MStarACE-3 picture/color processing

engine

x Embedded On-Screen Display (OSD)

controller engine

x Built-in MCU supports PWM & GPIO x Built-in dual-link 8-bit LVDS transmitter x 5-volt tolerant inputs x Low EMI and power saving features x 216-pin LQFP

 Multi-Standard TV Sound Decoding/Processing

x Supports BTSC/A2/EIA-J demodulation and

decoding

x FM Stereo & SAP demodulation x Supports MP3 decode x Programmable delay for audio/video

synchronisation

x Audio processing for loudspeaker channel,

including volume, balance, mute, tone and P/G EQ

x Optional advanced surround available (Dolby

SRS

, BBE3 …etc) Note

 Digital Audio Interface

S digital audio input & output

x I x S/PDIF digital audio output x HDMI audio channel processing capability x Audio Line-In L/R x2 x Audio Line-Out L/R x3 x Built-in audio DAC L/R x3 x Built-in audio ADC L/R x1 x SIF audio input

 NTSC/PAL/SECAM Video Decoder

x Supports NTSC M, NTSC-J, NTSC-4.43,

PAL (B,D,G,H,M,N,I,Nc)

x Automatic TV standard detection x 3-D Comb filter for NTSC/PAL x 5 configurable CVBS & Y/C S-Video inputs x Supports closed caption and V-chip x CVBS video output

x Video IF for Multi-Standard Analog TV

x Digital low IF architecture x Stepped-gain PGA with 26dB tuning range

and 1dB tuning resolution

x Maximum IF analog gain of 37dB in

addition to digital gain

x Programmable TOP to accommodate

different tuner gain to optimise noise and linearity performance

 Analog RGB Compliant Input Ports

x Two analog ports support up to UXGA x Supports HDTV RGB/YPbPr/YCbCr x Supports Composite Sync and SOG (Sync-On-

Green) separator

x Automatic color calibration

 DVI/HDCP/HDMI Compliant Input Ports

x TWO DVI/HDMI input ports with built-in switch x Supports TMDS clock up to 225MHz @ 1080P

60Hz with 12-bit deep-color resolution

x Single link on-chip DVI 1.0 compliant receiver x High-bandwidth Digital Content Protection

(HDCP) 1.1 compliant receiver

x High Definition Multimedia Interface (HDMI) 1.3

compliant receiver with CEC support

x Long-cable tolerant robust receiver x Supports HDTV up to 1080P

6 INTEGRATED DVB-T RECEIVER (CHEERTEK)

6.1 General Description

CT216T is a highly integrated single chip for DVB-T compliant STB solution. Compared with Cheertek's previous generations of STB receiver devices. CT216T further interates COFDM demodulator USB 2.0 HS host controller, memory card reader, 1/2-bit SPIFlash interface, audio DAC, PWM in/out and SAR-ADC functions. In additiont special enhangements are provided such as MPEG-4 video decoding, 16-bit OSD with anti-flickering, HW JPEG decoding, flesh tone and black-white extensions, and improvement of small video quality.

CT216T includes COFDM demodulator transport stream de-multiplexer, DVB-CSA compliant de-scrambler, RISC MPUs, MPEG-1/2/4 AV decoder, digital T\/ encoder, audio DACs, USB 2.0 HS host controller, memory card reader, smart card reader, CI controller and other peripherals.

Cli216T is designed in focus on the market of single tuner input product which makes, it a cost effective solution. Supports include free to air, conditional access for SC (Smart card) and CI portable devices, PVR, LCD TV, and other DVB-T applications.

Digital Front End Diagram:

6.2 Features

COFDM Demodulator

x ETSI EN 300 744 DVB-T NorDig Unified 1.0.3, and D-book compliant x Automatic spectral inversion, detection x Integrated ADC x Direct IF (36.167 MHz or 43.75 MHz) or low IF (4.57 MHz) supported x 6LQJOH,)$*&RUGXDO5)O)$*&FRQWUROVZLWKǻȈPRGXODERQ x Impulsive noise cancellation x Carrier acquisition range: ±400 kHz (extensible to ±600 kHz in 8MHz BW)

x Adjacent channel interference (ACI) filter,for supporting 6, 7, and 8MHz channels

with one 8MHz analog filter

x Co-channel interterence (CCl) supression x RF signal strength monitor

MPU

x Three 32-bit RISC MPU run up to 166MHz with total 448DMIPS x 8KB I-Cache and 8KB D-Cache x Two general purpose timers x Watchdog timer x DSU for source level debug

Memory

x 6-bit SDRAM controller supports up to 32MB (16MB for l28-pin) x Unified memory architecture x Parallel flash (216-pin only) x 1/2-bit SPI flash

Transport De-multiplexing

x TS, PES, and ES demultiplexing x OneTS path x CI CAM interface (216-pin only) x 32 general purpose PID filters x 32 Section filters x CRC-32 accelerator x DVB-CSA de-scramblers

Video Decoding and Processing

x MPEG-2 MP@ML x MPEG-4 SP&ASP x PAL/NTSC format conversion x 3:2 pull down x Zoom in/out from 1/16X to 16X x HW JPEG decode x 4/8/16-bit OSD with anti-flickering x On chip NTSC/PAL TV encoder x CVBS, S-VHS, and component video x VBI insertion for Teletext, CC and WSS x ITU-R BT.601 and ITU-R BT.656 outputs x Flesh tone extension x Black/white extension,

Audio Decoding and Processing

x MPEG-1: layer 1/2/3 x MPEG-2: layer 1/2 x Decode MPEG-2 and MPEG-1 audio at sampling frequency of 16K, 22.05K, 24K,

32K, 44.1K, and 48KHz

x Decode CU-DA at sampling frequency of 44.1 KHz

x SPDIF out for AC-3 by-pass x Embedded 2 channels audio DAC for L/R outputs x Digital mute control and volume adjustment

OSD(On Screen Display)

x There are total 9 display planes: border; background. video. RS1 (Rectangle Strip 1),

RS2, OSD, RS3, RS4, and cursor.

x 4/8l16-bit OSD with anti-flickering and anti-flutter x Support alpha-blending per color x Adjustable brightness control in window x Bitmap OSD x Support horizontal pixel duplication to enlarge bitmap automatically x Support sub-region redraw to facilitate bitmap display.

Digitnal TV Encoder

x NTSC-M, PAL-B, D, G, H, I, Nc, M encoding x Four video DACs to provide 6 configuration output: modes x Support CVBS, S-VHS. and component video outs x VBI insertion for Teletext, CC and WSS x Color burst amplitude control x Programmable sync. level x On chip, color-bar generator

High Speed I/O

x USB 2.0 HS host controller x Memory card reader with SD, MMC, and MS interfaces x Compliant with SD spec. 1.1 and MMC spec. 4.0 with 1-bit & 4-bit modes. x Compliant with Memory Stick Pro format spec. 1.02 and Memory stick format spec

1.43 with 1-bit and 4-bit modes.

Peripherals

x Up to 3 full duplex UART with 16-byte FIFO x 2-wire serial (2WS) in master mode .. . x Up to 2 IS0-7816 compliant SC (1 in 128-pin, can also be used as UART) x 5 digits 7-Segrnent LED control x 5x3 two-dimension key scan x 2 SAR-ADC input x 4 PWM input/output x 1 HW IR command decode x GPIO

Electrical and Physical Characteristics

x Capable of using single 27MHz clock input crystal x 1.8V and 3.3V dual power supply x Power standby mode x PQFP-128 (CT216T-Z) or LQFP-216 (CT216T-R) package

7. 4MX16 BIT SYNCHRONOUS DRAM ( DIGITAL SIDE SDRAM)

7.1 General Description

The EM638165 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits. It is internally configured as 4 Banks of 1M word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The EM638165 provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications.

7.2 Features

x Fast access time from clock: 4.5/5/5.4 ns x Fast clock rate: 200/166/143 MHz x Fully synchronous operation x Internal pipelined architecture x 1M word x 16-bit x 4-bank x Programmable Mode registers x CAS Latency: 2, or 3 x Burst Length: 1, 2, 4, 8, or full page x Burst Type: interleaved or linear burst x Burst stop function x Auto Refresh and Self Refresh x 4096 refresh cycles/64ms x CKE power down mode x Single +3.3V ± 0.3V power supply x Interface: LVTTL x 54-pin 400 mil plastic TSOP II package x Pb free and Halogen free x 60-ball 6.4mm x 10.1mm VFBGA package x Pb free

7.3 Pin Configuration

8 S25FL016A - 16 Megabit Cmos 3.0 Volt Flash Memory with 50-Mhz (Serial Peripheral Interface)Bus

8.1 General Description

The S25FL016A is a 3.0 Volt (2.7V to 3.6V), single-power supply Flash memory device.The device consist of thirty-two sectors, each with 512 Kb memory.

The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standart 3.0 volt Vcc supply.

The memory can be programmed 1 to 256 bytes at a time, using the Page Praogram command. The device supports Sector Erase and Bulk Erase commands.

Each device requires only a 3.0 volt power supply (2.7V to 3.6V) for both read and write functions. Internally generated and regulated voltages are provided for the program oprerations. This device does not require a Vpp supply.

8.2 Distinctive Characteristics

Architectural Advantages

x Single Power supply operation

- Full voltage range: 2,7 to 3,6V read and program operations

x Memory Architecture

- Thirty-two sectors with 512 Kb each

x Program

- Page program (up to 256 bytes) in 1,4 ms (typical)

- Program operations are on a page by page basis

x Erase

- 0,5s typical sector erase time

- 10s typical bulk erase time

x Cycling Endurance

- 100,000 cycles per sector typical

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