H8/3867 Series
H8/3867 HD6473867, HD6433867
H8/3866 HD6433866
H8/3865 HD6433865
H8/3864 HD6433864
H8/3863 HD6433863
H8/3862 HD6433862
H8/3827 Series
H8/3827 HD6473827, HD6433827
H8/3826 HD6433826
H8/3825 HD6433825
H8/3824 HD6433824
H8/3823 HD6433823
H8/3822 HD6433822
ADE-602-142B
Rev. 3
2/1/99
Hitachi Ltd.
Hardware Manual
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patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
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contained in this document.
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have received the latest product standards or specifications before final design, purchase or use.
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However, contact Hitachi’s sales office before using the product in an application that demands
especially high quality and reliability or where its failure or malfunction may directly threaten
human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power,
combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider
normally foreseeable failure rates or failure modes in semiconductor devices and employ
systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does
not cause bodily injury, fire or other consequential damage due to operation of the Hitachi
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without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
Cautions
List of Items Revised or Added for This Version
Page Item Description
1 Table 1-1 Features / CPU Change in (2) High-speed calculation
specification
2 Table 1-1 Features / Clock pulse Change in specification
generators
3 Table 1-1 Features / LCD drive power Addition
supply
5 Figure 1-1 Block Diagram Modification
8 Table 1-2 Pin Functions / Power Modification of stabilization capacitance
source pin
13 2.1.1 Features Change in High-speed operation
88 Figure 4-2 Typical Connection to Addition of recommended value
Crystal Oscillator
89 Figure 4-4 Typical Connection to Addition of recommended value
Ceramic Oscillator
91 Figure 4-7 Typical Connection to Addition of description
32.768-kHz/38.4 kHz Crystal Oscillator
(Subclock)
92 Figure 4-9 Pin Connection when not Modification
Using Subclock
95 Table 5-1 Operating Modes Modification of subsleep mode/watch mode
descriptions
97 Table 5-2 Internal State in Each Modification of Note 4
Operating Mode
99 5.1.1 System Control Registers Addition of Notes to Bits 6 to 4
1. System control register 1 (SYSCR1)
100 2. System control register 2 (SYSCR2) Modification of Bit 4 contents
102 5.2 Sleep Mode Addition of description
104 5.3.3 Oscillator Settling Timer after Addition of description
Stanby Mode is Cleared
107 5.5.2 Clearing Subsleep Mode Addition of description
• Clearing by interrupt
109 5.7.1 Transition to Active (Medium- Addition of description
Speed) Mode
147 Table 8-10 Port 3 Pin States Modification
226 Table 9-13 Timer G Operation Modes Addition of description in Notes
248 9.7.5 Application Notes Addition and modification of descriptions
251 Figure 10-1 SCI3 Block Diagram Modification
Page Item Description
256 10.2.5 Serial Mode Register (SMR) Addition of description in Notes
/ Bits 1 and 0
265 Table 10-4 Relation between n Addition of description in Notes
and Clock
266 Table 10-5 Maximum Bit Rate for Each Modification of Notes
Frequency (Asynchronous Mode)
267 Table 10-7 Relation between n Addition of description in Notes
and Clock
268 10.2.9 Clock Stop Register 1 Addition of description in Notes for Bits 6
(CKSTPR1) and 5
303 10.5 Application Notes Addition of 9 and 10.
357 14.2 When Using the Internal Power Modification of description
Supply Step-Down Circuit
360 15.2.1 Power Supply Voltage Modification of 1 to 3
to 362 and Operating Range
363 Table 15-2 DC Characteristics Addition and modification
to 368
369 Table 15-3 Control Signal Timing Addition and modification
to 370
371 Table 15-4 Serial Interface (SCI3-1, Addition of Notes
SCI3-2) Timing
372 Table 15-5 A/D Converter Modification
Characteristics
373 Table 15-7 AC Characteristics for Addition
External Segment Expansion
376 Figure 15-6 SCI-3 Synchronous Mode Modification of Notes
Input/Output Timing
377 Figure 15-7 Segment Expansion Addition
Signal Timing
Preface
The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible
with the H8/300 CPU.
The H8/3867 Series and H8/3827 Series have a system-on-a-chip architecture that includes such
peripheral functions as a as an LCD controller/driver, six timers, a 14-bit PWM, a two-channel serial communication interface, and an A/D converter. This allows H8/3867 Series devices to be used
as embedded microcomputers in systems requiring LCD display.
The H8/3867 Series incorporates an LCD drive power supply and step-up constant power supply
(5 V), enabling a fixed 5 V voltage to be obtained independently of VCC.
This manual describes the hardware of the H8/3867 Series and H8/3827 Series. For details on the
H8/3864 Series instruction set, refer to the H8/300L Series Programming Manual.
Contents
Section 1 Overview.......................................................................................................... 1
1.1 Overview......................................................................................................................... 1
1.2 Internal Block Diagram .................................................................................................. 5
1.3 Pin Arrangement and Functions ..................................................................................... 6
1.3.1 Pin Arrangement................................................................................................. 6
1.3.2 Pin Functions ...................................................................................................... 8
Section 2 CPU................................................................................................................... 13
2.1 Overview......................................................................................................................... 13
2.1.1 Features............................................................................................................... 13
2.1.2 Address Space..................................................................................................... 14
2.1.3 Register Configuration........................................................................................ 14
2.2 Register Descriptions...................................................................................................... 15
2.2.1 General Registers................................................................................................ 15
2.2.2 Control Registers ................................................................................................ 15
2.2.3 Initial Register Values ........................................................................................ 17
2.3 Data Formats................................................................................................................... 17
2.3.1 Data Formats in General Registers..................................................................... 18
2.3.2 Memory Data Formats........................................................................................ 19
2.4 Addressing Modes.......................................................................................................... 20
2.4.1 Addressing Modes .............................................................................................. 20
2.4.2 Effective Address Calculation ............................................................................ 22
2.5 Instruction Set................................................................................................................. 26
2.5.1 Data Transfer Instructions .................................................................................. 28
2.5.2 Arithmetic Operations ........................................................................................ 30
2.5.3 Logic Operations ................................................................................................ 31
2.5.4 Shift Operations.................................................................................................. 31
2.5.5 Bit Manipulations ............................................................................................... 33
2.5.6 Branching Instructions........................................................................................ 37
2.5.7 System Control Instructions ............................................................................... 39
2.5.8 Block Data Transfer Instruction ......................................................................... 40
2.6 Basic Operational Timing............................................................................................... 42
2.6.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 42
2.6.2 Access to On-Chip Peripheral Modules ............................................................. 43
2.7 CPU States...................................................................................................................... 45
2.7.1 Overview............................................................................................................. 45
2.7.2 Program Execution State ................................................................................... 46
2.7.3 Program Halt State.............................................................................................. 46
2.7.4 Exception-Handling State................................................................................... 46
2.8 Memory Map.................................................................................................................. 47
2.8.1 Memory Map ...................................................................................................... 47
2.9 Application Notes........................................................................................................... 53
2.9.1 Notes on Data Access ......................................................................................... 53
2.9.2 Notes on Bit Manipulation.................................................................................. 55
2.9.3 Notes on Use of the EEPMOV Instruction......................................................... 61
Section 3 Exception Handling...................................................................................... 63
3.1 Overview......................................................................................................................... 63
3.2 Reset ............................................................................................................................ 63
3.2.1 Overview............................................................................................................. 63
3.2.2 Reset Sequence ................................................................................................... 63
3.2.3 Interrupt Immediately after Reset....................................................................... 65
3.3 Interrupts......................................................................................................................... 65
3.3.1 Overview............................................................................................................. 65
3.3.2 Interrupt Control Registers ................................................................................. 67
3.3.3 External Interrupts .............................................................................................. 76
3.3.4 Internal Interrupts ............................................................................................... 77
3.3.5 Interrupt Operations............................................................................................ 78
3.3.6 Interrupt Response Time..................................................................................... 83
3.4 Application Notes........................................................................................................... 84
3.4.1 Notes on Stack Area Use .................................................................................... 84
3.4.2 Notes on Rewriting Port Mode Registers ........................................................... 85
Section 4 Clock Pulse Generators............................................................................... 87
4.1 Overview......................................................................................................................... 87
4.1.1 Block Diagram.................................................................................................... 87
4.1.2 System Clock and Subclock ............................................................................... 87
4.2 System Clock Generator................................................................................................. 88
4.3 Subclock Generator ........................................................................................................ 91
4.4 Prescalers........................................................................................................................ 93
4.5 Note on Oscillators......................................................................................................... 94
Section 5 Power-Down Modes..................................................................................... 95
5.1 Overview......................................................................................................................... 95
5.1.1 System Control Registers ................................................................................... 98
5.2 Sleep Mode..................................................................................................................... 102
5.2.1 Transition to Sleep Mode.................................................................................... 102
5.2.2 Clearing Sleep Mode .......................................................................................... 102
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode ............................................ 102
5.3 Standby Mode................................................................................................................. 103
5.3.1 Transition to Standby Mode ............................................................................... 103
5.3.2 Clearing Standby Mode ...................................................................................... 103
5.3.3 Oscillator Settling Time after Standby Mode is Cleared.................................... 104
5.3.4 Standby Mode Transition and Pin States............................................................ 105
5.4 Watch Mode.................................................................................................................... 106
5.4.1 Transition to Watch Mode.................................................................................. 106
5.4.2 Clearing Watch Mode......................................................................................... 106
5.4.3 Oscillator Settling Time after Watch Mode is Cleared ...................................... 106
5.5 Subsleep Mode................................................................................................................ 107
5.5.1 Transition to Subsleep Mode.............................................................................. 107
5.5.2 Clearing Subsleep Mode..................................................................................... 107
5.6 Subactive Mode.............................................................................................................. 108
5.6.1 Transition to Subactive Mode............................................................................. 108
5.6.2 Clearing Subactive Mode ................................................................................... 108
5.6.3 Operating Frequency in Subactive Mode ........................................................... 108
5.7 Active (Medium-Speed) Mode....................................................................................... 109
5.7.1 Transition to Active (Medium-Speed) Mode ..................................................... 109
5.7.2 Clearing Active (Medium-Speed) Mode ............................................................ 109
5.7.3 Operating Frequency in Active (Medium-Speed) Mode.................................... 109
5.8 Direct Transfer................................................................................................................ 110
5.8.1 Overview of Direct Transfer............................................................................... 110
5.8.2 Direct Transition Times...................................................................................... 111
5.9 Module Standby Mode ................................................................................................... 114
5.9.1 Setting Module Standby Mode ........................................................................... 114
5.9.2 Clearing Module Standby Mode......................................................................... 114
Section 6 ROM.................................................................................................................. 117
6.1 Overview......................................................................................................................... 117
6.1.1 Block Diagram.................................................................................................... 117
6.2 H8/3867 and H8/3827 PROM Mode.............................................................................. 118
6.2.1 Setting to PROM Mode ..................................................................................... 118
6.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 118
6.3 H8/3867 and H8/3827 Programming.............................................................................. 121
6.3.1 Writing and Verifying......................................................................................... 121
6.3.2 Programming Precautions................................................................................... 126
6.4 Reliability of Programmed Data..................................................................................... 127
Section 7 RAM................................................................................................................. 129
7.1 Overview......................................................................................................................... 129
7.1.1 Block Diagram.................................................................................................... 129
Section 8 I/O Ports........................................................................................................... 131
8.1 Overview......................................................................................................................... 131
8.2 Port 1 ............................................................................................................................ 133
8.2.1 Overview............................................................................................................. 133
8.2.2 Register Configuration and Description ............................................................. 133
8.2.3 Pin Functions ...................................................................................................... 138
8.2.4 Pin States ............................................................................................................ 140
8.2.5 MOS Input Pull-Up............................................................................................. 140
8.3 Port 3 ............................................................................................................................ 141
8.3.1 Overview............................................................................................................. 141
8.3.2 Register Configuration and Description ............................................................. 141
8.3.3 Pin Functions ...................................................................................................... 145
8.3.4 Pin States ............................................................................................................ 147
8.3.5 MOS Input Pull-Up............................................................................................. 147
8.4 Port 4 ............................................................................................................................ 148
8.4.1 Overview............................................................................................................. 148
8.4.2 Register Configuration and Description ............................................................. 148
8.4.3 Pin Functions ...................................................................................................... 149
8.4.4 Pin States ............................................................................................................ 150
8.5 Port 5 ............................................................................................................................ 151
8.5.1 Overview............................................................................................................. 151
8.5.2 Register Configuration and Description ............................................................. 151
8.5.3 Pin Functions ...................................................................................................... 154
8.5.4 Pin States ............................................................................................................ 155
8.5.5 MOS Input Pull-Up............................................................................................. 155
8.6 Port 6 ............................................................................................................................ 156
8.6.1 Overview............................................................................................................. 156
8.6.2 Register Configuration and Description ............................................................. 156
8.6.3 Pin Functions ...................................................................................................... 158
8.6.4 Pin States ............................................................................................................ 158
8.6.5 MOS Input Pull-Up............................................................................................. 158
8.7 Port 7 ............................................................................................................................ 159
8.7.1 Overview............................................................................................................. 159
8.7.2 Register Configuration and Description ............................................................. 159
8.7.3 Pin Functions ...................................................................................................... 161
8.7.4 Pin States ............................................................................................................ 161
8.8 Port 8 ............................................................................................................................ 162
8.8.1 Overview............................................................................................................. 162
8.8.2 Register Configuration and Description ............................................................. 162
8.8.3 Pin Functions ...................................................................................................... 164
8.8.4 Pin States ............................................................................................................ 165
8.9 Port A ............................................................................................................................ 166
8.9.1 Overview............................................................................................................. 166
8.9.2 Register Configuration and Description ............................................................. 166
8.9.3 Pin Functions ...................................................................................................... 168
8.9.4 Pin States ............................................................................................................ 168
8.10 Port B ............................................................................................................................ 169
8.10.1 Overview............................................................................................................. 169
8.10.2 Register Configuration and Description............................................................. 169
8.11 Input/Output Data Inversion Function............................................................................ 170
8.11.1 Overview............................................................................................................. 170
8.11.2 Register Configuration and Descriptions............................................................ 170
Section 9 Timers............................................................................................................... 173
9.1 Overview......................................................................................................................... 173
9.2 Timer A........................................................................................................................... 175
9.2.1 Overview............................................................................................................. 175
9.2.2 Register Descriptions.......................................................................................... 177
9.2.3 Timer Operation.................................................................................................. 181
9.2.4 Timer A Operation States ................................................................................... 182
9.3 Timer C........................................................................................................................... 183
9.3.1 Overview............................................................................................................. 183
9.3.2 Register Descriptions.......................................................................................... 185
9.3.3 Timer Operation.................................................................................................. 189
9.3.4 Timer C Operation States ................................................................................... 191
9.4 Timer F ........................................................................................................................... 192
9.4.1 Overview............................................................................................................. 192
9.4.2 Register Descriptions.......................................................................................... 195
9.4.3 CPU Interface ..................................................................................................... 203
9.4.4 Operation ............................................................................................................ 206
9.4.5 Application Notes ............................................................................................... 210
9.5 Timer G........................................................................................................................... 212
9.5.1 Overview............................................................................................................. 212
9.5.2 Register Descriptions.......................................................................................... 215
9.5.3 Noise Canceler.................................................................................................... 220
9.5.4 Operation ............................................................................................................ 222
9.5.5 Application Notes ............................................................................................... 226
9.5.6 Timer G Application Example............................................................................ 230
9.6 Watchdog Timer............................................................................................................. 232
9.6.1 Overview............................................................................................................. 232
9.6.2 Register Descriptions.......................................................................................... 233
9.6.3 Timer Operation.................................................................................................. 237
9.6.4 Watchdog Timer Operation States...................................................................... 238
9.7 Asynchronous Event Counter (AEC) ............................................................................. 239
9.7.1 Overview............................................................................................................. 239
9.7.2 Register Descriptions.......................................................................................... 241
9.7.3 Operation ............................................................................................................ 246
9.7.4 Asynchronous Event Counter Operation Modes ................................................ 247
9.7.5 Application Notes ............................................................................................... 248
Section 10 Serial Communication Interface............................................................... 249
10.1 Overview......................................................................................................................... 249
10.1.1 Features............................................................................................................... 249
10.1.2 Block diagram..................................................................................................... 251
10.1.3 Pin configuration................................................................................................ 252
10.1.4 Register configuration........................................................................................ 252
10.2 Register Descriptions...................................................................................................... 252
10.2.1 Receive shift register (RSR)............................................................................... 252
10.2.2 Receive data register (RDR)............................................................................... 253
10.2.3 Transmit shift register (TSR).............................................................................. 253
10.2.4 Transmit data register (TDR).............................................................................. 254
10.2.5 Serial mode register (SMR)................................................................................ 254
10.2.6 Serial control register 3 (SCR3)......................................................................... 257
10.2.7 Serial status register (SSR)................................................................................. 260
10.2.8 Bit rate register (BRR) ....................................................................................... 264
10.2.9 Clock stop register 1 (CKSTPR1)...................................................................... 268
10.2.10
10.3 Operation ........................................................................................................................ 271
10.3.1 Overview............................................................................................................. 271
10.3.2 Operation in Asynchronous Mode...................................................................... 275
10.3.3 Operation in Synchronous Mode........................................................................ 284
10.3.4 Multiprocessor Communication Function.......................................................... 291
10.4 Interrupts......................................................................................................................... 298
10.5 Application Notes........................................................................................................... 299
Serial Port Control Register (SPCR) .................................................................. 269
Section 11 14-Bit PWM ................................................................................................... 305
11.1 Overview......................................................................................................................... 305
11.1.1 Features............................................................................................................... 305
11.1.2 Block Diagram.................................................................................................... 305
11.1.3 Pin Configuration................................................................................................ 306
11.1.4 Register Configuration........................................................................................ 306
11.2 Register Descriptions...................................................................................................... 307
11.2.1 PWM Control Register (PWCR)........................................................................ 307
11.2.2 PWM Data Registers U and L (PWDRU, PWDRL).......................................... 308
11.2.3 Clock Stop Register 2 (CKSTPR2).................................................................... 308
11.3 Operation ........................................................................................................................ 310
11.3.1 Operation............................................................................................................ 310
11.3.2 PWM Operation Modes...................................................................................... 311
Section 12 A/D Converter................................................................................................ 313
12.1 Overview......................................................................................................................... 313
12.1.1 Features............................................................................................................... 313
12.1.2 Block Diagram.................................................................................................... 313
12.1.3 Pin Configuration................................................................................................ 314
12.1.4 Register Configuration........................................................................................ 314
12.2 Register Descriptions...................................................................................................... 315
12.2.1 A/D Result Registers (ADRRH, ADRRL)......................................................... 315
12.2.2 A/D Mode Register (AMR)................................................................................ 315
12.2.3 A/D Start Register (ADSR)................................................................................ 317
12.2.4 Clock Stop Register 1 (CKSTPR1).................................................................... 317
12.3 Operation ........................................................................................................................ 319
12.3.1 A/D Conversion Operation................................................................................. 319
12.3.2 Start of A/D Conversion by External Trigger Input........................................... 319
12.3.3 A/D Converter Operation Modes........................................................................ 320
12.4 Interrupts......................................................................................................................... 320
12.5 Typical Use..................................................................................................................... 320
12.6 Application Notes........................................................................................................... 323
Section 13 LCD Controller/Driver................................................................................ 325
13.1 Overview......................................................................................................................... 325
13.1.1 Features............................................................................................................... 325
13.1.2 Block Diagram.................................................................................................... 326
13.1.3 Pin Configuration................................................................................................ 327
13.1.4 Register Configuration........................................................................................ 327
13.2 Register Descriptions...................................................................................................... 328
13.2.1 LCD Port Control Register (LPCR)................................................................... 328
13.2.2 LCD Control Register (LCR)............................................................................. 331
13.2.3 LCD Control Register 2 (LCR2)........................................................................ 333
13.2.4 Clock Stop Register 2 (CKSTPR2).................................................................... 335
13.3 Operation ........................................................................................................................ 336
13.3.1 Settings up to LCD Display................................................................................ 336
13.3.2 Relationship between LCD RAM and Display.................................................. 339
13.3.3 Luminance Adjustment Function (V0 Pin)......................................................... 347
13.3.4 Step-Up Constant-Voltage (5 V) Power Supply................................................. 348
13.3.5 Low-Power-Consumption LCD Drive System................................................... 348
13.3.6 Operation in Power-Down Modes...................................................................... 352
13.3.7 Boosting the LCD Drive Power Supply............................................................. 353
13.3.8 Connection to HD66100..................................................................................... 354
Section 14 Power Supply Circuit................................................................................... 357
14.1 Overview......................................................................................................................... 357
14.2 When Using the Internal Power Supply Step-Down Circuit.......................................... 357
14.3 When Not Using the Internal Power Supply Step-Down Circuit................................... 358
Section 15 Electrical Characteristics............................................................................ 359
15.1 H8/3867 Series and H8/3827 Series Absolute Maximum Ratings................................. 359
15.2 H8/3867 Series and H8/3827 Series Electrical Characteristics...................................... 360
15.2.1 Power Supply Voltage and Operating Range..................................................... 360
15.2.2 DC Characteristics.............................................................................................. 363
15.2.3 AC Characteristics.............................................................................................. 369
15.2.4 A/D Converter Characteristics............................................................................ 372
15.2.5 LCD Characteristics............................................................................................ 373
15.3 Operation Timing............................................................................................................ 374
15.4 Output Load Circuit........................................................................................................ 378
15.5 Resonator Equivalent Circuit.......................................................................................... 378
Appendix A CPU Instruction Set .................................................................................. 379
A.1 Instructions ..................................................................................................................... 379
A.2 Operation Code Map....................................................................................................... 387
A.3 Number of Execution States........................................................................................... 389
Appendix B Internal I/O Registers................................................................................ 396
B.1 Addresses........................................................................................................................ 396
B.2 Functions......................................................................................................................... 400
Appendix C I/O Port Block Diagrams......................................................................... 449
C.1 Block Diagrams of Port 1............................................................................................... 449
C.2 Block Diagrams of Port 3............................................................................................... 453
C.3 Block Diagrams of Port 4............................................................................................... 460
C.4 Block Diagram of Port 5................................................................................................. 464
C.5 Block Diagram of Port 6................................................................................................. 465
C.6 Block Diagram of Port 7................................................................................................. 466
C.7 Block Diagrams of Port 8............................................................................................... 467
C.8 Block Diagram of Port A................................................................................................ 468
C.9 Block Diagram of Port B................................................................................................ 469
Appendix D Port States in the Different Processing States................................... 470
Appendix E List of Product Codes................................................................................ 471
Appendix F Package Dimensions.................................................................................. 473
Section 1 Overview
1.1 Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3867 Series and H8/3827 Series comprise single-chip
microcomputers equipped with a controller/driver. Other on-chip peripheral functions include six
timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels, and an
A/D converter. Together, these functions make the H8/3864 Series ideally suited for embedded
applications in systems requiring low power consumption and LCD display. Models in the H8/3867
and H8/3827 Series are the H8/3862 and H8/3822, with on-chip 16-kbyte ROM and 1-kbyte RAM,
the H8/3863 and H8/3823, with 24-kbyte ROM and 1-kbyte RAM, the H8/3864 and H8/3824, with
32-kbyte ROM and 2-kbyte RAM, the H8/3865 and H8/3825, with 40-kbyte ROM and 2-kbyte
RAM, the H8/3866 and H8/3826, with 48-kbyte ROM and 2-kbyte RAM, and the H8/3867 and
H8/3827, with 60-kbyte ROM and 2-kbyte RAM.
The H8/3867 and H8/3827 are also available in a ZTAT™* version with on-chip PROM which can
be programmed as required by the user.
Table 1-1 summarizes the features of the H8/3867 Series and H8/3827 Series.
Note: * ZTAT (Zero Turn Around Time) is a trademark of Hitachi, Ltd.
Table 1-1 Features
Item Description
CPU High-speed H8/300L CPU
• General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
• Operating speed
— Max. operating speed: 3 MHz
— Add/subtract: 0.67 µs (operating at 3 MHz)
— Multiply/divide: 4.67 µs (operating at 3 MHz)
— Can run on 32.768 kHz or 38.4 kHz subclock
• Instruction set compatible with H8/300 CPU
— Instruction length of 2 bytes or 4 bytes
— Basic arithmetic operations between registers
— MOV instruction for data transfer between memory and registers
• Typical instructions
— Multiply (8 bits
— Divide (16 bits ÷ 8 bits)
— Bit accumulator
— Register-indirect designation of bit position
× 8 bits)
1
Table 1-1 Features (cont)
Item Description
Interrupts 36 interrupt sources
• 13 external interrupt sources (IRQ
• 23 internal interrupt sources
Clock pulse generators Two on-chip clock pulse generators
• System clock pulse generator: 0.4 to 6 MHz
• Subclock pulse generator: 32.768 kHz, 38.4 kHz
Power-down modes Seven power-down modes
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
• Standby mode
• Watch mode
• Subsleep mode
• Subactive mode
• Active (medium-speed) mode
Memory Large on-chip memory
• H8/3862, H8/3822: 16-kbyte ROM, 1-kbyte RAM
• H8/3863, H8/3823: 24-kbyte ROM, 1-kbyte RAM
• H8/3864, H8/3824: 32-kbyte ROM, 2-kbyte RAM
• H8/3865, H8/3825: 40-kbyte ROM, 2-kbyte RAM
• H8/3866, H8/3826: 48-kbyte ROM, 2-kbyte RAM
• H8/3867, H8/3827: 60-kbyte ROM, 2-kbyte RAM
I/O ports 64 pins
• 55 I/O pins
• 9 input pins
Timers Six on-chip timers
• Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from
the system clock (ø)* and four clock signals divided from the watch clock
)*
(ø
w
• Asynchronous event counter: 16-bit timer
— Count-up timer able to count asynchronous external events
independently of the MCU's internal clocks
Note: * See section 4, Clock Pulse Generator, for the definition of ø and ø
to IRQ0, WKP7to WKP0)
4
.
w
2
Table 1-1 Features (cont)
Item Description
Timers • Timer C: 8-bit timer
— Count-up/down timer with selection of seven internal clock signals or
event input from external pin
— Auto-reloading
• Timer F: 16-bit timer
— Can be used as two independent 8-bit timers
— Count-up timer with selection of four internal clock signals or event
input from external pin
— Provision for toggle output by means of compare-match function
• Timer G: 8-bit timer
— Count-up timer with selection of four internal clock signals
— Incorporates input capture function (built-in noise canceler)
• Watchdog timer
— Reset signal generated by overflow of 8-bit counter
Serial communication Two serial communication interface channels on chip
interface
14-bit PWM Pulse-division PWM output for reduced ripple
A/D converter Successive approximations using a resistance ladder
LCD controller/driver LCD controller/driver equipped with a maximum of 32 segment pins and
LCD drive power Step-up constant-voltage power supply allows LCD display
supply (H8/3867 Series only)
• SCI3-1: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
• SCI3-2: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
• Can be used as a 14-bit D/A converter by connecting to an external
low-pass filter.
• 8-channel analog input pins
• Conversion time: 31/ø or 62/ø per channel
four common pins
• Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
• Segment pins can be switched to general-purpose port function in 8-bit
units
3
Table 1-1 Features (cont)
Item Specification
Product lineup Product Code
Mask ROM ZTAT
Version Version Package ROM/RAM Size
HD6433862H, — 80-pin QFP (FP-80A) ROM 16 kbytes
HD6433822H RAM 1 kbyte
HD6433862F, — 80-pin QFP (FP-80B)
HD6433822F
HD6433862W, — 80-pin TQFP (TFP-80C)
HD6433822W
HD6433863H, — 80-pin QFP (FP-80A) ROM 24 kbytes
HD6433823H RAM 1 kbyte
HD6433863F, — 80-pin QFP (FP-80B)
HD6433823F
HD6433863W, — 80-pin TQFP (TFP-80C)
HD6433823W
HD6433864H, — 80-pin QFP (FP-80A) ROM 32 kbytes
HD6433824H RAM 2 kbytes
HD6433864F, — 80-pin QFP (FP-80B)
HD6433824F
HD6433864W, — 80-pin TQFP (TFP-80C)
HD6433824W
HD6433865H, — 80-pin QFP (FP-80A) ROM 40 kbytes
HD6433825H RAM 2 kbytes
HD6433865F, — 80-pin QFP (FP-80B)
HD6433825F
HD6433865W, — 80-pin TQFP (TFP-80C)
HD6433825W
HD6433866H, — 80-pin QFP (FP-80A) ROM 48 kbytes
HD6433826H RAM 2 kbytes
HD6433866F, — 80-pin QFP (FP-80B)
HD6433826F
HD6433866W, — 80-pin TQFP (TFP-80C)
HD6433826W
HD6433867H, HD6473867H, 80-pin QFP (FP-80A) ROM 60 kbytes
HD6433827H HD6473827H RAM 2 kbytes
HD6433867F, HD6473867F, 80-pin QFP (FP-80B)
HD6433827F HD6473827F
HD6433867W, HD6473867W, 80-pin TQFP (TFP-80C)
HD6433827W HD6473827W
4
1.2 Internal Block Diagram
P10/TMOW
P1
1/TMOFL
P1
2/TMOFH
P1
3/TMIG
P14/IRQ4/ADTRG
P1
5/IRQ1/TMIC
P1
6/IRQ2
P17/IRQ3/TMIF
P30/PWM
P3
1/UD
P3
2/RESO
P3
3/SCK31
P34/RXD31
P35/TXD31
P36/AEVH
P3
7/AEVL
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
OSC1
OSC2
System Clock
OSC
Port 1
Port APort 8Port 7Port 6
Port 3Port 4Port 5
X1
X2
Sub Clock
OSC
VSS
VSS
VCC
CVCC
RES
TEST
H8/300L
CPU
LCD Power
Supply
ROM
(60k/48k/40k/32k
24k/16k)
RAM
(2k/1k)
Timer - A
Timer - C
Timer - F
Timer - G
Asynchronous
counter
Serial
communication
interface 3-1
Serial
communication
interface 3-2
14-bit
PWM
WDT
LCD
Controller
A/D
(10bit)
V0
V1
V2
V3
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
P87/SEG32/CL1
P86/SEG31/CL2
P85/SEG30/DO
P8
4/SEG29/M
P8
3/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Port B
AVCC
AVSS
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Figure 1-1 shows a block diagram of the H8/3867 Series and H8/3827 Series.
Figure 1-1 Block Diagram
5
1.3 Pin Arrangement and Functions
P77/SEG24
P7
6/SEG23P75/SEG22P74/SEG21P73/SEG20P72/SEG19P71/SEG18P70/SEG17P67/SEG16P66/SEG15P65/SEG14P64/SEG13P63/SEG12P62/SEG11P61/SEG10P60/SEG9P57/WKP7/SEG8P56/WKP6/SEG7P55/WKP5/SEG6P54/WKP4/SEG5
P80/SEG25
P8
1/SEG26
P8
2/SEG27
P8
3/SEG28
P8
4/SEG29/M
P8
5/SEG30/DO
P8
6/SEG31CL2
P87/SEG32CL1
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
AVCC
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
AVSS
X1X
2
VSS
OSC2OSC
1
TEST
RES
P1
0/TMOW
P1
1/TMOFL
P1
2/TMOFH
P1
3/TMIG
P1
4/IRQ4/ADTRG
P1
5/IRQ1/TMIC
P1
6/IRQ2
P17/IRQ3/TMIF
P3
0/PWM
P3
1/UD
P3
2/RESO
P53/WKP3/SEG4
P5
2/WKP2/SEG3
P5
1/WKP1/SEG2
P5
0/WKP0/SEG1
PA
0/COM1
PA
1/COM2
PA
2/COM3
PA
3/COM4
V
CC
V0
V1
V2
V3
V
SS
CVCC
P37/AEVL
P3
6/AEVH
P3
5/TXD31
P34/RXD31
P33/SCK31
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
605958
57
56 55
54 53
52 51 50
494847
46
454443
42 41
123456789
10
11
12
13 14
15
16
17 18 19 20
1.3.1 Pin Arrangement
The H8/3867 Series and H8/3827 Series pin arrangement is shown in figures 1-2 and 1-3.
Figure 1-2 Pin Arrangement (FP-80A, TFP-80C: Top View)
6
PB5/AN5
PB6/AN6
PB7/AN7
AVSS
X1X
2
VSS
OSC2OSC
1
TEST
RES
P1
0/TMOW
P1
1/TMOFL
P1
2/TMOFH
P1
3/TMIG
P1
4/IRQ4/ADTRG
P1
5/IRQ1/TMIC
P1
6/IRQ2
P17/IRQ3/TMIF
P3
0/PWM
P3
1/UD
P3
2/RESO
P3
3/SCK31
P34/RXD31
54
P81/SEG26
P8
0/SEG25P77/SEG24P76/SEG23P75/SEG22P74/SEG21P73/SEG20P72/SEG19P71/SEG18P70/SEG17P67/SEG16P66/SEG15P65/SEG14P64/SEG13P63/SEG12P62/SEG11P61/SEG10P60/SEG9P57/WKP7/SEG8P56/WKP6/SEG7P55/WKP5/SEG6P54/WKP4/SEG5P53/WKP3/SEG4P52/WKP2/SEG3
P82/SEG27
P8
3/SEG28
P8
4/SEG29/M
P8
5/SEG30/DO
P8
6/SEG31/CL2
P87/SEG32/CL1
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
AVCC
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
P51/WKP1/SEG2
P5
0/WKP0/SEG1
PA
0/COM1
PA
1/COM2
PA
2/COM3
PA
3/COM4
V
CC
V0
V1
V2
V3
V
SS
CVCC
P37/AEVL
P3
6/AEVH
P3
5/TXD31
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
64 63 62
61
60
59 58
57
56
55
53
525150
494847
46 45 44
43 42 41
1 2 3 4 5 6 7 8 9 101112131415161718192021222324
Figure 1-3 Pin Arrangement (FP-80B: Top View)
7
1.3.2 Pin Functions
Table 1-2 outlines the pin functions of the H8/3864 Series.
Table 1-2 Pin Functions
Pin No.
FP-80A
Type Symbol TFP-80C FP-80B I/O Name and Functions
Power V
source pins CV
Clock pins OSC
CC
V
SS
AV
AV
V
0
V
1
V
2
V
3
OSC
X
1
X
2
CC
CC
SS
1
2
System RES 9 11 Input Reset: When this pin is driven low,
control the chip is reset
RESO 20 22 Output Reset output: Outputs the CPU internal
32 34 Input Power supply: All VCCpins should be
26 28 connected to the system power supply.
See section 14, Power Supply Circuit.
5 7 Input Ground: All VSSpins should be
27 29 connected to the system power supply
(0 V).
73 75 Input Analog power supply: This is the
power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply.
2 4 Input Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power supply
(0V).
31 33 Output LCD power supply: These are the
30 32 Input
29 31
28 30
power supply pins for the LCD controller/
driver. They incorporate a power supply
split-resistance, and are normally used
with V
and V1shorted.
0
7 9 Input These pins connect to a
6 8 Output
crystal or ceramic oscillator, or can be
used to input an external clock.
See section 4, Clock Pulse
Generators, for a typical connection
diagram.
3 5 Input These pins connect to a 32.768-kHz
4 6 Output
or 38.4-kHz crystal oscillator.
See section 4, Clock Pulse
Generators, for a typical connection
diagram.
reset signal.
8
Table 1-2 Pin Functions (cont)
Pin No.
FP-80A
Type Symbol TFP-80C FP-80B I/O Name and Functions
System TEST 8 10 Output Test pin: This pin is reserved and
control cannot be used. It should be connected
to VSS.
Interrupt IRQ
pins IRQ
IRQ
IRQ
IRQ
0
1
2
3
4
WKP
WKP
Timer pins TMOW 10 12 Output Clock output: This is an output pin for
AEVL 25 27 Input Asynchronous event counter event
AEVH 24 26 input: This is an event input pin for input
TMIC 15 17 Input Timer C event input: This is an event
UD 19 21 Input Timer C up/down select: This pin
TMIF 17 19 Input Timer F event input: This is an event
TMOFL 11 13 Output Timer FL output: This is an output pin
TMOFH 12 14 Output Timer FH output: This is an output pin
TMIG 13 15 Input Timer G capture input: This is an input
72 74 Input IRQ interrupt request 0 to 4: These
15 17 are input pins for edge-sensitive external
16 18 interrupts, with a selection of rising or
17 19 falling edge
14 16
to 44 to 46 to Input Wakeup interrupt request 0 to 7:
7
37 39 These are input pins for rising or falling-
0
edge-sensitive external interrupts.
waveforms generated by the timer A
output circuit.
to the asynchronous event counter.
input pin for input to the timer C counter.
selects up- or down-counting for the
timer C counter. The counter operates
as an up-counter when this pin is high,
and as a down-counter when low.
input pin for input to the timer F counter.
for waveforms generated by the timer FL
output compare function.
for waveforms generated by the timer
FH output compare function.
pin for timer G input capture.
9
Table 1-2 Pin Functions (cont)
Pin No.
FP-80A
Type Symbol TFP-80C FP-80B I/O Name and Functions
14-bit PWM 18 20 Output 14-bit PWM output: This is an output
PWM pin pin for waveforms generated by the
14-bit PWM
I/O ports PB
to 1, 3 to 1, Input Port B: This is an 8-bit input port.
7
PB
0
P4
3
to P4071 to 69 73 to 71 I/O Port 4 (bits 2 to 0): This is a 3-bit I/O
P4
2
80 to 74 80 to 76
72 74 Input Port 4 (bit 3): This is a 1-bit input port.
port. Input or output can be designated
for each bit by means of port control
register 4 (PCR4).
to 33 to 36 35 to 38 I/O Port A: This is a 4-bit I/O port. Input or
PA
3
PA
0
output can be designated for each bit by
means of port control register A (PCRA).
to 17 to 10 19 to 12 I/O Port 1: This is an 8-bit I/O port. Input or
P1
7
P1
0
output can be designated for each bit by
means of port control register 1 (PCR1).
to 25 to 18 27 to 20 I/O Port 3: This is an 8-bit I/O port. Input or
P3
7
P3
0
output can be designated for each bit by
means of port control register 3 (PCR3).
to 44 to 37 46 to 39 I/O Port 5: This is an 8-bit I/O port. Input or
P5
7
P5
0
output can be designated for each bit by
means of port control register 5 (PCR5).
to 52 to 45 54 to 47 I/O Port 6: This is an 8-bit I/O port. Input or
P6
7
P6
0
output can be designated for each bit by
means of port control register 6 (PCR6).
to 60 to 53 62 to 55 I/O Port 7: This is an 8-bit I/O port. Input or
P7
7
P7
0
output can be designated for each bit by
means of port control register 7 (PCR7).
to 68 to 61 70 to 63 I/O Port 8: This is an 8-bit I/O port. Input or
P8
7
P8
0
output can be designated for each bit by
means of port control register 8 (PCR8).
10
Table 1-2 Pin Functions (cont)
Pin No.
FP-80A
Type Symbol TFP-80C FP-80B I/O Name and Functions
Serial RXD
31
communi- This is the SCI31 data input pin.
cation
interface
TXD
31
(SCI)
SCK
31
RXD
32
TXD
32
SCK
32
A/D AN7 to 1 3 to 1 Input Analog input channels 7 to 0:
converter An0 80 to 74 80 to 76 These are analog data input channels
ADTRG 14 16 Input A/D converter trigger input:
LCD COM
controller/ COM
driver
SEG
SEG
32
1
CL1 68 70 Output LCD latch clock: This is the output pin
CL2 67 69 Output LCD shift clock: This is the output pin
DO 66 68 Output LCD serial data output: This is the
M 65 67 Output LCD alternation signal: This is the
22 24 Input SCI3-1 receive data input:
23 25 Output SCI3-1 transmit data output:
This is the SCI31 data output pin.
21 23 I/O SCI3-1 clock I/O:
This is the SCI31 clock I/O pin.
70 72 Input SCI3-2 receive data input:
This is the SCI32 data input pin.
71 73 Output SCI3-2 transmit data output:
This is the SCI32 data output pin.
69 71 I/O SCI3-2 clock I/O:
This is the SCI32 clock I/O pin.
to the A/D converter
This is the external trigger input pin to
the A/D converter
to 33 to 36 35 to 38 Output LCD common output: These are the
4
1
LCD common output pins.
to 68 to 37 70 to 39 Output LCD segment output: These are the
LCD segment output pins.
for the segment external expansion
display data latch clock.
for the segment external expansion
display data shift clock.
output pin for segment external
expansion serial display data.
output pin for the segment external
expansion LCD alternation signal.
11
Section 2 CPU
2.1 Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1 Features
Features of the H8/300L CPU are listed below.
• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions
• Eight addressing modes
— Register direct
— Register indirect
— Register indirect with displacement
— Register indirect with post-increment or pre-decrement
— Absolute address
— Immediate
— Program-counter relative
— Memory indirect
• 64-kbyte address space
• High-speed operation
— All frequently used instructions are executed in two to four states
— High-speed arithmetic and logic operations
— 8- or 16-bit register-register add or subtract: 0.67 µs*
—8 × 8-bit multiply: 4.67 µs*
— 16 ÷ 8-bit divide: 4.67 µs*
Note: * These values are at ø = 3 MHz.
• Low-power operation modes
SLEEP instruction for transfer to low-power operation
13
2.1.2 Address Space
7070
15 0
PC
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
(SP)
SP: Stack pointer
PC: Program counter
CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
CCR I U H U N Z V C
General registers (Rn)
Control registers (CR)
75321064
The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data.
See 2.8, Memory Map, for details of the memory map.
2.1.3 Register Configuration
Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
Figure 2-1 CPU Registers
14
2.2 Register Descriptions
Lower address side [H'0000]
Upper address side [H'FFFF]
Unused area
Stack area
SP (R7)
2.2.1 General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and
subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7) points to
the top of the stack.
Figure 2-2 Stack Pointer
2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU
will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the
PC is ignored (always regarded as 0).
15
Condition Code Register (CCR): This 8-bit register contains internal status information, including
the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and
XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional
branching (Bcc) instructions.
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written by
software. For further details, see section 3.3, Interrupts.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits.
16
2.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000
in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers
are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be
initialized by software, by the first instruction executed after a reset.
2.3 Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed
BCD form. Each nibble of the byte is treated as a decimal digit.
17
2.3.1 Data Formats in General Registers
76543210 don’t care
Data Type Register No. Data Format
70
1-bit data RnH
76543210don’t care
70
1-bit data RnL
MSB LSB don’t care
70
Byte data RnH
Byte data RnL
Word data Rn
4-bit BCD data RnH
4-bit BCD data RnL
Notation:
RnH:
RnL:
MSB:
LSB:
Upper byte of general register
Lower byte of general register
Most significant bit
Least significant bit
MSB LSBdon’t care
70
MSB LSB
15 0
Upper digit Lower digit
don’t care
7034
don’t care
Upper digit Lower digit
70
34
Data of all the sizes above can be stored in general registers as shown in figure 2-3.
Figure 2-3 Register Data Formats
18
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