Hitachi HD6433827, HD6433864, HD6473827, HD6433865, HD6433866 Hardware Manual

H8/3867 Series

H8/3867 HD6473867, HD6433867
H8/3866 HD6433866
H8/3865 HD6433865
H8/3864 HD6433864
H8/3863 HD6433863
H8/3862 HD6433862

H8/3827 Series

H8/3827 HD6473827, HD6433827
H8/3826 HD6433826
H8/3825 HD6433825
H8/3824 HD6433824
H8/3823 HD6433823
H8/3822 HD6433822

ADE-602-142B
Rev. 3
2/1/99
Hitachi Ltd.

Hardware Manual

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life support.

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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
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normally foreseeable failure rates or failure modes in semiconductor devices and employ
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semiconductor products.

Cautions

List of Items Revised or Added for This Version

Page Item Description

1 Table 1-1 Features / CPU Change in (2) High-speed calculation

specification

2 Table 1-1 Features / Clock pulse Change in specification

generators

3 Table 1-1 Features / LCD drive power Addition

supply
5 Figure 1-1 Block Diagram Modification
8 Table 1-2 Pin Functions / Power Modification of stabilization capacitance

source pin
13 2.1.1 Features Change in High-speed operation
88 Figure 4-2 Typical Connection to Addition of recommended value

Crystal Oscillator
89 Figure 4-4 Typical Connection to Addition of recommended value

Ceramic Oscillator
91 Figure 4-7 Typical Connection to Addition of description

32.768-kHz/38.4 kHz Crystal Oscillator

(Subclock)
92 Figure 4-9 Pin Connection when not Modification

Using Subclock
95 Table 5-1 Operating Modes Modification of subsleep mode/watch mode

descriptions

97 Table 5-2 Internal State in Each Modification of Note 4

Operating Mode
99 5.1.1 System Control Registers Addition of Notes to Bits 6 to 4

1. System control register 1 (SYSCR1)
100 2. System control register 2 (SYSCR2) Modification of Bit 4 contents
102 5.2 Sleep Mode Addition of description
104 5.3.3 Oscillator Settling Timer after Addition of description

Stanby Mode is Cleared

107 5.5.2 Clearing Subsleep Mode Addition of description

• Clearing by interrupt
109 5.7.1 Transition to Active (Medium- Addition of description

Speed) Mode
147 Table 8-10 Port 3 Pin States Modification
226 Table 9-13 Timer G Operation Modes Addition of description in Notes
248 9.7.5 Application Notes Addition and modification of descriptions
251 Figure 10-1 SCI3 Block Diagram Modification

Page Item Description

256 10.2.5 Serial Mode Register (SMR) Addition of description in Notes

/ Bits 1 and 0
265 Table 10-4 Relation between n Addition of description in Notes

and Clock
266 Table 10-5 Maximum Bit Rate for Each Modification of Notes

Frequency (Asynchronous Mode)
267 Table 10-7 Relation between n Addition of description in Notes

and Clock
268 10.2.9 Clock Stop Register 1 Addition of description in Notes for Bits 6

(CKSTPR1) and 5
303 10.5 Application Notes Addition of 9 and 10.
357 14.2 When Using the Internal Power Modification of description

Supply Step-Down Circuit
360 15.2.1 Power Supply Voltage Modification of 1 to 3

to 362 and Operating Range
363 Table 15-2 DC Characteristics Addition and modification

to 368
369 Table 15-3 Control Signal Timing Addition and modification

to 370
371 Table 15-4 Serial Interface (SCI3-1, Addition of Notes

SCI3-2) Timing
372 Table 15-5 A/D Converter Modification

Characteristics
373 Table 15-7 AC Characteristics for Addition

External Segment Expansion
376 Figure 15-6 SCI-3 Synchronous Mode Modification of Notes

Input/Output Timing
377 Figure 15-7 Segment Expansion Addition

Signal Timing

Preface

The H8/300L Series of single-chip microcomputers has the high-speed H8/300L CPU at its core,
with many necessary peripheral functions on-chip. The H8/300L CPU instruction set is compatible
with the H8/300 CPU.

The H8/3867 Series and H8/3827 Series have a system-on-a-chip architecture that includes such
peripheral functions as a as an LCD controller/driver, six timers, a 14-bit PWM, a two-channel seri­al communication interface, and an A/D converter. This allows H8/3867 Series devices to be used
as embedded microcomputers in systems requiring LCD display.

The H8/3867 Series incorporates an LCD drive power supply and step-up constant power supply
(5 V), enabling a fixed 5 V voltage to be obtained independently of VCC.

This manual describes the hardware of the H8/3867 Series and H8/3827 Series. For details on the
H8/3864 Series instruction set, refer to the H8/300L Series Programming Manual.

Contents

Section 1 Overview.......................................................................................................... 1

1.1 Overview......................................................................................................................... 1

1.2 Internal Block Diagram .................................................................................................. 5

1.3 Pin Arrangement and Functions ..................................................................................... 6

1.3.1 Pin Arrangement................................................................................................. 6

1.3.2 Pin Functions ...................................................................................................... 8

Section 2 CPU................................................................................................................... 13

2.1 Overview......................................................................................................................... 13

2.1.1 Features............................................................................................................... 13

2.1.2 Address Space..................................................................................................... 14

2.1.3 Register Configuration........................................................................................ 14

2.2 Register Descriptions...................................................................................................... 15

2.2.1 General Registers................................................................................................ 15

2.2.2 Control Registers ................................................................................................ 15

2.2.3 Initial Register Values ........................................................................................ 17

2.3 Data Formats................................................................................................................... 17

2.3.1 Data Formats in General Registers..................................................................... 18

2.3.2 Memory Data Formats........................................................................................ 19

2.4 Addressing Modes.......................................................................................................... 20

2.4.1 Addressing Modes .............................................................................................. 20

2.4.2 Effective Address Calculation ............................................................................ 22

2.5 Instruction Set................................................................................................................. 26

2.5.1 Data Transfer Instructions .................................................................................. 28

2.5.2 Arithmetic Operations ........................................................................................ 30

2.5.3 Logic Operations ................................................................................................ 31

2.5.4 Shift Operations.................................................................................................. 31

2.5.5 Bit Manipulations ............................................................................................... 33

2.5.6 Branching Instructions........................................................................................ 37

2.5.7 System Control Instructions ............................................................................... 39

2.5.8 Block Data Transfer Instruction ......................................................................... 40

2.6 Basic Operational Timing............................................................................................... 42

2.6.1 Access to On-Chip Memory (RAM, ROM) ....................................................... 42

2.6.2 Access to On-Chip Peripheral Modules ............................................................. 43

2.7 CPU States...................................................................................................................... 45

2.7.1 Overview............................................................................................................. 45

2.7.2 Program Execution State ................................................................................... 46

2.7.3 Program Halt State.............................................................................................. 46

2.7.4 Exception-Handling State................................................................................... 46

2.8 Memory Map.................................................................................................................. 47

2.8.1 Memory Map ...................................................................................................... 47

2.9 Application Notes........................................................................................................... 53

2.9.1 Notes on Data Access ......................................................................................... 53

2.9.2 Notes on Bit Manipulation.................................................................................. 55

2.9.3 Notes on Use of the EEPMOV Instruction......................................................... 61

Section 3 Exception Handling...................................................................................... 63

3.1 Overview......................................................................................................................... 63

3.2 Reset ............................................................................................................................ 63

3.2.1 Overview............................................................................................................. 63

3.2.2 Reset Sequence ................................................................................................... 63

3.2.3 Interrupt Immediately after Reset....................................................................... 65

3.3 Interrupts......................................................................................................................... 65

3.3.1 Overview............................................................................................................. 65

3.3.2 Interrupt Control Registers ................................................................................. 67

3.3.3 External Interrupts .............................................................................................. 76

3.3.4 Internal Interrupts ............................................................................................... 77

3.3.5 Interrupt Operations............................................................................................ 78

3.3.6 Interrupt Response Time..................................................................................... 83

3.4 Application Notes........................................................................................................... 84

3.4.1 Notes on Stack Area Use .................................................................................... 84

3.4.2 Notes on Rewriting Port Mode Registers ........................................................... 85

Section 4 Clock Pulse Generators............................................................................... 87

4.1 Overview......................................................................................................................... 87

4.1.1 Block Diagram.................................................................................................... 87

4.1.2 System Clock and Subclock ............................................................................... 87

4.2 System Clock Generator................................................................................................. 88

4.3 Subclock Generator ........................................................................................................ 91

4.4 Prescalers........................................................................................................................ 93

4.5 Note on Oscillators......................................................................................................... 94

Section 5 Power-Down Modes..................................................................................... 95

5.1 Overview......................................................................................................................... 95

5.1.1 System Control Registers ................................................................................... 98

5.2 Sleep Mode..................................................................................................................... 102

5.2.1 Transition to Sleep Mode.................................................................................... 102

5.2.2 Clearing Sleep Mode .......................................................................................... 102

5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode ............................................ 102

5.3 Standby Mode................................................................................................................. 103

5.3.1 Transition to Standby Mode ............................................................................... 103

5.3.2 Clearing Standby Mode ...................................................................................... 103

5.3.3 Oscillator Settling Time after Standby Mode is Cleared.................................... 104

5.3.4 Standby Mode Transition and Pin States............................................................ 105

5.4 Watch Mode.................................................................................................................... 106

5.4.1 Transition to Watch Mode.................................................................................. 106

5.4.2 Clearing Watch Mode......................................................................................... 106

5.4.3 Oscillator Settling Time after Watch Mode is Cleared ...................................... 106

5.5 Subsleep Mode................................................................................................................ 107

5.5.1 Transition to Subsleep Mode.............................................................................. 107

5.5.2 Clearing Subsleep Mode..................................................................................... 107

5.6 Subactive Mode.............................................................................................................. 108

5.6.1 Transition to Subactive Mode............................................................................. 108

5.6.2 Clearing Subactive Mode ................................................................................... 108

5.6.3 Operating Frequency in Subactive Mode ........................................................... 108

5.7 Active (Medium-Speed) Mode....................................................................................... 109

5.7.1 Transition to Active (Medium-Speed) Mode ..................................................... 109

5.7.2 Clearing Active (Medium-Speed) Mode ............................................................ 109

5.7.3 Operating Frequency in Active (Medium-Speed) Mode.................................... 109

5.8 Direct Transfer................................................................................................................ 110

5.8.1 Overview of Direct Transfer............................................................................... 110

5.8.2 Direct Transition Times...................................................................................... 111

5.9 Module Standby Mode ................................................................................................... 114

5.9.1 Setting Module Standby Mode ........................................................................... 114

5.9.2 Clearing Module Standby Mode......................................................................... 114

Section 6 ROM.................................................................................................................. 117

6.1 Overview......................................................................................................................... 117

6.1.1 Block Diagram.................................................................................................... 117

6.2 H8/3867 and H8/3827 PROM Mode.............................................................................. 118

6.2.1 Setting to PROM Mode ..................................................................................... 118

6.2.2 Socket Adapter Pin Arrangement and Memory Map ......................................... 118

6.3 H8/3867 and H8/3827 Programming.............................................................................. 121

6.3.1 Writing and Verifying......................................................................................... 121

6.3.2 Programming Precautions................................................................................... 126

6.4 Reliability of Programmed Data..................................................................................... 127

Section 7 RAM................................................................................................................. 129

7.1 Overview......................................................................................................................... 129

7.1.1 Block Diagram.................................................................................................... 129

Section 8 I/O Ports........................................................................................................... 131

8.1 Overview......................................................................................................................... 131

8.2 Port 1 ............................................................................................................................ 133

8.2.1 Overview............................................................................................................. 133

8.2.2 Register Configuration and Description ............................................................. 133

8.2.3 Pin Functions ...................................................................................................... 138

8.2.4 Pin States ............................................................................................................ 140

8.2.5 MOS Input Pull-Up............................................................................................. 140

8.3 Port 3 ............................................................................................................................ 141

8.3.1 Overview............................................................................................................. 141

8.3.2 Register Configuration and Description ............................................................. 141

8.3.3 Pin Functions ...................................................................................................... 145

8.3.4 Pin States ............................................................................................................ 147

8.3.5 MOS Input Pull-Up............................................................................................. 147

8.4 Port 4 ............................................................................................................................ 148

8.4.1 Overview............................................................................................................. 148

8.4.2 Register Configuration and Description ............................................................. 148

8.4.3 Pin Functions ...................................................................................................... 149

8.4.4 Pin States ............................................................................................................ 150

8.5 Port 5 ............................................................................................................................ 151

8.5.1 Overview............................................................................................................. 151

8.5.2 Register Configuration and Description ............................................................. 151

8.5.3 Pin Functions ...................................................................................................... 154

8.5.4 Pin States ............................................................................................................ 155

8.5.5 MOS Input Pull-Up............................................................................................. 155

8.6 Port 6 ............................................................................................................................ 156

8.6.1 Overview............................................................................................................. 156

8.6.2 Register Configuration and Description ............................................................. 156

8.6.3 Pin Functions ...................................................................................................... 158

8.6.4 Pin States ............................................................................................................ 158

8.6.5 MOS Input Pull-Up............................................................................................. 158

8.7 Port 7 ............................................................................................................................ 159

8.7.1 Overview............................................................................................................. 159

8.7.2 Register Configuration and Description ............................................................. 159

8.7.3 Pin Functions ...................................................................................................... 161

8.7.4 Pin States ............................................................................................................ 161

8.8 Port 8 ............................................................................................................................ 162

8.8.1 Overview............................................................................................................. 162

8.8.2 Register Configuration and Description ............................................................. 162

8.8.3 Pin Functions ...................................................................................................... 164

8.8.4 Pin States ............................................................................................................ 165

8.9 Port A ............................................................................................................................ 166

8.9.1 Overview............................................................................................................. 166

8.9.2 Register Configuration and Description ............................................................. 166

8.9.3 Pin Functions ...................................................................................................... 168

8.9.4 Pin States ............................................................................................................ 168

8.10 Port B ............................................................................................................................ 169

8.10.1 Overview............................................................................................................. 169

8.10.2 Register Configuration and Description............................................................. 169

8.11 Input/Output Data Inversion Function............................................................................ 170

8.11.1 Overview............................................................................................................. 170

8.11.2 Register Configuration and Descriptions............................................................ 170

Section 9 Timers............................................................................................................... 173

9.1 Overview......................................................................................................................... 173

9.2 Timer A........................................................................................................................... 175

9.2.1 Overview............................................................................................................. 175

9.2.2 Register Descriptions.......................................................................................... 177

9.2.3 Timer Operation.................................................................................................. 181

9.2.4 Timer A Operation States ................................................................................... 182

9.3 Timer C........................................................................................................................... 183

9.3.1 Overview............................................................................................................. 183

9.3.2 Register Descriptions.......................................................................................... 185

9.3.3 Timer Operation.................................................................................................. 189

9.3.4 Timer C Operation States ................................................................................... 191

9.4 Timer F ........................................................................................................................... 192

9.4.1 Overview............................................................................................................. 192

9.4.2 Register Descriptions.......................................................................................... 195

9.4.3 CPU Interface ..................................................................................................... 203

9.4.4 Operation ............................................................................................................ 206

9.4.5 Application Notes ............................................................................................... 210

9.5 Timer G........................................................................................................................... 212

9.5.1 Overview............................................................................................................. 212

9.5.2 Register Descriptions.......................................................................................... 215

9.5.3 Noise Canceler.................................................................................................... 220

9.5.4 Operation ............................................................................................................ 222

9.5.5 Application Notes ............................................................................................... 226

9.5.6 Timer G Application Example............................................................................ 230

9.6 Watchdog Timer............................................................................................................. 232

9.6.1 Overview............................................................................................................. 232

9.6.2 Register Descriptions.......................................................................................... 233

9.6.3 Timer Operation.................................................................................................. 237

9.6.4 Watchdog Timer Operation States...................................................................... 238

9.7 Asynchronous Event Counter (AEC) ............................................................................. 239

9.7.1 Overview............................................................................................................. 239

9.7.2 Register Descriptions.......................................................................................... 241

9.7.3 Operation ............................................................................................................ 246

9.7.4 Asynchronous Event Counter Operation Modes ................................................ 247

9.7.5 Application Notes ............................................................................................... 248

Section 10 Serial Communication Interface............................................................... 249

10.1 Overview......................................................................................................................... 249

10.1.1 Features............................................................................................................... 249

10.1.2 Block diagram..................................................................................................... 251

10.1.3 Pin configuration................................................................................................ 252

10.1.4 Register configuration........................................................................................ 252

10.2 Register Descriptions...................................................................................................... 252

10.2.1 Receive shift register (RSR)............................................................................... 252

10.2.2 Receive data register (RDR)............................................................................... 253

10.2.3 Transmit shift register (TSR).............................................................................. 253

10.2.4 Transmit data register (TDR).............................................................................. 254

10.2.5 Serial mode register (SMR)................................................................................ 254

10.2.6 Serial control register 3 (SCR3)......................................................................... 257

10.2.7 Serial status register (SSR)................................................................................. 260

10.2.8 Bit rate register (BRR) ....................................................................................... 264

10.2.9 Clock stop register 1 (CKSTPR1)...................................................................... 268

10.2.10

10.3 Operation ........................................................................................................................ 271

10.3.1 Overview............................................................................................................. 271

10.3.2 Operation in Asynchronous Mode...................................................................... 275

10.3.3 Operation in Synchronous Mode........................................................................ 284

10.3.4 Multiprocessor Communication Function.......................................................... 291

10.4 Interrupts......................................................................................................................... 298

10.5 Application Notes........................................................................................................... 299

Serial Port Control Register (SPCR) .................................................................. 269

Section 11 14-Bit PWM ................................................................................................... 305

11.1 Overview......................................................................................................................... 305

11.1.1 Features............................................................................................................... 305

11.1.2 Block Diagram.................................................................................................... 305

11.1.3 Pin Configuration................................................................................................ 306

11.1.4 Register Configuration........................................................................................ 306

11.2 Register Descriptions...................................................................................................... 307

11.2.1 PWM Control Register (PWCR)........................................................................ 307

11.2.2 PWM Data Registers U and L (PWDRU, PWDRL).......................................... 308

11.2.3 Clock Stop Register 2 (CKSTPR2).................................................................... 308

11.3 Operation ........................................................................................................................ 310

11.3.1 Operation............................................................................................................ 310

11.3.2 PWM Operation Modes...................................................................................... 311

Section 12 A/D Converter................................................................................................ 313

12.1 Overview......................................................................................................................... 313

12.1.1 Features............................................................................................................... 313

12.1.2 Block Diagram.................................................................................................... 313

12.1.3 Pin Configuration................................................................................................ 314

12.1.4 Register Configuration........................................................................................ 314

12.2 Register Descriptions...................................................................................................... 315

12.2.1 A/D Result Registers (ADRRH, ADRRL)......................................................... 315

12.2.2 A/D Mode Register (AMR)................................................................................ 315

12.2.3 A/D Start Register (ADSR)................................................................................ 317

12.2.4 Clock Stop Register 1 (CKSTPR1).................................................................... 317

12.3 Operation ........................................................................................................................ 319

12.3.1 A/D Conversion Operation................................................................................. 319

12.3.2 Start of A/D Conversion by External Trigger Input........................................... 319

12.3.3 A/D Converter Operation Modes........................................................................ 320

12.4 Interrupts......................................................................................................................... 320

12.5 Typical Use..................................................................................................................... 320

12.6 Application Notes........................................................................................................... 323

Section 13 LCD Controller/Driver................................................................................ 325

13.1 Overview......................................................................................................................... 325

13.1.1 Features............................................................................................................... 325

13.1.2 Block Diagram.................................................................................................... 326

13.1.3 Pin Configuration................................................................................................ 327

13.1.4 Register Configuration........................................................................................ 327

13.2 Register Descriptions...................................................................................................... 328

13.2.1 LCD Port Control Register (LPCR)................................................................... 328

13.2.2 LCD Control Register (LCR)............................................................................. 331

13.2.3 LCD Control Register 2 (LCR2)........................................................................ 333

13.2.4 Clock Stop Register 2 (CKSTPR2).................................................................... 335

13.3 Operation ........................................................................................................................ 336

13.3.1 Settings up to LCD Display................................................................................ 336

13.3.2 Relationship between LCD RAM and Display.................................................. 339

13.3.3 Luminance Adjustment Function (V0 Pin)......................................................... 347

13.3.4 Step-Up Constant-Voltage (5 V) Power Supply................................................. 348

13.3.5 Low-Power-Consumption LCD Drive System................................................... 348

13.3.6 Operation in Power-Down Modes...................................................................... 352

13.3.7 Boosting the LCD Drive Power Supply............................................................. 353

13.3.8 Connection to HD66100..................................................................................... 354

Section 14 Power Supply Circuit................................................................................... 357

14.1 Overview......................................................................................................................... 357

14.2 When Using the Internal Power Supply Step-Down Circuit.......................................... 357

14.3 When Not Using the Internal Power Supply Step-Down Circuit................................... 358

Section 15 Electrical Characteristics............................................................................ 359

15.1 H8/3867 Series and H8/3827 Series Absolute Maximum Ratings................................. 359

15.2 H8/3867 Series and H8/3827 Series Electrical Characteristics...................................... 360

15.2.1 Power Supply Voltage and Operating Range..................................................... 360

15.2.2 DC Characteristics.............................................................................................. 363

15.2.3 AC Characteristics.............................................................................................. 369

15.2.4 A/D Converter Characteristics............................................................................ 372

15.2.5 LCD Characteristics............................................................................................ 373

15.3 Operation Timing............................................................................................................ 374

15.4 Output Load Circuit........................................................................................................ 378

15.5 Resonator Equivalent Circuit.......................................................................................... 378

Appendix A CPU Instruction Set .................................................................................. 379

A.1 Instructions ..................................................................................................................... 379

A.2 Operation Code Map....................................................................................................... 387

A.3 Number of Execution States........................................................................................... 389

Appendix B Internal I/O Registers................................................................................ 396

B.1 Addresses........................................................................................................................ 396

B.2 Functions......................................................................................................................... 400

Appendix C I/O Port Block Diagrams......................................................................... 449

C.1 Block Diagrams of Port 1............................................................................................... 449

C.2 Block Diagrams of Port 3............................................................................................... 453

C.3 Block Diagrams of Port 4............................................................................................... 460

C.4 Block Diagram of Port 5................................................................................................. 464

C.5 Block Diagram of Port 6................................................................................................. 465

C.6 Block Diagram of Port 7................................................................................................. 466

C.7 Block Diagrams of Port 8............................................................................................... 467

C.8 Block Diagram of Port A................................................................................................ 468

C.9 Block Diagram of Port B................................................................................................ 469

Appendix D Port States in the Different Processing States................................... 470

Appendix E List of Product Codes................................................................................ 471

Appendix F Package Dimensions.................................................................................. 473

Section 1 Overview

1.1 Overview

The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.

Within the H8/300L Series, the H8/3867 Series and H8/3827 Series comprise single-chip
microcomputers equipped with a controller/driver. Other on-chip peripheral functions include six
timers, a 14-bit pulse width modulator (PWM), two serial communication interface channels, and an
A/D converter. Together, these functions make the H8/3864 Series ideally suited for embedded
applications in systems requiring low power consumption and LCD display. Models in the H8/3867
and H8/3827 Series are the H8/3862 and H8/3822, with on-chip 16-kbyte ROM and 1-kbyte RAM,
the H8/3863 and H8/3823, with 24-kbyte ROM and 1-kbyte RAM, the H8/3864 and H8/3824, with
32-kbyte ROM and 2-kbyte RAM, the H8/3865 and H8/3825, with 40-kbyte ROM and 2-kbyte
RAM, the H8/3866 and H8/3826, with 48-kbyte ROM and 2-kbyte RAM, and the H8/3867 and
H8/3827, with 60-kbyte ROM and 2-kbyte RAM.

The H8/3867 and H8/3827 are also available in a ZTAT™* version with on-chip PROM which can
be programmed as required by the user.

Table 1-1 summarizes the features of the H8/3867 Series and H8/3827 Series.
Note: * ZTAT (Zero Turn Around Time) is a trademark of Hitachi, Ltd.

Table 1-1 Features

Item Description

CPU High-speed H8/300L CPU

• General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit

registers)

• Operating speed
— Max. operating speed: 3 MHz
— Add/subtract: 0.67 µs (operating at 3 MHz)
— Multiply/divide: 4.67 µs (operating at 3 MHz)
— Can run on 32.768 kHz or 38.4 kHz subclock

• Instruction set compatible with H8/300 CPU
— Instruction length of 2 bytes or 4 bytes
— Basic arithmetic operations between registers
— MOV instruction for data transfer between memory and registers

• Typical instructions
— Multiply (8 bits
— Divide (16 bits ÷ 8 bits)
— Bit accumulator
— Register-indirect designation of bit position

× 8 bits)

1

Table 1-1 Features (cont)

Item Description

Interrupts 36 interrupt sources

• 13 external interrupt sources (IRQ

• 23 internal interrupt sources

Clock pulse generators Two on-chip clock pulse generators

• System clock pulse generator: 0.4 to 6 MHz

• Subclock pulse generator: 32.768 kHz, 38.4 kHz

Power-down modes Seven power-down modes

• Sleep (high-speed) mode

• Sleep (medium-speed) mode

• Standby mode

• Watch mode

• Subsleep mode

• Subactive mode

• Active (medium-speed) mode

Memory Large on-chip memory

• H8/3862, H8/3822: 16-kbyte ROM, 1-kbyte RAM

• H8/3863, H8/3823: 24-kbyte ROM, 1-kbyte RAM

• H8/3864, H8/3824: 32-kbyte ROM, 2-kbyte RAM

• H8/3865, H8/3825: 40-kbyte ROM, 2-kbyte RAM

• H8/3866, H8/3826: 48-kbyte ROM, 2-kbyte RAM

• H8/3867, H8/3827: 60-kbyte ROM, 2-kbyte RAM

I/O ports 64 pins

• 55 I/O pins

• 9 input pins

Timers Six on-chip timers

• Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from

the system clock (ø)* and four clock signals divided from the watch clock

)*

(ø

w

• Asynchronous event counter: 16-bit timer
— Count-up timer able to count asynchronous external events

independently of the MCU's internal clocks

Note: * See section 4, Clock Pulse Generator, for the definition of ø and ø

to IRQ0, WKP7to WKP0)

4

.

w

2

Table 1-1 Features (cont)

Item Description

Timers • Timer C: 8-bit timer

— Count-up/down timer with selection of seven internal clock signals or

event input from external pin

— Auto-reloading

• Timer F: 16-bit timer
— Can be used as two independent 8-bit timers
— Count-up timer with selection of four internal clock signals or event

input from external pin

— Provision for toggle output by means of compare-match function

• Timer G: 8-bit timer

— Count-up timer with selection of four internal clock signals
— Incorporates input capture function (built-in noise canceler)

• Watchdog timer

— Reset signal generated by overflow of 8-bit counter

Serial communication Two serial communication interface channels on chip
interface

14-bit PWM Pulse-division PWM output for reduced ripple

A/D converter Successive approximations using a resistance ladder

LCD controller/driver LCD controller/driver equipped with a maximum of 32 segment pins and

LCD drive power Step-up constant-voltage power supply allows LCD display
supply (H8/3867 Series only)

• SCI3-1: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function

• SCI3-2: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function

• Can be used as a 14-bit D/A converter by connecting to an external
low-pass filter.

• 8-channel analog input pins

• Conversion time: 31/ø or 62/ø per channel

four common pins

• Choice of four duty cycles (static, 1/2, 1/3, or 1/4)

• Segment pins can be switched to general-purpose port function in 8-bit
units

3

Table 1-1 Features (cont)

Item Specification
Product lineup Product Code

Mask ROM ZTAT
Version Version Package ROM/RAM Size

HD6433862H, — 80-pin QFP (FP-80A) ROM 16 kbytes
HD6433822H RAM 1 kbyte

HD6433862F, — 80-pin QFP (FP-80B)
HD6433822F

HD6433862W, — 80-pin TQFP (TFP-80C)
HD6433822W

HD6433863H, — 80-pin QFP (FP-80A) ROM 24 kbytes
HD6433823H RAM 1 kbyte

HD6433863F, — 80-pin QFP (FP-80B)
HD6433823F

HD6433863W, — 80-pin TQFP (TFP-80C)
HD6433823W

HD6433864H, — 80-pin QFP (FP-80A) ROM 32 kbytes
HD6433824H RAM 2 kbytes

HD6433864F, — 80-pin QFP (FP-80B)
HD6433824F

HD6433864W, — 80-pin TQFP (TFP-80C)
HD6433824W

HD6433865H, — 80-pin QFP (FP-80A) ROM 40 kbytes
HD6433825H RAM 2 kbytes

HD6433865F, — 80-pin QFP (FP-80B)
HD6433825F

HD6433865W, — 80-pin TQFP (TFP-80C)
HD6433825W

HD6433866H, — 80-pin QFP (FP-80A) ROM 48 kbytes
HD6433826H RAM 2 kbytes

HD6433866F, — 80-pin QFP (FP-80B)
HD6433826F

HD6433866W, — 80-pin TQFP (TFP-80C)
HD6433826W

HD6433867H, HD6473867H, 80-pin QFP (FP-80A) ROM 60 kbytes
HD6433827H HD6473827H RAM 2 kbytes

HD6433867F, HD6473867F, 80-pin QFP (FP-80B)
HD6433827F HD6473827F

HD6433867W, HD6473867W, 80-pin TQFP (TFP-80C)
HD6433827W HD6473827W

4

1.2 Internal Block Diagram

P10/TMOW

P1

1/TMOFL

P1

2/TMOFH

P1

3/TMIG

P14/IRQ4/ADTRG

P1

5/IRQ1/TMIC

P1

6/IRQ2

P17/IRQ3/TMIF

P30/PWM

P3

1/UD

P3

2/RESO

P3

3/SCK31

P34/RXD31
P35/TXD31
P36/AEVH

P3

7/AEVL

P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8

P40/SCK32
P41/RXD32
P42/TXD32

P43/IRQ0

OSC1

OSC2

System Clock

OSC

Port 1

Port APort 8Port 7Port 6

Port 3Port 4Port 5

X1

X2

Sub Clock

OSC

VSS

VSS

VCC

CVCC

RES

TEST

H8/300L

CPU

LCD Power

Supply

ROM

(60k/48k/40k/32k

24k/16k)

RAM

(2k/1k)

Timer - A

Timer - C

Timer - F

Timer - G

Asynchronous

counter

Serial

communication

interface 3-1

Serial

communication

interface 3-2

14-bit
PWM

WDT

LCD

Controller

A/D

(10bit)

V0
V1
V2
V3

PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1

P87/SEG32/CL1
P86/SEG31/CL2
P85/SEG30/DO
P8

4/SEG29/M

P8

3/SEG28

P82/SEG27
P81/SEG26
P80/SEG25

P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17

P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9

Port B

AVCC

AVSS

PB0/AN0

PB1/AN1

PB2/AN2

PB3/AN3

PB4/AN4

PB5/AN5

PB6/AN6

PB7/AN7

Figure 1-1 shows a block diagram of the H8/3867 Series and H8/3827 Series.

Figure 1-1 Block Diagram

5

1.3 Pin Arrangement and Functions

P77/SEG24

P7

6/SEG23P75/SEG22P74/SEG21P73/SEG20P72/SEG19P71/SEG18P70/SEG17P67/SEG16P66/SEG15P65/SEG14P64/SEG13P63/SEG12P62/SEG11P61/SEG10P60/SEG9P57/WKP7/SEG8P56/WKP6/SEG7P55/WKP5/SEG6P54/WKP4/SEG5

P80/SEG25
P8

1/SEG26

P8

2/SEG27

P8

3/SEG28

P8

4/SEG29/M

P8

5/SEG30/DO

P8

6/SEG31CL2

P87/SEG32CL1

P40/SCK32
P41/RXD32
P42/TXD32

P43/IRQ0

AVCC
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6

PB7/AN7

AVSS

X1X

2

VSS

OSC2OSC

1

TEST

RES

P1

0/TMOW

P1

1/TMOFL

P1

2/TMOFH

P1

3/TMIG

P1

4/IRQ4/ADTRG

P1

5/IRQ1/TMIC

P1

6/IRQ2

P17/IRQ3/TMIF

P3

0/PWM

P3

1/UD

P3

2/RESO

P53/WKP3/SEG4
P5

2/WKP2/SEG3

P5

1/WKP1/SEG2

P5

0/WKP0/SEG1

PA

0/COM1

PA

1/COM2

PA

2/COM3

PA

3/COM4

V

CC

V0
V1
V2
V3
V

SS

CVCC
P37/AEVL
P3

6/AEVH

P3

5/TXD31

P34/RXD31
P33/SCK31

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

605958

57

56 55

54 53

52 51 50

494847

46

454443

42 41

123456789

10

11

12

13 14

15

16

17 18 19 20

1.3.1 Pin Arrangement

The H8/3867 Series and H8/3827 Series pin arrangement is shown in figures 1-2 and 1-3.

Figure 1-2 Pin Arrangement (FP-80A, TFP-80C: Top View)

6

PB5/AN5

PB6/AN6

PB7/AN7

AVSS

X1X

2

VSS

OSC2OSC

1

TEST

RES

P1

0/TMOW

P1

1/TMOFL

P1

2/TMOFH

P1

3/TMIG

P1

4/IRQ4/ADTRG

P1

5/IRQ1/TMIC

P1

6/IRQ2

P17/IRQ3/TMIF

P3

0/PWM

P3

1/UD

P3

2/RESO

P3

3/SCK31

P34/RXD31

54

P81/SEG26

P8

0/SEG25P77/SEG24P76/SEG23P75/SEG22P74/SEG21P73/SEG20P72/SEG19P71/SEG18P70/SEG17P67/SEG16P66/SEG15P65/SEG14P64/SEG13P63/SEG12P62/SEG11P61/SEG10P60/SEG9P57/WKP7/SEG8P56/WKP6/SEG7P55/WKP5/SEG6P54/WKP4/SEG5P53/WKP3/SEG4P52/WKP2/SEG3

P82/SEG27
P8

3/SEG28

P8

4/SEG29/M

P8

5/SEG30/DO

P8

6/SEG31/CL2

P87/SEG32/CL1

P40/SCK32

P41/RXD32

P42/TXD32

P43/IRQ0

AVCC
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4

P51/WKP1/SEG2
P5

0/WKP0/SEG1

PA

0/COM1

PA

1/COM2

PA

2/COM3

PA

3/COM4

V

CC

V0
V1
V2
V3
V

SS

CVCC
P37/AEVL
P3

6/AEVH

P3

5/TXD31

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

64 63 62

61

60

59 58

57

56

55

53

525150

494847

46 45 44

43 42 41

1 2 3 4 5 6 7 8 9 101112131415161718192021222324

Figure 1-3 Pin Arrangement (FP-80B: Top View)

7

1.3.2 Pin Functions

Table 1-2 outlines the pin functions of the H8/3864 Series.

Table 1-2 Pin Functions

Pin No.

FP-80A

Type Symbol TFP-80C FP-80B I/O Name and Functions

Power V
source pins CV

Clock pins OSC

CC

V

SS

AV

AV

V

0

V

1

V

2

V

3

OSC

X

1

X

2

CC

CC

SS

1
2

System RES 9 11 Input Reset: When this pin is driven low,
control the chip is reset

RESO 20 22 Output Reset output: Outputs the CPU internal

32 34 Input Power supply: All VCCpins should be
26 28 connected to the system power supply.

See section 14, Power Supply Circuit.

5 7 Input Ground: All VSSpins should be
27 29 connected to the system power supply

(0 V).

73 75 Input Analog power supply: This is the

power supply pin for the A/D converter.
When the A/D converter is not used,
connect this pin to the system power
supply.

2 4 Input Analog ground: This is the A/D

converter ground pin. It should be
connected to the system power supply
(0V).

31 33 Output LCD power supply: These are the
30 32 Input

29 31
28 30

power supply pins for the LCD controller/
driver. They incorporate a power supply
split-resistance, and are normally used
with V

and V1shorted.

0

7 9 Input These pins connect to a
6 8 Output

crystal or ceramic oscillator, or can be
used to input an external clock.
See section 4, Clock Pulse
Generators, for a typical connection
diagram.

3 5 Input These pins connect to a 32.768-kHz
4 6 Output

or 38.4-kHz crystal oscillator.
See section 4, Clock Pulse
Generators, for a typical connection
diagram.

reset signal.

8

Table 1-2 Pin Functions (cont)

Pin No.

FP-80A

Type Symbol TFP-80C FP-80B I/O Name and Functions

System TEST 8 10 Output Test pin: This pin is reserved and
control cannot be used. It should be connected

to VSS.

Interrupt IRQ
pins IRQ

IRQ
IRQ
IRQ

0
1
2
3
4

WKP
WKP

Timer pins TMOW 10 12 Output Clock output: This is an output pin for

AEVL 25 27 Input Asynchronous event counter event
AEVH 24 26 input: This is an event input pin for input

TMIC 15 17 Input Timer C event input: This is an event

UD 19 21 Input Timer C up/down select: This pin

TMIF 17 19 Input Timer F event input: This is an event

TMOFL 11 13 Output Timer FL output: This is an output pin

TMOFH 12 14 Output Timer FH output: This is an output pin

TMIG 13 15 Input Timer G capture input: This is an input

72 74 Input IRQ interrupt request 0 to 4: These
15 17 are input pins for edge-sensitive external
16 18 interrupts, with a selection of rising or
17 19 falling edge
14 16

to 44 to 46 to Input Wakeup interrupt request 0 to 7:

7

37 39 These are input pins for rising or falling-

0

edge-sensitive external interrupts.

waveforms generated by the timer A
output circuit.

to the asynchronous event counter.

input pin for input to the timer C counter.

selects up- or down-counting for the
timer C counter. The counter operates
as an up-counter when this pin is high,
and as a down-counter when low.

input pin for input to the timer F counter.

for waveforms generated by the timer FL
output compare function.

for waveforms generated by the timer
FH output compare function.

pin for timer G input capture.

9

Table 1-2 Pin Functions (cont)

Pin No.

FP-80A

Type Symbol TFP-80C FP-80B I/O Name and Functions

14-bit PWM 18 20 Output 14-bit PWM output: This is an output
PWM pin pin for waveforms generated by the

14-bit PWM

I/O ports PB

to 1, 3 to 1, Input Port B: This is an 8-bit input port.

7

PB

0

P4

3

to P4071 to 69 73 to 71 I/O Port 4 (bits 2 to 0): This is a 3-bit I/O

P4

2

80 to 74 80 to 76
72 74 Input Port 4 (bit 3): This is a 1-bit input port.

port. Input or output can be designated
for each bit by means of port control
register 4 (PCR4).

to 33 to 36 35 to 38 I/O Port A: This is a 4-bit I/O port. Input or

PA

3

PA

0

output can be designated for each bit by
means of port control register A (PCRA).

to 17 to 10 19 to 12 I/O Port 1: This is an 8-bit I/O port. Input or

P1

7

P1

0

output can be designated for each bit by
means of port control register 1 (PCR1).

to 25 to 18 27 to 20 I/O Port 3: This is an 8-bit I/O port. Input or

P3

7

P3

0

output can be designated for each bit by
means of port control register 3 (PCR3).

to 44 to 37 46 to 39 I/O Port 5: This is an 8-bit I/O port. Input or

P5

7

P5

0

output can be designated for each bit by
means of port control register 5 (PCR5).

to 52 to 45 54 to 47 I/O Port 6: This is an 8-bit I/O port. Input or

P6

7

P6

0

output can be designated for each bit by
means of port control register 6 (PCR6).

to 60 to 53 62 to 55 I/O Port 7: This is an 8-bit I/O port. Input or

P7

7

P7

0

output can be designated for each bit by
means of port control register 7 (PCR7).

to 68 to 61 70 to 63 I/O Port 8: This is an 8-bit I/O port. Input or

P8

7

P8

0

output can be designated for each bit by
means of port control register 8 (PCR8).

10

Table 1-2 Pin Functions (cont)

Pin No.

FP-80A

Type Symbol TFP-80C FP-80B I/O Name and Functions

Serial RXD

31

communi- This is the SCI31 data input pin.
cation
interface

TXD

31

(SCI)

SCK

31

RXD

32

TXD

32

SCK

32

A/D AN7 to 1 3 to 1 Input Analog input channels 7 to 0:
converter An0 80 to 74 80 to 76 These are analog data input channels

ADTRG 14 16 Input A/D converter trigger input:

LCD COM
controller/ COM

driver

SEG
SEG

32
1

CL1 68 70 Output LCD latch clock: This is the output pin

CL2 67 69 Output LCD shift clock: This is the output pin

DO 66 68 Output LCD serial data output: This is the

M 65 67 Output LCD alternation signal: This is the

22 24 Input SCI3-1 receive data input:

23 25 Output SCI3-1 transmit data output:

This is the SCI31 data output pin.

21 23 I/O SCI3-1 clock I/O:

This is the SCI31 clock I/O pin.

70 72 Input SCI3-2 receive data input:

This is the SCI32 data input pin.

71 73 Output SCI3-2 transmit data output:

This is the SCI32 data output pin.

69 71 I/O SCI3-2 clock I/O:

This is the SCI32 clock I/O pin.

to the A/D converter

This is the external trigger input pin to
the A/D converter

to 33 to 36 35 to 38 Output LCD common output: These are the

4
1

LCD common output pins.

to 68 to 37 70 to 39 Output LCD segment output: These are the

LCD segment output pins.

for the segment external expansion
display data latch clock.

for the segment external expansion
display data shift clock.

output pin for segment external
expansion serial display data.

output pin for the segment external
expansion LCD alternation signal.

11

Section 2 CPU

2.1 Overview

The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.

2.1.1 Features

Features of the H8/300L CPU are listed below.

• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers

• Instruction set with 55 basic instructions, including:
— Multiply and divide instructions
— Powerful bit-manipulation instructions

• Eight addressing modes
— Register direct
— Register indirect
— Register indirect with displacement
— Register indirect with post-increment or pre-decrement
— Absolute address
— Immediate
— Program-counter relative
— Memory indirect

• 64-kbyte address space

• High-speed operation
— All frequently used instructions are executed in two to four states
— High-speed arithmetic and logic operations
— 8- or 16-bit register-register add or subtract: 0.67 µs*
—8 × 8-bit multiply: 4.67 µs*
— 16 ÷ 8-bit divide: 4.67 µs*

Note: * These values are at ø = 3 MHz.

• Low-power operation modes
SLEEP instruction for transfer to low-power operation

13

2.1.2 Address Space

7070

15 0

PC

R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H

R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L

(SP)

SP: Stack pointer

PC: Program counter

CCR: Condition code register
Carry flag

Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit

CCR I U H U N Z V C

General registers (Rn)

Control registers (CR)

75321064

The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data.

See 2.8, Memory Map, for details of the memory map.

2.1.3 Register Configuration

Figure 2-1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.

Figure 2-1 CPU Registers

14

2.2 Register Descriptions

Lower address side [H'0000]

Upper address side [H'FFFF]

Unused area

Stack area

SP (R7)

2.2.1 General Registers

All the general registers can be used as both data registers and address registers.

When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.

When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).

R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing and
subroutine calls. When it functions as the stack pointer, as indicated in figure 2-2, SP (R7) points to
the top of the stack.

Figure 2-2 Stack Pointer

2.2.2 Control Registers

The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).

Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU
will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the
PC is ignored (always regarded as 0).

15

Condition Code Register (CCR): This 8-bit register contains internal status information, including
the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C)
flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and
XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional
branching (Bcc) instructions.

Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written by
software. For further details, see section 3.3, Interrupts.

Bit 6—User Bit (U): Can be used freely by the user.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B

instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.

The H flag is used implicitly by the DAA and DAS instructions.

When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.

Bit 4—User Bit (U): Can be used freely by the user.

Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an

instruction.

Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.

Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions, to store the value shifted out of the end bit

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave some or all of the flag bits unchanged.

Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits.

16

2.2.3 Initial Register Values

When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000
in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers
are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be
initialized by software, by the first instruction executed after a reset.

2.3 Data Formats

The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.

• Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).

• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.

• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.

• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in packed
BCD form. Each nibble of the byte is treated as a decimal digit.

17

2.3.1 Data Formats in General Registers

76543210 don’t care

Data Type Register No. Data Format

70

1-bit data RnH

76543210don’t care

70

1-bit data RnL

MSB LSB don’t care

70

Byte data RnH

Byte data RnL

Word data Rn

4-bit BCD data RnH

4-bit BCD data RnL

Notation:
RnH:
RnL:
MSB:
LSB:

Upper byte of general register
Lower byte of general register
Most significant bit
Least significant bit

MSB LSBdon’t care

70

MSB LSB

15 0

Upper digit Lower digit

don’t care

7034

don’t care

Upper digit Lower digit

70

34

Data of all the sizes above can be stored in general registers as shown in figure 2-3.

Figure 2-3 Register Data Formats

18

2.3.2 Memory Data Formats

Data Format

76543210

AddressData Type

70

Address n

MSB LSB

MSB

LSB

Upper 8 bits
Lower 8 bits

MSB LSBCCR

CCR*

MSB

LSB

MSB LSB

Address n

Even address

Odd address

Even address

Odd address

Even address

Odd address

1-bit data

Byte data

Word data

Byte data (CCR) on stack

Word data on stack

CCR: Condition code register
Note: Ignored on return*

Figure 2-4 indicates the data formats in memory. The H8/300L CPU can access word data stored in
memory (MOV.W instruction), but the word data must always begin at an even address. If word
data starting at an odd address is accessed, the least significant bit of the address is regarded as 0,
and the word data starting at the preceding address is accessed. The same applies to instruction
codes.

Figure 2-4 Memory Data Formats

When the stack is accessed using R7 as an address register, word access should always be
performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to
make a complete word. When they are restored, the lower byte is ignored.

19

2.4 Addressing Modes

2.4.1 Addressing Modes

The H8/300L CPU supports the eight addressing modes listed in table 2-1. Each instruction uses a
subset of these addressing modes.

Table 2-1 Addressing Modes

No. Address Modes Symbol

1 Register direct Rn
2 Register indirect @Rn
3 Register indirect with displacement @(d:16, Rn)
4 Register indirect with post-increment @Rn+

Register indirect with pre-decrement @–Rn
5 Absolute address @aa:8 or @aa:16
6 Immediate #xx:8 or #xx:16
7 Program-counter relative @(d:8, PC)
8 Memory indirect @@aa:8

1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general

register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and

DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.

2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general

register containing the address of the operand in memory.

3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word

(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.

This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address
must be even.

20

4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:

• Register indirect with post-increment—@Rn+

The @Rn+ mode is used with MOV instructions that load registers from memory.

The register field of the instruction specifies a 16-bit general register containing the address
of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B
or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be
even.

• Register indirect with pre-decrement—@–Rn

The @–Rn mode is used with MOV instructions that store register contents to memory.

The register field of the instruction specifies a 16-bit general register which is decremented
by 1 or 2 to obtain the address of the operand in memory. The register retains the
decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.

5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the

operand in memory.

The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and
JSR instructions can use 16-bit absolute addresses.

For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).

6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second

byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can
contain 16-bit immediate values.

The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some
bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.

7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR instructions.

An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to
the program counter contents to generate a branch destination address. The possible branching
range is –126 to +128 bytes (–63 to +64 words) from the current address. The displacement
should be an even number.

21

8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The

second byte of the instruction code specifies an 8-bit absolute address. The word located at this
address contains the branch destination address.

The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the
address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area.

If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.

2.4.2 Effective Address Calculation

Table 2-2 shows how effective addresses are calculated in each of the addressing modes.

Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).

Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).

Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST
instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position in
the operand.

22

Table 2-2 Effective Address Calculation

Addressing Mode and
Instruction Format

op rm

76 34015

No. Effective Address Calculation Method Effective Address (EA)

1 Register direct, Rn

Operand is contents of registers indicated by rm/rn

Register indirect, @Rn

Contents (16 bits) of register

indicated by rm

015

Register indirect with displacement,
@(d:16, Rn)

op rm rn

87 34015

op rm

76 34015

disp

op rm

76 34015

Register indirect with
post-increment, @Rn+

op rm

76 34015

Register indirect with pre-decrement,
@–Rn

2

3

4

Incremented or decremented
by 1 if operand is byte size,
and by 2 if word size

015

disp

015

015

015

1 or 2

015

015

1 or 2

015

rm

30rn30

Contents (16 bits) of register

indicated by rm

Contents (16 bits) of register

indicated by rm

Contents (16 bits) of register

indicated by rm

23

Table 2-2 Effective Address Calculation (cont)

Addressing Mode and
Instruction Format No. Effective Address Calculation Method Effective Address (EA)

5 Absolute address

@aa:8

Operand is 1- or 2-byte immediate data

@aa:16

op

87 015

op

015

IMM

op disp

7015

Program-counter relative
@(d:8, PC)

6

7

015

PC contents

015

015

abs

H'FF

87 015

015

abs

op

#xx:16

op

87 015

IMM

Immediate
#xx:8

8

Sign extension disp

24

Table 2-2 Effective Address Calculation (cont)

Addressing Mode and
Instruction Format No. Effective Address Calculation Method Effective Address (EA)

8 Memory indirect, @@aa:8

op

87 015

Memory contents (16 bits)

015

abs

H'00

87 015

Notation:
rm, rn:
op:
disp:
IMM:
abs:

Register field
Operation field
Displacement
Immediate data
Absolute address

abs

25

2.5 Instruction Set

The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2-3.

Table 2-3 Instruction Set

Function Instructions Number

Data transfer MOV, PUSH*1, POP
Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, 14

SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG
Logic operations AND, OR, XOR, NOT 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, 8

ROTXL, ROTXR
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, 14

BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
Branch Bcc*2, JMP, BSR, JSR, RTS 5
System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 8
Block data transfer EEPMOV 1

Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.

POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine language.

2. Bcc is a conditional branch instruction in which cc represents a condition code.

*1

1

Total: 55

The following sections give a concise summary of the instructions in each category, and indicate the
bit patterns of their object code. The notation used is defined next.

26

Notation

Rd General register (destination)
Rs General register (source)
Rn General register
(EAd), <EAd> Destination operand
(EAs), <EAs> Source operand
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction

× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
→ Move

~ Logical negation (logical complement)
:3 3-bit length
:8 8-bit length
:16 16-bit length
( ), < > Contents of operand indicated by effective address

27

2.5.1 Data Transfer Instructions

Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats.

Table 2-4 Data Transfer Instructions

Instruction Size* Function

MOV B/W (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.

The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for word data. The @aa:8 addressing
mode is available for byte data only.

The @–R7 and @R7+ modes require word operands. Do not specify
byte size for these two modes.

POP W @SP+ → Rn

Pops a 16-bit general register from the stack. Equivalent to MOV.W
@SP+, Rn.

PUSH W Rn → @–SP

Pushes a 16-bit general register onto the stack. Equivalent to MOV.W
Rn, @–SP.

Notes: * Size: Operand size

B: Byte
W: Word

Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details.

28

15 087

op rm rn

MOV
Rm→Rn

15 087

op rm rn

@Rm←→Rn

15 087

op rm rn

@(d:16, Rm)←→Rn

disp

15 087

op rm rn

@Rm+→Rn, or
Rn →@–Rm

15 087

op rn abs

@aa:8←→Rn

15 087

op rn

@aa:16←→Rn

abs

15 087

op rn IMM

#xx:8→Rn

15 087

op rn

#xx:16→Rn

IMM

15 087

op rn

PUSH, POP

Notation:
op:
rm, rn:
disp:
abs:
IMM:

Operation field
Register field
Displacement
Absolute address
Immediate data

@SP+ Rn, or
Rn @–SP

→

→

111

Figure 2-5 Data Transfer Instruction Codes

29

2.5.2 Arithmetic Operations

Table 2-5 describes the arithmetic instructions.

Table 2-5 Arithmetic Instructions

Instruction Size* Function

ADD B/W Rd ± Rs → Rd, Rd + #IMM → Rd
SUB Performs addition or subtraction on data in two general registers, or

addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word
data can be added or subtracted only when both words are in general
registers.

ADDX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
SUBX Performs addition or subtraction with carry or borrow on byte data in

two general registers, or addition or subtraction on immediate data and
data in a general register.

INC B Rd ± 1 → Rd
DEC Increments or decrements a general register by 1.

ADDS W Rd ±1 → Rd, Rd ± 2 → Rd
SUBS Adds or subtracts 1 or 2 to or from a general register

DAA B Rd decimal adjust → Rd
DAS Decimal-adjusts (adjusts to 4-bit BCD) an addition or subtraction

result in a general register by referring to the CCR

MULXU B Rd × Rs → Rd

Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result

DIVXU B Rd ÷ Rs → Rd

Performs 16-bit ÷ 8-bit unsigned division on data in two general registers,
providing an 8-bit quotient and 8-bit remainder

CMP B/W Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register
or with immediate data, and indicates the result in the CCR. Word data
can be compared only between two general registers.

NEG B 0 – Rd → Rd

Obtains the two’s complement (arithmetic complement) of data in a
general register

Notes: * Size: Operand size

B: Byte
W: Word

30

2.5.3 Logic Operations

Table 2-6 describes the four instructions that perform logic operations.

Table 2-6 Logic Operation Instructions

Instruction Size* Function

AND B Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another
general register or immediate data

OR B Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another
general register or immediate data

XOR B Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and
another general register or immediate data

NOT B ~ Rd → Rd

Obtains the one’s complement (logical complement) of general register
contents

Notes: * Size: Operand size

B: Byte

2.5.4 Shift Operations

Table 2-7 describes the eight shift instructions.

Table 2-7 Shift Instructions

Instruction Size* Function

SHAL B Rd shift → Rd
SHAR

SHLL B Rd shift → Rd
SHLR

ROTL B Rd rotate → Rd
ROTR

ROTXL B Rd rotate through carry → Rd
ROTXR

Notes: * Size: Operand size

B: Byte

Performs an arithmetic shift operation on general register contents

Performs a logical shift operation on general register contents

Rotates general register contents

Rotates general register contents through the C (carry) bit

31

Figure 2-6 shows the instruction code format of arithmetic, logic, and shift instructions.

15 087

op rm rn

ADD, SUB, CMP,
ADDX, SUBX (Rm)

Notation:
op:
rm, rn:
IMM:

Operation field
Register field
Immediate data

15 087

op rn

ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT

15 087

op rn

MULXU, DIVXU

rm

15 087

rn IMM

ADD, ADDX, SUBX,
CMP (#XX:8)

op

15 087

op rn

AND, OR, XOR (Rm)

rm

15 087

rn IMM

AND, OR, XOR (#xx:8)

op

15 087

rn

SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR

op

Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes

32

2.5.5 Bit Manipulations

Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code formats.

Table 2-8 Bit-Manipulation Instructions

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory to 1. The bit number
is specified by 3-bit immediate data or the lower three bits of a general
register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.

BNOT B ~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory. The bit number is
specified by 3-bit immediate data or the lower three bits of a general
register.

BTST B ~ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory and sets or clears
the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the C flag with a specified bit in a general register or memory, and
stores the result in the C flag.

BIAND B C ∧ [~ (<bit-No.> of <EAd>)] → C

ANDs the C flag with the inverse of a specified bit in a general register or
memory, and stores the result in the C flag.

The bit number is specified by 3-bit immediate data.

BOR B C ∨ (<bit-No.> of <EAd>) → C

ORs the C flag with a specified bit in a general register or memory, and
stores the result in the C flag.

BIOR B C ∨ [~ (<bit-No.> of <EAd>)] → C

ORs the C flag with the inverse of a specified bit in a general register or
memory, and stores the result in the C flag.

The bit number is specified by 3-bit immediate data.

Notes: * Size: Operand size

B: Byte

33

Table 2-8 Bit-Manipulation Instructions (cont)

Instruction Size* Function

BXOR B C ⊕ (<bit-No.> of <EAd>) → C

XORs the C flag with a specified bit in a general register or memory, and
stores the result in the C flag.

BIXOR B C ⊕ [~(<bit-No.> of <EAd>)] → C

XORs the C flag with the inverse of a specified bit in a general register or
memory, and stores the result in the C flag.

The bit number is specified by 3-bit immediate data.

BLD B (<bit-No.> of <EAd>) → C

Copies a specified bit in a general register or memory to the C flag.

BILD B ~ (<bit-No.> of <EAd>) → C

Copies the inverse of a specified bit in a general register or memory to
the C flag.

The bit number is specified by 3-bit immediate data.

BST B C → (<bit-No.> of <EAd>)

Copies the C flag to a specified bit in a general register or memory.

BIST B ~ C → (<bit-No.> of <EAd>)

Copies the inverse of the C flag to a specified bit in a general register or
memory.

The bit number is specified by 3-bit immediate data.

Notes: * Size: Operand size

B: Byte

Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for
details.

34

15 087

op IMM rn

Operand:
Bit No.:

Notation:
op:
rm, rn:
abs:
IMM:

Operation field
Register field
Absolute address
Immediate data

15 087

op rn

BSET, BCLR, BNOT, BTST

register direct (Rn)
immediate (#xx:3)

Operand:
Bit No.:

register direct (Rn)
register direct (Rm)

rm

15 087

op 0

Operand:
Bit No.:

register indirect (@Rn)
immediate (#xx:3)

rn

0000000IMM

15 087

op 0

Operand:
Bit No.:

register indirect (@Rn)
register direct (Rm)

rn

0000000rmop

15 087

op

Operand:
Bit No.:

absolute (@aa:8)
immediate (#xx:3)

abs

0000IMM

op

op

15 087

op

Operand:
Bit No.:

absolute (@aa:8)
register direct (Rm)

abs

0000rmop

15 087

op IMM rn

Operand:
Bit No.:

register direct (Rn)
immediate (#xx:3)

BAND, BOR, BXOR, BLD, BST

15 087

op 0

Operand:
Bit No.:

register indirect (@Rn)
immediate (#xx:3)

rn

0000000IMMop

15 087

op

Operand:
Bit No.:

absolute (@aa:8)
immediate (#xx:3)

abs

0000IMMop

Figure 2-7 Bit Manipulation Instruction Codes

35

Figure 2-7 Bit Manipulation Instruction Codes (cont)

Notation:
op:
rm, rn:
abs:
IMM:

Operation field
Register field
Absolute address
Immediate data

15 087

op IMM rn

Operand:
Bit No.:

register direct (Rn)
immediate (#xx:3)

BIAND, BIOR, BIXOR, BILD, BIST

15 087

op 0

Operand:
Bit No.:

register indirect (@Rn)
immediate (#xx:3)

rn

0000000IMMop

15 087

op

Operand:
Bit No.:

absolute (@aa:8)
immediate (#xx:3)

abs

0000IMMop

36

2.5.6 Branching Instructions

Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats.

Table 2-9 Branching Instructions

Instruction Size Function

Bcc — Branches to the designated address if condition cc is true. The branching

conditions are given below.

Mnemonic Description Condition

BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC (BHS) Carry clear (high or same) C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1

JMP — Branches unconditionally to a specified address
BSR — Branches to a subroutine at a specified address
JSR — Branches to a subroutine at a specified address
RTS — Returns from a subroutine

37

Notation:
op:
cc:
rm:
disp:
abs:

Operation field
Condition field
Register field
Displacement
Absolute address

15 087

op cc disp

Bcc

15 087

op rm 0

JMP (@Rm)

000

15 087

op

JMP (@aa:16)

abs

15 087

op abs

JMP (@@aa:8)

15 087

op disp

BSR

15 087

op rm 0

JSR (@Rm)

000

15 087

op

JSR (@aa:16)

abs

15 087

op abs

JSR (@@aa:8)

15 087

op

RTS

Figure 2-8 Branching Instruction Codes

38

2.5.7 System Control Instructions

Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats.

Table 2-10 System Control Instructions

Instruction Size* Function

RTE — Returns from an exception-handling routine
SLEEP — Causes a transition from active mode to a power-down mode. See

section 5, Power-Down Modes, for details.

LDC B Rs → CCR, #IMM → CCR

Moves immediate data or general register contents to the condition code
register

STC B CCR → Rd

Copies the condition code register to a specified general register

ANDC B CCR ∧ #IMM → CCR

Logically ANDs the condition code register with immediate data

ORC B CCR ∨ #IMM → CCR

Logically ORs the condition code register with immediate data

XORC B CCR ⊕ #IMM → CCR

Logically exclusive-ORs the condition code register with immediate data

NOP — PC + 2 → PC

Only increments the program counter

Notes: * Size: Operand size

B: Byte

39

Figure 2-9 System Control Instruction Codes

Notation:
op:
rn:
IMM:

Operation field
Register field
Immediate data

15 087

op

RTE, SLEEP, NOP

15 087

op rn

LDC, STC (Rn)

15 087

op IMM

ANDC, ORC,
XORC, LDC (#xx:8)

2.5.8 Block Data Transfer Instruction

Table 2-11 describes the block data transfer instruction. Figure 2-10 shows its object code format.

Table 2-11 Block Data Transfer Instruction

Instruction Size Function

EEPMOV — If R4L ≠ 0 then

repeat @R5+ → @R6+

R4L – 1 → R4L

until R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes specified by

R4L from locations starting at the address indicated by R5 to locations
starting at the address indicated by R6. After the transfer, the next
instruction is executed.

Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the
EEPMOV Instruction, for details.

40

Figure 2-10 Block Data Transfer Instruction Code

Notation:
op: Operation field

15 087

op
op

41

2.6 Basic Operational Timing

T1 state

Bus cycle

T2 state

Internal address bus

Internal read signal

Internal data bus
(read access)

Internal write signal

Read data

Address

Write data

Internal data bus
(write access)

SUB

ø or ø

CPU operation is synchronized by a system clock (ø) or a subclock (ø
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø

). For details on these

SUB

SUB

to
the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.

2.6.1 Access to On-Chip Memory (RAM, ROM)

Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2-11 shows the on-chip memory access cycle.

Figure 2-11 On-Chip Memory Access Cycle

42

2.6.2 Access to On-Chip Peripheral Modules

T1 state

Bus cycle

T

2

state

ø or ø

Internal address bus

Internal read signal

Internal data bus
(read access)

Internal write signal

Read data

Address

Write data

Internal data bus
(write access)

SUB

On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2-12 and 2-13 show the on-chip peripheral module access cycle.

Two-state access to on-chip peripheral modules

Figure 2-12 On-Chip Peripheral Module Access Cycle (2-State Access)

43

Three-state access to on-chip peripheral modules

T1 state

Bus cycle

Internal
address bus

Internal
read signal

Internal
data bus
(read access)

Internal
write signal

Read data

Address

Internal
data bus
(write access)

T2 state T3 state

Write data

SUB

ø or ø

Figure 2-13 On-Chip Peripheral Module Access Cycle (3-State Access)

44

2.7 CPU States

CPU state Reset state

Program

execution state

Program halt state

Exception-

handling state

Active

(high speed) mode

Active

(medium speed) mode

Subactive mode

Sleep (high-speed)

mode

Standby mode

Watch mode

Subsleep mode

Low-power

modes

The CPU executes successive program
instructions at high speed,
synchronized by the system clock

The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock

The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock

A state in which some
or all of the chip
functions are stopped
to conserve power

A transient state in which the CPU changes
the processing flow due to a reset or an interrupt

The CPU is initialized

Note: See section 5, Power-Down Modes, for details on the modes and their transitions.

Sleep (medium-speed)

mode

2.7.1 Overview

There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or medium­speed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2-14. Figure 2-15 shows the state transitions.

Figure 2-14 CPU Operation States

45

Figure 2-15 State Transitions

Reset state

Program halt state

Exception-handling state

Program execution state

Reset cleared

SLEEP instruction executed

Reset
occurs

Interrupt
source
occurs

Reset
occurs

Interrupt
source
occurs

Exception­handling
complete

Reset occurs

2.7.2 Program Execution State

In the program execution state the CPU executes program instructions in sequence.

There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.

2.7.3 Program Halt State

In the program halt state there are five modes: two sleep modes (high speed and medium speed),
standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on
these modes.

2.7.4 Exception-Handling State

The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by
an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.

For details on interrupt handling, see section 3.3, Interrupts.

46

2.8 Memory Map

H'0000

H'0029
H'002A

H'3FFF

H'F740

H'F75F

H'F780

H'FB7F

H'FF90

H'FFFF

Interrupt vector area

On-chip ROM

16 kbytes
(16384 bytes)

1024 bytesOn-chip RAM

Internal I/O registers

(112 bytes)

Not used

Not used

Not used

LCD RAM

(32 bytes)

2.8.1 Memory Map

The memory map of the H8/3862 and H8/3822 is shown in figure 2-16 (1), that of the H8/3863 and
H8/3823 in figure 2-16 (2), that of the H8/3864 and H8/3824 in figure 2-16 (3), that of the H8/3865
and H8/3825 in figure 2-16 (4), that of the H8/3866 and H8/3826 in figure 2-16 (5), and that of the
H8/3867 and H8/3827 in figure 2-16 (6).

Figure 2-16 (1) H8/3862 and H8/3822 Memory Map

47

H'0000

H'0029
H'002A

H'5FFF

H'F740

H'F75F

H'F780

H'FB7F

H'FF90

H'FFFF

Interrupt vector area

On-chip ROM

24 kbytes
(24576 bytes)

1024 bytesOn-chip RAM

Internal I/O registers

(112 bytes)

Not used

Not used

Not used

LCD RAM
(32 bytes)

Figure 2-16 (2) H8/3863 and H8/3823 Memory Map

48

H'0000

H'0029
H'002A

H'7FFF

H'F740

H'F75F

H'F780

H'FF7F

H'FF90

H'FFFF

Interrupt vector area

On-chip ROM

32 kbytes
(32768 bytes)

2048 bytesOn-chip RAM

Internal I/O registers

(112 bytes)

Not used

Not used

Not used

LCD RAM

(32 bytes)

Figure 2-16 (3) H8/3864 and H8/3824 Memory Map

49

H'0000

H'0029
H'002A

H'9FFF

H'F740

H'F75F

H'F780

H'FF7F

H'FF90

H'FFFF

Interrupt

vector area

On-chip ROM

40 kbytes
(40960 bytes)

2048 bytes

On-chip RAM

Internal I/O registers

(112 bytes)

Not used

Not used

Not used

LCD RAM

(32 bytes)

Figure 2-16 (4) H8/3865 and H8/3825 Memory Map

50

H'0000

H'0029
H'002A

H'BFFF

H'F740

H'F75F

H'F780

H'FF7F

H'FF90

H'FFFF

Interrupt vector area

On-chip ROM

48 kbytes
(49152 bytes)

2048 bytes

On-chip RAM

Not used

Internal I/O registers

(112 bytes)

Not used

Not used

LCD RAM

(32 bytes)

Figure 2-16 (5) H8/3866 and H8/3826 Memory Map

51

H'0000

H'0029
H'002A

H'EDFF

H'F740

H'F75F

H'F780

H'FF7F

H'FF90

H'FFFF

Interrupt vector area

On-chip ROM

60 kbytes
(60928 bytes)

2048 bytes

On-chip RAM

Internal I/O registers

(112 bytes)

Not used

Not used

Not used

LCD RAM

(32 bytes)

Figure 2-16 (6) H8/3867 and H8/3827 Memory Map

52

2.9 Application Notes

2.9.1 Notes on Data Access

1. Access to Empty Areas:

The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers,
and ROM areas available to the user. If these empty areas are mistakenly accessed by an
application program, the following results will occur.

Data transfer from CPU to empty area:

The transferred data will be lost. This action may also cause the CPU to misoperate.

Data transfer from empty area to CPU:

Unpredictable data is transferred.

2. Access to Internal I/O Registers:

Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.

Word access from CPU to I/O register area:

Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.

Word access from I/O register to CPU:

Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.

Byte size instructions should therefore be used when transferring data to or from I/O registers other
than the on-chip ROM and RAM areas. Figure 2-17 shows the data size and number of states in
which on-chip peripheral modules can be accessed.

53

Interrupt vector area

(42 bytes)

On-chip ROM

32kbytes

On-chip RAM

Not used

Not used

Not used

LCD RAM
(32 bytes)

Internal I/O registers

(112 bytes)

Access

Word Byte

2

———

———

2

———

2

×

3

×

2

×

3

×

2

×

2

States

2048 bytes

H'FFA8 to H'FFAF

H'0000

H'0029
H'002A

H'7FFF

H'F740

H'F75F

H'F780

H'FF7F*

2

H'FF90

H'FFFF

Notes:

1.

2.

*

1

The example of the H8/3864 and H8/3824 is shown here.
This address is H'3FFF in the H8/3862 and H8/3822 (16-kbyte on-chip ROM), H'5FFF in
the H8/3863 and H8/3823 (24-kbyte on-chip ROM), H'9FFF in the H8/3865 and H8/3825
(40-kbyte on-chip ROM), H'BFFF in the H8/3866 and H8/3826 (48-kbyte on-chip ROM),
and H'EDFF in the H8/3867 and H8/3827 (60-kbyte on-chip ROM).
This address is H'FB7F in the H8/3862, H8/3822, H8/3863, and H8/3823 (1024 bytes of
on-chip RAM).

H'FF98 to H'FF9F

Figure 2-17 Data Size and Number of States for Access to and from

On-Chip Peripheral Modules

54

2.9.2 Notes on Bit Manipulation

Read

Write

Count clock Timer counter

Timer load register

Reload

Internal bus

The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then
write the data byte again. Special care is required when using these instructions in cases where two
registers are assigned to the same address, in the case of registers that include write-only bits, and
when the instruction accesses an I/O port.

Order of Operation Operation

1 Read Read byte data at the designated address
2 Modify Modify a designated bit in the read data
3 Write Write the altered byte data to the designated address

1. Bit manipulation in two registers assigned to the same address

Example 1: timer load register and timer counter

Figure 2-18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.

Order of Operation Operation

1 Read Timer counter data is read (one byte)
2 Modify The CPU modifies (sets or resets) the bit designated in the instruction
3 Write The altered byte data is written to the timer load register

The timer counter is counting, so the value read is not necessarily the same as the value in the timer
load register. As a result, bits other than the intended bit in the timer load register may be modified
to the timer counter value.

Figure 2-18 Timer Configuration Example

55

Example 2: BSET instruction executed designating port 3

P37and P36are designated as input pins, with a low-level signal input at P37and a high-level signal
at P36. The remaining pins, P35to P30, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P30to high-level output.

[A: Prior to executing BSET]

P3

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low

level level level level level level level level
PCR3 00111111
PDR3 10000000

[B: BSET instruction executed]

BSET #0 , @PDR3

The BSET instruction is executed designating port 3.

[C: After executing BSET]

P3

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low High

level level level level level level level level
PCR3 00111111
PDR3 01000001

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

[D: Explanation of how BSET operates]

When the BSET instruction is executed, first the CPU reads port 3.

Since P37and P36are input pins, the CPU reads the pin states (low-level and high-level input).
P35to P30are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.

Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.

56

As a result of this operation, bit 0 in PDR3 becomes 1, and P30outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.

To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.

[A: Prior to executing BSET]

MOV. B #80, R0L
MOV. B R0L, @RAM0

The PDR3 value (H'80) is written to a work area in memory
(RAM0) as well as to PDR3.

MOV. B R0L, @PDR3

P3

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low

level level level level level level level level
PCR3 00111111
PDR3 10000000
RAM0 10000000

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

[B: BSET instruction executed]

BSET #0 , @RAM0

The BSET instruction is executed designating the PDR3
work area (RAM0).

[C: After executing BSET]

MOV. B @RAM0, R0L

The work area (RAM0) value is written to PDR3.

MOV. B R0L, @PDR3

P3

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low High

level level level level level level level level
PCR3 00111111
PDR3 10000001
RAM0 10000001

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

57

2. Bit manipulation in a register containing a write-only bit

Example 3: BCLR instruction executed designating port 3 control register PCR3

As in the examples above, P37and P36are input pins, with a low-level signal input at P37and a
high-level signal at P36. The remaining pins, P35to P30, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P30to an input port. It is
assumed that a high-level signal will be input to this input pin.

[A: Prior to executing BCLR]

P3

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low

level level level level level level level level
PCR3 00111111
PDR3 10000000

[B: BCLR instruction executed]

BCLR #0 , @PCR3

The BCLR instruction is executed designating PCR3.

[C: After executing BCLR]

P3

Input/output Output Output Output Output Output Output Output Input
Pin state Low High Low Low Low Low Low High

level level level level level level level level
PCR3 11111110
PDR3 10000000

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

[D: Explanation of how BCLR operates]

When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.

Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.

As a result of this operation, bit 0 in PCR3 becomes 0, making P30an input port. However, bits 7
and 6 in PCR3 change to 1, so that P37and P36change from input pins to output pins.

To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR3.

58

[A: Prior to executing BCLR]

MOV. B #3F, R0L
MOV. B R0L, @RAM0

The PCR3 value (H'3F) is written to a work area in memory
(RAM0) as well as to PCR3.

MOV. B R0L, @PCR3

P3

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low

level level level level level level level level
PCR3 00111111
PDR3 10000000
RAM0 00111111

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

[B: BCLR instruction executed]

BCLR #0 , @RAM0

The BCLR instruction is executed designating the PCR3
work area (RAM0).

[C: After executing BCLR]

MOV. B @RAM0, R0L

The work area (RAM0) value is written to PCR3.

MOV. B R0L, @PCR3

P3

Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low High

level level level level level level level level
PCR3 00111110
PDR3 10000000
RAM0 00111110

P3

7

P3

6

P3

5

P3

4

P3

3

P3

2

P3

1

0

59

Table 2-12 lists the pairs of registers that share identical addresses. Table 2-13 lists the registers that
contain write-only bits.

Table 2-12 Registers with Shared Addresses

Register Name Abbreviation Address

Timer counter and timer load register C TCC/TLC H'FFB5
Port data register 1* PDR1 H'FFD4
Port data register 3* PDR3 H'FFD6
Port data register 4* PDR4 H'FFD7
Port data register 5* PDR5 H'FFD8
Port data register 6* PDR6 H'FFD9
Port data register 7* PDR7 H'FFDA
Port data register 8* PDR8 H'FFDB
Port data register A* PDRA H'FFDD
Note: * Port data registers have the same addresses as input pins.

Table 2-13 Registers with Write-Only Bits

Register Name Abbreviation Address

Port control register 1 PCR1 H'FFE4
Port control register 3 PCR3 H'FFE6
Port control register 4 PCR4 H'FFE7
Port control register 5 PCR5 H'FFE8
Port control register 6 PCR6 H'FFE9
Port control register 7 PCR7 H'FFEA
Port control register 8 PCR8 H'FFEB
Port control register A PCRA H'FFED
Timer control register F TCRF H'FFB6
PWM control register PWCR H'FFD0
PWM data register U PWDRU H'FFD1
PWM data register L PWDRL H'FFD2

60

2.9.3 Notes on Use of the EEPMOV Instruction

H'FFFF

Not allowed

←

R6

←

R6 + R4L

R5

→

R5 + R4L

→

←

R6

←

R6 + R4L

R5

→

R5 + R4L

→

• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes

specified by R4L from the address specified by R5 to the address specified by R6.

• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not

exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.

61

Section 3 Exception Handling

3.1 Overview

Exception handling is performed in the H8/3864 Series when a reset or interrupt occurs. Table 3-1
shows the priorities of these two types of exception handling.

Table 3-1 Exception Handling Types and Priorities

Priority Exception Source Time of Start of Exception Handling

High Reset Exception handling starts as soon as the reset state is cleared

Interrupt When an interrupt is requested, exception handling starts

after execution of the present instruction or the exception

Low handling in progress is completed

3.2 Reset

3.2.1 Overview

A reset is the highest-priority exception. The internal state of the CPU and the registers of the on­chip peripheral modules are initialized.

3.2.2 Reset Sequence

As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.

To make sure the chip is reset properly, observe the following precautions.

• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.

• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.

Reset exception handling takes place as follows.

• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I

bit of the condition code register (CCR) set to 1.

• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after

which the program starts executing from the address indicated in PC.

63

When system power is turned on or off, the RES pin should be held low.

Vector fetch

ø

Internal
address bus

Internal read
signal

Internal write
signal

Internal data
bus (16-bit)

RES

Internal
processing

Program initial
instruction prefetch

(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program

(2) (3)

(2)

(1)

Reset cleared

Figure 3-1 shows the reset sequence starting from RES input.

Figure 3-1 Reset Sequence

64

3.2.3 Interrupt Immediately after Reset

After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction should
initialize the stack pointer (e.g. MOV.W #xx: 16, SP).

3.3 Interrupts

3.3.1 Overview

The interrupt sources include 13 external interrupts (IRQ4to IRQ0, WKP7to WKP0) and 23 internal
interrupts from on-chip peripheral modules. Table 3-2 shows the interrupt sources, their priorities,
and their vector addresses. When more than one interrupt is requested, the interrupt with the highest
priority is processed.

The interrupts have the following features:

• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,

interrupt request flags can be set but the interrupts are not accepted.

• IRQ4to IRQ0and WKP7to WKP0can be set to either rising edge sensing or falling edge

sensing.

65

Table 3-2 Interrupt Sources and Their Priorities

Interrupt Source Interrupt Vector Number Vector Address Priority

RES Reset 0 H'0000 to H'0001 High
IRQ

0

IRQ

1

IRQ

2

IRQ

3

IRQ

4

WKP

0

WKP

1

WKP

2

WKP

3

WKP

4

WKP

5

WKP

6

WKP

7

Timer A Timer A overflow 11 H'0016 to H'0017
Asynchronous Asynchronous counter 12 H'0018 to H'0019

counter overflow
Timer C Timer C overflow or 13 H'001A to H'001B

Timer FL Timer FL compare match 14 H'001C to H'001D

Timer FH Timer FH compare match 15 H'001E to H'001F

Timer G Timer G input capture 16 H'0020 to H'0021

SCI3-1 SCI3-1 transmit end 17 H'0022 to H'0023

SCI3-2 SCI3-2 transmit end 18 H'0024 to H'0025

A/D A/D conversion end 19 H'0026 to H'0027
(SLEEP instruction Direct transfer 20 H'0028 to H'0029 Low

executed)
Note: Vector addresses H'0002 to H'0007 and H'0014 to H'0015 are reserved and cannot be used.

IRQ

0

IRQ

1

IRQ

2

IRQ

3

IRQ

4

WKP

0

WKP

1

WKP

2

WKP

3

WKP

4

WKP

5

WKP

6

WKP

7

underflow

Timer FL overflow

Timer FH overflow

Timer G overflow

SCI3-1 transmit data empty
SCI3-1 receive data full
SCI3-1 overrrun error
SCI3-1 framing error
SCI3-1 parity error

SCI3-2 transmit data empty
SCI3-2 receive data full
SCI3-2 overrun error
SCI3-2 framing error
SCI3-2 parity error

4 H'0008 to H'0009
5 H'000A to H'000B
6 H'000C to H'000D
7 H'000E to H'000F
8 H'0010 to H'0011
9 H'0012 to H'0013

66

3.3.2 Interrupt Control Registers

Bit

Initial value
Read/Write

7

—

1

—

6

—

1

—

5

—

1

—

4

IEG4

0

R/W

3

IEG3

0

R/W

0

IEG0

0

R/W

2

IEG2

0

R/W

1

IEG1

0

R/W

Table 3-3 lists the registers that control interrupts.

Table 3-3 Interrupt Control Registers

Name Abbreviation R/W Initial Value Address

IRQ edge select register IEGR R/W H'E0 H'FFF2
Interrupt enable register 1 IENR1 R/W H'00 H'FFF3
Interrupt enable register 2 IENR2 R/W H'00 H'FFF4
Interrupt request register 1 IRR1 R/W* H'20 H'FFF6
Interrupt request register 2 IRR2 R/W* H'00 H'FFF7
Wakeup interrupt request register IWPR R/W* H'00 H'FFF9
Wakeup edge select register WEGR R/W H'00 H'FF90
Note: * Write is enabled only for writing of 0 to clear a flag.

1. IRQ edge select register (IEGR)

IEGR is an 8-bit read/write register used to designate whether pins IRQ4to IRQ0are set to rising
edge sensing or falling edge sensing.

Bits 7 to 5: Reserved bits

Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.

Bit 4: IRQ4edge select (IEG4)

Bit 4 selects the input sensing of the IRQ4pin and ADTRG pin.

Bit 4
IEG4 Description

0 Falling edge of IRQ4and ADTRG pin input is detected (initial value)
1 Rising edge of IRQ4and ADTRG pin input is detected

67

Bit 3: IRQ3edge select (IEG3)

Bit 3 selects the input sensing of the IRQ3pin and TMIF pin.

Bit 3
IEG3 Description

0 Falling edge of IRQ3and TMIF pin input is detected (initial value)
1 Rising edge of IRQ3and TMIF pin input is detected

Bit 2: IRQ2edge select (IEG2)

Bit 2 selects the input sensing of pin IRQ2.

Bit 2
IEG2 Description

0 Falling edge of IRQ2pin input is detected (initial value)
1 Rising edge of IRQ2pin input is detected

Bit 1: IRQ1edge select (IEG1)

Bit 3 selects the input sensing of the IRQ1pin and TMIC pin.

Bit 1
IEG1 Description

0 Falling edge of IRQ1and TMIC pin input is detected (initial value)
1 Rising edge of IRQ1and TMIC pin input is detected

Bit 0: IRQ0edge select (IEG0)

Bit 0 selects the input sensing of pin IRQ0.

Bit 0
IEG0 Description

0 Falling edge of IRQ0pin input is detected (initial value)
1 Rising edge of IRQ0pin input is detected

68

2. Interrupt enable register 1 (IENR1)

Bit

Initial value
Read/Write

7

IENTA

0

R/W

6

—

0

R/W

5

IENWP

0

R/W

4

IEN4

0

R/W

3

IEN3

0

R/W

0

IEN0

0

R/W

2

IEN2

0

R/W

1

IEN1

0

R/W

IENR1 is an 8-bit read/write register that enables or disables interrupt requests.

Bit 7: Timer A interrupt enable (IENTA)

Bit 7 enables or disables timer A overflow interrupt requests.

Bit 7
IENTA Description

0 Disables timer A interrupt requests (initial value)
1 Enables timer A interrupt requests

Bit 6: Reserved bit

Bit 6 is a readable/writable reserved bit. It is initialized to 0 by a reset.

Bit 5: Wakeup interrupt enable (IENWP)

Bit 5 enables or disables WKP7to WKP0interrupt requests.

Bit 5
IENWP Description

0 Disables WKP7to WKP0interrupt requests (initial value)
1 Enables WKP7to WKP0interrupt requests

Bits 4 to 0: IRQ4to IRQ0interrupt enable (IEN4 to IEN0)

Bits 4 to 0 enable or disable IRQ4to IRQ0interrupt requests.

Bit n
IENn Description

0 Disables interrupt requests from pin IRQn (initial value)
1 Enables interrupt requests from pin IRQn

69

(n = 4 to 0)

3. Interrupt enable register 2 (IENR2)

Bit

Initial value
Read/Write

7

IENDT

0

R/W

6

IENAD

0

R/W

5

—

0

R/W

4

IENTG

0

R/W

3

IENTFH

0

R/W

0

IENEC

0

R/W

2

IENTFL

0

R/W

1

IENTC

0

R/W

IENR2 is an 8-bit read/write register that enables or disables interrupt requests.

Bit 7: Direct transfer interrupt enable (IENDT)

Bit 7 enables or disables direct transfer interrupt requests.

Bit 7
IENDT Description

0 Disables direct transfer interrupt requests (initial value)
1 Enables direct transfer interrupt requests

Bit 6: A/D converter interrupt enable (IENAD)

Bit 6 enables or disables A/D converter interrupt requests.

Bit 6
IENAD Description

0 Disables A/D converter interrupt requests (initial value)
1 Enables A/D converter interrupt requests

Bit 5: Reserved bit

Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.

Bit 4: Timer G interrupt enable (IENTG)

Bit 4 enables or disables timer G input capture or overflow interrupt requests.

Bit 4
IENTG Description

0 Disables timer G interrupt requests (initial value)
1 Enables timer G interrupt requests

70

Bit 3: Timer FH interrupt enable (IENTFH)

Bit 3 enables or disables timer FH compare match and overflow interrupt requests.

Bit 3
IENTFH Description

0 Disables timer FH interrupt requests (initial value)
1 Enables timer FH interrupt requests

Bit 2: Timer FL interrupt enable (IENTFL)

Bit 2 enables or disables timer FL compare match and overflow interrupt requests.

Bit 2
IENTFL Description

0 Disables timer FL interrupt requests (initial value)
1 Enables timer FL interrupt requests

Bit 1: Timer C interrupt enable (IENTC)

Bit 1 enables or disables timer C overflow and underflow interrupt requests.

Bit 1
IENTC Description

0 Disables timer C interrupt requests (initial value)
1 Enables timer C interrupt requests

Bit 0: Asynchronous event counter interrupt enable (IENEC)

Bit 0 enables or disables asynchronous event counter interrupt requests.

Bit 0
IENEC Description

0 Disables asynchronous event counter interrupt requests (initial value)
1 Enables asynchronous event counter interrupt requests

For details of SCI3-1 and SCI3-2 interrupt control, see 6. Serial control register 3 (SCR3) in section

10.4.2.

71

4. Interrupt request register 1 (IRR1)

Bit

Initial value
Read/Write

7

IRRTA

0

R/W

6

—

0

R/W

5

—

1

—

4

IRRI4

0

R/W

3

IRRI3

0

R/W

0

IRRI0

0

R/W

2

IRRI2

0

R/W

1

IRRI1

0

R/W

** *****

Note: * Only a write of 0 for flag clearing is possible

IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A or
IRQ4to IRQ0interrupt is requested. The flags are not cleared automatically when an interrupt is
accepted. It is necessary to write 0 to clear each flag.

Bit 7: Timer A interrupt request flag (IRRTA)

Bit 7
IRRTA Description

0 Clearing conditions: (initial value)

When IRRTA = 1, it is cleared by writing 0

1 Setting conditions:

When the timer A counter value overflows from H'FF to H'00

Bit 6: Reserved bit

Bit 6 is a readable/writable reserved bit. It is initialized to 0 by a reset.

Bit 5: Reserved bit

Bit 5 is reserved; it is always read as 1 and cannot be modified.

Bits 4 to 0: IRQ4to IRQ0interrupt request flags (IRRI4 to IRRI0)

Bit n
IRRIn Description

0 Clearing conditions: (initial value)

When IRRIn = 1, it is cleared by writing 0

1 Setting conditions:

When pin IRQn is designated for interrupt input and the designated signal edge is input

(n = 4 to 0)

72

5. Interrupt request register 2 (IRR2)

Bit

Initial value
Read/Write

7

IRRDT

0

R/W

6

IRRAD

0

R/W

5

—

0

R/W

4

IRRTG

0

R/W

3

IRRTFH

0

R/W

0

IRREC

0

R/W

2

IRRTFL

0

R/W

1

IRRTC

0

R/W

** *****

Note: * Only a write of 0 for flag clearing is possible

IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct transfer,
A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The flags are not
cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag.

Bit 7: Direct transfer interrupt request flag (IRRDT)

Bit 7
IRRDT Description

0 Clearing conditions: (initial value)

When IRRDT = 1, it is cleared by writing 0

1 Setting conditions:

When a direct transfer is made by executing a SLEEP instruction while DTON = 1 in
SYSCR2

Bit 6: A/D converter interrupt request flag (IRRAD)

Bit 6
IRRAD Description

0 Clearing conditions: (initial value)

When IRRAD = 1, it is cleared by writing 0

1 Setting conditions:

When A/D conversion is completed and ADSF is cleared to 0 in ADSR

Bit 5: Reserved bit

Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.

73

Bit 4: Timer G interrupt request flag (IRRTG)

Bit 4
IRRTG Description

0 Clearing conditions: (initial value)

When IRRTG = 1, it is cleared by writing 0

1 Setting conditions:

When the TMIG pin is designated for TMIG input and the designated signal edge is
input, or when TCG overflows while OVIE is set to 1 in TMG

Bit 3: Timer FH interrupt request flag (IRRTFH)

Bit 3
IRRTFH Description

0 Clearing conditions: (initial value)

When IRRTFH = 1, it is cleared by writing 0

1 Setting conditions:

When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH) and
OCRF (OCRFL, OCRFH) match in 16-bit timer mode

Bit 2: Timer FL interrupt request flag (IRRTFL)

Bit 2
IRRTFL Description

0 Clearing conditions: (initial value)

When IRRTFL= 1, it is cleared by writing 0

1 Setting conditions:

When TCFL and OCRFL match in 8-bit timer mode

Bit 1: Timer C interrupt request flag (IRRTC)

Bit 1
IRRTC Description

0 Clearing conditions: (initial value)

When IRRTC= 1, it is cleared by writing 0

1 Setting conditions:

When the timer C counter value overflows (from H'FF to H'00) or underflows
(from H'00 to H'FF)

74

Bit 0: Asynchronous event counter interrupt request flag (IRREC)

Bit

Initial value
Read/Write

7

IWPF7

0

R/W

6

IWPF6

0

R/W

5

IWPF5

0

R/W

4

IWPF4

0

R/W

3

IWPF3

0

R/W

0

IWPF0

0

R/W

2

IWPF2

0

R/W

1

IWPF1

0

R/W

** ******

Note: * Only a write of 0 for flag clearing is possible

Bit 0
IRREC Description

0 Clearing conditions: (initial value)

When IRREC = 1, it is cleared by writing 0

1 Setting conditions:

When ECH overflows in 16-bit counter mode, or ECH or ECL overflows
in 8-bit counter mode

6. Wakeup Interrupt Request Register (IWPR)

IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins

WKP7to WKP0is designated for wakeup input and a rising or falling edge is input at that pin, the

corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the corresponding
interrupt is accepted. Flags must be cleared by writing 0.

Bits 7 to 0: Wakeup interrupt request flags (IWPF7 to IWPF0)

Bit n
IWPFn Description

0 Clearing conditions: (initial value)

When IWPFn= 1, it is cleared by writing 0

1 Setting conditions:

When pin WKPnis designated for wakeup input and a rising or falling edge is input
at that pin

(n = 7 to 0)

75

7. Wakeup Edge Select Register (WEGR)

Bit

Initial value
Read/Write

7

WKEGS7

0

R/W

6

WKEGS6

0

R/W

5

WKEGS5

0

R/W

4

WKEGS4

0

R/W

3

WKEGS3

0

R/W

0

WKEGS0

0

R/W

2

WKEGS2

0

R/W

1

WKEGS1

0

R/W

WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.

WEGR is initialized to H'00 by a reset.

Bit n: WKPn edge select (WKEGSn)

Bit n selects WKPn pin input sensing.

Bit n
WKEGSn Description

0 WKPn pin falling edge detected (initial value)
1 WKPn pin rising edge detected

(n = 7 to 0)

3.3.3 External Interrupts

There are 13 external interrupts: IRQ4to IRQ0and WKP7to WKP0.

1. Interrupts WKP7to WKP

0

Interrupts WKP7to WKP0are requested by either rising or falling edge input to pins WKP7to

WKP0. When these pins are designated as pins WKP7to WKP0in port mode register 5 and a rising

or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in IENR1.
These interrupts can all be masked by setting the I bit to 1 in CCR.

When WKP7to WKP0interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP7to WKP0. All eight interrupt sources have the same vector
number, so the interrupt-handling routine must discriminate the interrupt source.

76

2. Interrupts IRQ4to IRQ

0

Interrupts IRQ4to IRQ0are requested by input signals to pins IRQ4to IRQ0. These interrupts are
detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4
to IEG0 in IEGR.

When these pins are designated as pins IRQ4to IRQ0in port mode register 3 and 1 and the
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN0
to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.

When IRQ4to IRQ0interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 8 to 4 are assigned to interrupts IRQ4to IRQ0. The order of priority is from IRQ0(high) to
IRQ4(low). Table 3-2 gives details.

3.3.4 Internal Interrupts

There are 23 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When internal
interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 11 are
assigned to these interrupts. Table 3-2 shows the order of priority of interrupts from on-chip
peripheral modules.

77

3.3.5 Interrupt Operations

Interrupt controller

Priority decision logic

Interrupt
request

CCR (CPU)I

External or
internal
interrupts

External
interrupts or
internal
interrupt
enable
signals

Interrupts are controlled by an interrupt controller. Figure 3-2 shows a block diagram of the
interrupt controller. Figure 3-3 shows the flow up to interrupt acceptance.

Figure 3-2 Block Diagram of Interrupt Controller

Interrupt operation is described as follows.

• When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt

request signal is sent to the interrupt controller.

• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.

• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects

the interrupt request with the highest priority and holds the others pending. (Refer to
table 3-2 for a list of interrupt priorities.)

• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is

accepted; if the I bit is 1, the interrupt request is held pending.

78

• If the interrupt is accepted, after processing of the current instruction is completed, both PC and

CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3-4. The
PC value pushed onto the stack is the address of the first instruction to be executed upon return
from interrupt handling.

• The I bit of CCR is set to 1, masking further interrupts.

• The vector address corresponding to the accepted interrupt is generated, and the interrupt

handling routine located at the address indicated by the contents of the vector address is
executed.

Notes:

1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits

in an interrupt request register, always do so while interrupts are masked (I = 1).

2. If the above clear operations are performed while I = 0, and as a result a conflict arises between

the clear instruction and an interrupt request, exception processing for the interrupt will be
executed after the clear instruction has been executed.

79

PC contents saved

CCR contents saved

I ← 1

I = 0

Program execution state

No

Yes

Yes

No

Notation:
PC:
CCR:
I:

Program counter
Condition code register
I bit of CCR

IEN0 = 1

No

Yes

IENDT = 1

No

Yes

IRRDT = 1

No

Yes

Branch to interrupt

handling routine

IRRI0 = 1

No

Yes

IEN1 = 1

No

Yes

IRRI1 = 1

No

Yes

IEN2 = 1

No

Yes

IRRI2 = 1

Figure 3-3 Flow up to Interrupt Acceptance

80

Figure 3-4 Stack State after Completion of Interrupt Exception Handling

PC and CCR

saved to stack

SP (R7)

SP – 1

SP – 2

SP – 3

SP – 4

Stack area

SP + 4

SP + 3

SP + 2

SP + 1

SP (R7)

Even address

Prior to start of interrupt

exception handling

After completion of interrupt

exception handling

Notation:
PC

H

:

PC

L

:
CCR:
SP:

Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer

Notes:

CCR

CCR

PC

H

PC

L

1.

2.

*

PC shows the address of the first instruction to be executed upon

return from the interrupt handling routine.
Register contents must always be saved and restored by word access,
starting from an even-numbered address.
Ignored on return.

*

Figure 3-5 shows a typical interrupt sequence.

81

Vector fetch

ø

Internal

address bus

Internal read

signal

Internal write

signal

(2)

Internal data bus

(16 bits)

Interrupt

request signal

(9)

(1)

Internal

processing

Prefetch instruction of

interrupt-handling routine

(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)

(2)(4) Instruction code (not executed)

(3) Instruction prefetch address (Instruction is not executed.)

(5) SP – 2

(6) SP – 4

(7) CCR

(8) Vector address

(9) Starting address of interrupt-handling routine (contents of vector)

(10) First instruction of interrupt-handling routine

(3) (9)(8)(6)(5)

(4) (1) (7) (10)

Stack access

Internal

processing

Instruction

prefetch

Interrupt level

decision and wait for

end of instruction

Interrupt is

accepted

Figure 3-5 Interrupt Sequence

82

3.3.6 Interrupt Response Time

Table 3-4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.

Table 3-4 Interrupt Wait States

Item States Total

Waiting time for completion of executing instruction* 1 to 13 15 to 27
Saving of PC and CCR to stack 4
Vector fetch 2
Instruction fetch 4
Internal processing 4
Note: * Not including EEPMOV instruction.

83

3.4 Application Notes

PC
PC

R1L

PC

SP

SP

SP

H'FEFC
H'FEFD

H'FEFF

→

→

→

H
L

L

MOV. B R1L, @–R7

SP set to H'FEFF Stack accessed beyond SP

BSR instruction

Contents of PC are lost

H

Notation:
PC

H

:

PC

L

:
R1L:
SP:

Upper byte of program counter
Lower byte of program counter
General register R1L
Stack pointer

3.4.1 Notes on Stack Area Use

When word data is accessed in the H8/3864 Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.

Setting an odd address in SP may cause a program to crash. An example is shown in figure 3-6.

Figure 3-6 Operation when Odd Address is Set in SP

When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.

84

3.4.2 Notes on Rewriting Port Mode Registers

When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.

When an external interrupt pin function is switched by rewriting the port mode register that controls
pins IRQ4to IRQ0, WKP7to WKP0, the interrupt request flag may be set to 1 at the time the pin
function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt
request flag to 0 after switching pin functions. Table 3-5 shows the conditions under which
interrupt request flags are set to 1 in this way.

Table 3-5 Conditions under which Interrupt Request Flag is Set to 1

Interrupt Request
Flags Set to 1 Conditions

IRR1 IRRI4 When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ

bit IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4is low and IEGR

bit IEG4 = 1.

IRRI3 When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ

bit IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3is low and IEGR

bit IEG3 = 1.

IRRI2 When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ

bit IEG2 = 0.
When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2is low and IEGR

bit IEG2 = 1.

IRRI1 When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ

bit IEG1 = 0.
When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1is low and IEGR

bit IEG1 = 1.

IRRI0 When PMR3 bit IRQ0 is changed from 0 to 1 while pin IRQ

bit IEG0 = 0.
When PMR3 bit IRQ0 is changed from 1 to 0 while pin IRQ0is low and IEGR

bit IEG0 = 1.

IWPR IWPF7 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7is low.

IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6is low.
IWPF5 When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5is low.
IWPF4 When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4is low.
IWPF3 When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3is low.
IWPF2 When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2is low.
IWPF1 When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1is low.
IWPF0 When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0is low.

is low and IEGR

4

is low and IEGR

3

is low and IEGR

2

is low and IEGR

1

is low and IEGR

0

85

Figure 3-7 shows the procedure for setting a bit in a port mode register and clearing the interrupt

CCR I bit 1

Set port mode register bit

Execute NOP instruction

Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)

After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0

Interrupt mask cleared

Clear interrupt request flag to 0

←

CCR I bit 0

←

request flag.

When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.

An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3-5 do not occur.

Figure 3-7 Port Mode Register Setting and Interrupt Request Flag

Clearing Procedure

86

Section 4 Clock Pulse Generators

System clock

oscillator

System clock

divider (1/2)

Subclock
oscillator

Subclock

divider

(1/2, 1/4, 1/8)

System

clock

divider

System clock pulse generator

Subclock pulse generator

Prescaler S

(13 bits)

Prescaler W

(5 bits)

OSC
OSC

1
2

X
X

1
2

ø

OSC

(f )

OSC

ø

W

ø

W

(f )

W

ø /2

OSC

ø /2

W

ø /8

W

ø

SUB

ø/2
to
ø/8192

ø /2

W

ø /4

W

ø /8
to
ø /128

W

W

ø

ø

OSC

/128

ø

OSC

/64

ø

OSC

/32

ø

OSC

/16

ø /4

W

4.1 Overview

Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system
clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of
a system clock oscillator and system clock dividers. The subclock pulse generator consists of a
subclock oscillator circuit and a subclock divider.

4.1.1 Block Diagram

Figure 4-1 shows a block diagram of the clock pulse generators.

Figure 4-1 Block Diagram of Clock Pulse Generators

4.1.2 System Clock and Subclock

The basic clock signals that drive the CPU and on-chip peripheral modules are ø and ø
the clock signals have names: ø is the system clock, ø

is the subclock, ø

SUB

is the oscillator

OSC

SUB

. Four of

clock, and øWis the watch clock.

The clock signals available for use by peripheral modules are ø/2, ø/4, ø/8, ø/16, ø/32, ø/64, ø/128,
ø/256, ø/512, ø/1024, ø/2048, ø/4096, ø/8192, øW, øW/2, øW/4, øW/8, øW/16, øW/32, øW/64, and
øW/128. The clock requirements differ from one module to another.

87

4.2 System Clock Generator

C

S

C

0

R

S

OSC

1

OSC

2

L

S

1

2

C

1

C

2

OSC

OSC

R = 1 M ±20%

f

Ω

R

f

Frequency

1.0 MHz

4.0 MHz

Crystal
oscillator

NDK
NDK

C1, C2
Recommendation
value

27 pF ±10%
12 pF ±20%

Products Name
NR-18 (NDK45)
NR-18 (NDK03)

Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.

1. Connecting a crystal oscillator

Figure 4-2 shows a typical method of connecting a crystal oscillator.

Figure 4-2 Typical Connection to Crystal Oscillator

Figure 4-3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
characteristics given in table 4-1 should be used.

Figure 4-3 Equivalent Circuit of Crystal Oscillator

Table 4-1 Crystal Oscillator Parameters

Frequency (MHz) 1 4.193
RSmax (Ω) 40 100
C0(pF) 3.5 pF max 16 pF

88

2. Connecting a ceramic oscillator

OSC

OSC

C

1

C

2

Signal A Signal B

2

1

To be avoided

Figure 4-4 shows a typical method of connecting a ceramic oscillator.

OSC

OSC

C

1

1

R

f

2

C

2

R = 1 M ±20%

Frequency

1.0 MHz

4.0 MHz

Ω

f

C1, C2
Ceramic
oscillator

Murata
Murata

Recommendation

value

150 pF ±10%

30 pF ±10%

Products Name
CSB 1000J
CSA 4.00MG

Figure 4-4 Typical Connection to Ceramic Oscillator

3. Notes on board design

When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to
the following points.

Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4-5.)

The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1and OSC2.

Figure 4-5 Board Design of Oscillator Circuit

89