Page 1
Hitachi Single-Chip Microcomputer
H8/3664 Series
H8/3664
HD6433664
H8/3663
HD6433663
H8/3662
HD6433662
H8/3661
ADE-602-202A
HD6433661
H8/3660
HD6433660
H8/3664F-ZTAT™
HD64F3664
Hardware Manual
Rev. 2.0
9/25/00
Hitachi, Ltd.
Page 2
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright, trademark, or other intellectual property rights for information contained in
this document. Hitachi bears no responsibility for problems that may arise with third party’s
rights, including intellectual property rights, in connection with use of the information
contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you
have received the latest product standards or specifications before final design, purchase or
use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.
However, contact Hitachi’s sales office before using the product in an application that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear
power, combustion control, transportation, traffic, safety equipment or medical equipment for
life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally foreseeable failure rates or failure modes in semiconductor devices and
employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi
product does not cause bodily injury, fire or other consequential damage due to operation of
the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document
without written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi
semiconductor products.
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Preface
The H8/3664 Series of single-chip microcomputers has the high-speed H8/300H CPU at its core,
with many necessary peripheral functions on-chip. The H8/300H CPU instruction set is
compatible with the H8/300 CPU.
The H8/3664 Series includes such peripheral functions as four timers, an I2C bus interface, a serial
communication interface, and a 10-bit A/D converter, so that they can be used as an embedded
microcomputer for a sophisticated control system.
This manual describes the hardware of the H8/3664 Series. For details on the H8/3664 Series
instruction set, refer to the H8/300H Series Programming Manual.
Notes:
When using an on-chip emulator (E10T) for H8/3664 program development and debugging, the
following restrictions must be noted.
1. The NMI pin is reserved for the E10T, and cannot be used.
2. Pins P85, P86, and P87 cannot be used. (In order to use these pins, additional hardware must
be provided on the user board.)
3. Area H'7000 to H'7FFF is used by the E10T, and is not available to the user.
4. Area H'F780 to H'FB7F must on no account be accessed.
5. When the E10T is used, address breaks can be set as available to the user, or for use by the
E10T. If address breaks are set as being used by the E10T, the address break control registers
must not be accessed.
6. When the E10T is used, NMI is an input/output pin (open-drain in output mode), P85 and P87
are input pins, and P86 is an output pin.
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Main Revisions and Additions in this Edition
Page Item Description
4 Figure 1.1 Block Diagram TEST pin is amended to TEST pin
43 2.9.2 Notes on Bit Manipulation Example 1 description added
54 3.4.2 Interrupt Edge Select Register 2 (IEGR2) Bit 5 description amended
79 Figure 5.9 Pin Connection when not Using
Subclock
88 Table 6.3 Transition Mode after the SLEEP
Instruction Execution and Interrupt Handling
102 Figure 7.4 User Program Mode Figure amended
122 7.9 Flash Memory and Power-Down States
Table 7.10 Flash Memory Operating States
179 Figure 11.2 Increment Timing with Internal Clock Figure amended
281 14.5.1 Data Transfer Format 1st line, reference figure No.
322 Figure 15.5 I2C Bus Timing R/W is amended to R/W
322 to
324
324 to
326
15.3.2 Master Transmit Operation
Figure 15.6 Example of Master Transmit Mode
Operation Timing (MLS = WAIT = 0)
15.3.3 Master Receive Operation
Figure 15.7 Example of Master Receive Mode
Operation Timing (1) (NLS = ACKB = 0, WAIT = 1)
Figure amended
*1 description changed
Description amended
amended
Description changed
Figure amended
Description changed
Figure amended
Figure 15.7 Example of Master Receive Mode
Operation Timing (2) (NLS = ACKB = 0, WAIT = 1)
326 15.3.4 Slave Receive Operation R/W is amended to R/W
327 Figure 15.8 Example of Slave Receive Mode
Operation Timing (1) (MLS = ACKB = 0)
328 15.3.5 Slave Transmit Operation Description amended
329 Figure 15.10 Example of Slave Transmit Mode
Operation Timing (MLS = 0)
332 Figure 15.13 Flowchart for Master Transmit Mode
(Example)
333 Figure 15.14 Flowchart for Master Receive Mode
(Example)
R/W is amended to R/W
R/W is amended to R/W
Flowchart changed
Flowchart changed
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Page Item Description
339,
340
15.4 Usage Notes
• Notes on Start Condition Issuance for
Description added
Retransmission
Figure 15.17 Flowchart and Timing of Start
Condition Instruction Issuance for Retransmission
348 16.2.3 A/D Control Register (ADCR) Bit 7 Note added
367 Table 18.2 DC Characteristics (2) Conditions changed
370 Table 18.4 I2C Bus Interface Timing Symbol in SCL and SDA output fall
time amended
372,
373
Table 18.6 A/D Converter Characteristics Min Value in AVcc amended
Test Condition of Conversion time
(single mode) amended
373 Table 18.7 Watchdog Timer Characteristics Unit amended
376 to
18.3 Electrical Characteristics (Mask ROM Version) Added
388
411 to
A.3 Number of Execution States Added
417
423 B.2 Register Bits Bit name in ABRKSR amended
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Contents
Section 1 Overview............................................................................................................ 1
1.1 Features .............................................................................................................................. 1
1.2 Internal Block Diagram......................................................................................................4
1.3 Pin Arrangement ................................................................................................................ 5
1.4 Pin Functions...................................................................................................................... 7
Section 2 CPU...................................................................................................................... 11
2.1 Features .............................................................................................................................. 11
2.2 Address Space and Memory Map ...................................................................................... 12
2.3 Register Configuration ....................................................................................................... 15
2.3.1 General Registers.................................................................................................. 16
2.3.2 Program Counter (PC) .......................................................................................... 17
2.3.3 Condition Code Register (CCR) ........................................................................... 17
2.4 Data Formats ...................................................................................................................... 19
2.4.1 General Register Data Formats ............................................................................. 19
2.4.2 Memory Data Formats .......................................................................................... 21
2.5 Instruction Set .................................................................................................................... 22
2.5.1 Instruction Set Overview ...................................................................................... 22
2.5.2 Basic Instruction Formats...................................................................................... 32
2.6 Addressing Modes and Effective Address Calculation...................................................... 33
2.6.1 Addressing Modes................................................................................................. 33
2.6.2 Effective Address Calculation............................................................................... 35
2.7 Basic Bus Cycle.................................................................................................................. 39
2.7.1 Access to On-Chip Memory (RAM, ROM).......................................................... 39
2.7.2 Access to On-Chip Peripheral Modules................................................................ 40
2.8 CPU States.......................................................................................................................... 41
2.8.1 Overview............................................................................................................... 41
2.9 Application Notes............................................................................................................... 42
2.9.1 Notes on Data Access to Empty Areas.................................................................. 42
2.9.2 Notes on Bit Manipulation.................................................................................... 43
2.9.3 Notes on Use of the EEPMOV Instruction ........................................................... 48
Section 3 Exception Handling........................................................................................ 49
3.1 Overview............................................................................................................................ 49
3.1.1 Exception Handling Types.................................................................................... 49
3.2 Reset................................................................................................................................... 49
3.2.1 Reset Sequence...................................................................................................... 49
3.2.2 Reset by Watchdog Timer..................................................................................... 50
3.2.3 Interrupt Immediately after Reset ......................................................................... 50
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3.3 Interrupts ............................................................................................................................ 51
3.3.1 Interrupt and Vector Address................................................................................ 51
3.4 Interrupt Control Registers.................................................................................................53
3.4.1 Interrupt Edge Select Register 1 (IEGR1) ............................................................ 53
3.4.2 Interrupt Edge Select Register 2 (IEGR2) ............................................................ 54
3.4.3 Interrupt Enable Register 1 (IENR1) .................................................................... 55
3.4.4 Interrupt Flag Register 1 (IRR1)........................................................................... 56
3.4.5 Wakeup Interrupt Flag Register (IWPR) .............................................................. 57
3.5 Interrupt Sources ................................................................................................................ 58
3.5.1 External Interrupts................................................................................................. 58
3.5.2 Internal Interrupts.................................................................................................. 58
3.5.3 Interrupt Operations.............................................................................................. 59
3.5.4 Interrupt Response Time....................................................................................... 62
3.6 Trap Instruction.................................................................................................................. 62
3.7 Application Notes............................................................................................................... 62
3.7.1 Notes on Stack Area Use ...................................................................................... 62
3.7.2 Notes on Rewriting Port Mode Registers.............................................................. 63
Section 4 Address Break.................................................................................................. 67
4.1 Overview............................................................................................................................ 67
4.1.1 Block Diagram...................................................................................................... 67
4.1.2 Register Configuration.......................................................................................... 68
4.2 Register Descriptions.......................................................................................................... 68
4.2.1 Address Break Control Register (ABRKCR)........................................................ 68
4.2.2 Address Break Status Register (ABRKSR) .......................................................... 70
4.2.3 Break Address Registers (BARH, BARL)............................................................ 71
4.2.4 Break Data Registers (BDRH, BDRL) ................................................................. 72
4.3 Operation............................................................................................................................ 72
Section 5 Clock Pulse Generators.................................................................................. 75
5.1 Overview............................................................................................................................ 75
5.1.1 Block Diagram...................................................................................................... 75
5.1.2 System Clock and Subclock.................................................................................. 75
5.2 System Clock Generator..................................................................................................... 76
5.3 Subclock Generator............................................................................................................ 78
5.4 Prescalers............................................................................................................................ 79
5.5 Usage Notes........................................................................................................................ 80
5.5.1 Note on Oscillators................................................................................................ 80
5.5.2 Notes on Board Design ......................................................................................... 80
Section 6 Power-down Modes........................................................................................ 81
6.1 Overview............................................................................................................................ 81
6.1.1 Register Configuration.......................................................................................... 81
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6.2 Register Descriptions.......................................................................................................... 82
6.2.1 System Control Register 1 (SYSCR1).................................................................. 82
6.2.2 System Control Register 2 (SYSCR2).................................................................. 83
6.2.3 Module Standby Control Register 1 (MSTCR1) .................................................. 85
6.3 Mode Transition Conditions............................................................................................... 87
6.4 Sleep Mode......................................................................................................................... 90
6.4.1 Transition to the Sleep Mode................................................................................ 90
6.4.2 Clearing the Sleep Mode....................................................................................... 90
6.5 Standby Mode .................................................................................................................... 90
6.5.1 Transition to the Standby Mode............................................................................ 90
6.5.2 Clearing the Standby Mode................................................................................... 91
6.5.3 Oscillator Settling Time after the Standby Mode is Cleared ................................ 91
6.6 Subsleep Mode ................................................................................................................... 92
6.6.1 Transition to the Subsleep Mode .......................................................................... 92
6.6.2 Clearing the Subsleep Mode ................................................................................. 92
6.7 Subactive Mode.................................................................................................................. 93
6.7.1 Transition to the Subactive Mode ......................................................................... 93
6.7.2 Clearing the Subactive Mode................................................................................ 93
6.8 Active Mode....................................................................................................................... 94
6.8.1 Transition to the Active Mode .............................................................................. 94
6.8.2 Transition from the Active Mode to Other Modes................................................ 94
6.8.3 Operating Frequency in the Active Mode............................................................. 94
6.9 Direct Transition ................................................................................................................ 95
6.9.1 Direct Transition Time.......................................................................................... 95
6.10 Module Standby Mode ....................................................................................................... 96
Section 7 ROM.................................................................................................................... 97
7.1 Features .............................................................................................................................. 97
7.2 Overview............................................................................................................................ 98
7.2.1 Block Diagram...................................................................................................... 98
7.2.2 On-board Programming Mode.............................................................................. 99
7.2.3 Block Configuration.............................................................................................. 103
7.2.4 Pin Configuration.................................................................................................. 103
7.2.5 Register Configuration.......................................................................................... 104
7.3 Register Descriptions.......................................................................................................... 104
7.3.1 Flash Memory Control Register 1 (FLMCR1)...................................................... 104
7.3.2 Flash Memory Control Register 2 (FLMCR2)...................................................... 106
7.3.3 Erase Block Register 1 (EBR1) ............................................................................ 107
7.3.4 Flash Memory Power Control Register (FLPWCR)............................................. 108
7.3.5 Flash Memory Enable Register (FENR)............................................................... 108
7.4 Boot Mode.......................................................................................................................... 109
7.4.1 Automatic SCI Bit Rate Adjustment..................................................................... 111
7.4.2 Programming Control Program Area.................................................................... 111
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7.4.3 Notes on Use of Boot Mode.................................................................................. 112
7.5 User Program Mode ........................................................................................................... 112
7.6 Programming/Erasing Flash Memory................................................................................ 113
7.6.1 Program/Program-Verify ...................................................................................... 114
7.6.2 Erase/Erase-Verify................................................................................................ 117
7.6.3 Interrupts during Flash Memory Programming/Erasing....................................... 117
7.7 Protection............................................................................................................................ 119
7.7.1 Hardware Protection.............................................................................................. 119
7.7.2 Software Protection............................................................................................... 120
7.7.3 Error Protection..................................................................................................... 120
7.8 Interrupt Handling when Programming/Erasing Flash Memory........................................ 121
7.9 Flash Memory and Power-Down States............................................................................. 122
7.10 Flash Memory Programmer Mode ..................................................................................... 122
7.10.1 Socket Adapter Pin Correspondence Diagram...................................................... 123
7.10.2 Programmer Mode Operation................................................................................ 125
7.10.3 Memory Read Mode.............................................................................................. 126
7.10.4 Auto-Program Mode ............................................................................................. 129
7.10.5 Auto-Erase Mode.................................................................................................. 131
7.10.6 Status Read Mode.................................................................................................. 133
7.10.7 Status Polling ........................................................................................................ 134
7.10.8 Programmer Mode Transition Time...................................................................... 134
7.10.9 Notes on Memory Programming........................................................................... 135
Section 8 RAM.................................................................................................................... 137
8.1 Overview............................................................................................................................ 137
8.1.1 Block Diagram...................................................................................................... 137
Section 9 I/O Ports ............................................................................................................. 139
9.1 Overview............................................................................................................................ 139
9.2 Port 1 .................................................................................................................................. 140
9.2.1 Overview............................................................................................................... 140
9.2.2 Register Configuration and Description................................................................ 140
9.2.3 Port Data Register 1 (PDR1)................................................................................. 141
9.2.4 Port Control Register 1 (PCR1) ............................................................................ 141
9.2.5 Port Pull-Up Control Register 1 (PUCR1)............................................................ 141
9.2.6 Port Mode Register 1 (PMR1) .............................................................................. 142
9.2.7 Pin Functions......................................................................................................... 144
9.2.8 MOS Input Pull-Up............................................................................................... 145
9.3 Port 2 .................................................................................................................................. 146
9.3.1 Overview............................................................................................................... 146
9.3.2 Register Configuration and Description................................................................ 146
9.3.3 Port Data Register 2 (PDR2)................................................................................. 146
9.3.4 Port Control Register 2 (PCR2) ............................................................................ 147
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9.3.5 Pin Functions......................................................................................................... 148
9.4 Port 5 .................................................................................................................................. 149
9.4.1 Overview............................................................................................................... 149
9.4.2 Register Configuration and Description................................................................ 149
9.4.3 Port Data Register 5 (PDR5)................................................................................. 150
9.4.4 Port Control Register 5 (PCR5) ............................................................................ 150
9.4.5 Port Pull-Up Control Register 5 (PUCR5)............................................................ 151
9.4.6 Port Mode Register 5 (PMR5) .............................................................................. 151
9.4.7 Pin Functions......................................................................................................... 152
9.4.8 MOS Input Pull-Up............................................................................................... 153
9.5 Port 7 .................................................................................................................................. 154
9.5.1 Overview............................................................................................................... 154
9.5.2 Register Configuration and Description................................................................ 154
9.5.3 Port Data Register 7 (PDR7)................................................................................. 154
9.5.4 Port Control Register 7 (PCR7) ............................................................................ 155
9.5.5 Pin Functions......................................................................................................... 155
9.6 Port 8 .................................................................................................................................. 156
9.6.1 Overview............................................................................................................... 156
9.6.2 Register Configuration and Description................................................................ 156
9.6.3 Port Data Register 8 (PDR8)................................................................................. 157
9.6.4 Port Control Register 8 (PCR8) ............................................................................ 157
9.6.5 Pin Functions......................................................................................................... 158
9.7 Port B.................................................................................................................................. 161
9.7.1 Overview............................................................................................................... 161
9.7.2 Register Configuration and Description................................................................ 161
9.7.3 Port Data Register B (PDRB)................................................................................ 161
9.7.4 Pin Functions......................................................................................................... 162
Section 10 Timer A .............................................................................................................. 163
10.1 Overview............................................................................................................................ 163
10.1.1 Features ................................................................................................................. 163
10.1.2 Block Diagram...................................................................................................... 164
10.1.3 Pin Configuration.................................................................................................. 164
10.1.4 Register Configuration.......................................................................................... 165
10.2 Register Descriptions.......................................................................................................... 165
10.2.1 Timer Mode Register A (TMA)............................................................................ 165
10.2.2 Timer Counter A (TCA)........................................................................................ 166
10.3 Timer Operation ................................................................................................................. 167
10.3.1 Interval Timer Operation ...................................................................................... 167
10.3.2 Clock Time Base Operation.................................................................................. 167
10.3.3 Clock Output ......................................................................................................... 167
10.4 Timer A Operation States................................................................................................... 168
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Section 11 Timer V .............................................................................................................. 169
11.1 Overview............................................................................................................................ 169
11.1.1 Features ................................................................................................................. 169
11.1.2 Block Diagram...................................................................................................... 170
11.1.3 Pin Configuration.................................................................................................. 171
11.1.4 Register Configuration.......................................................................................... 171
11.2 Register Descriptions.......................................................................................................... 172
11.2.1 Timer Counter V (TCNTV).................................................................................. 172
11.2.2 Time Constant Registers A and B (TCORA, TCORB)........................................ 172
11.2.3 Timer Control Register V0 (TCRV0)................................................................... 173
11.2.4 Timer Control/Status Register V (TCSRV).......................................................... 175
11.2.5 Timer Control Register V1 (TCRV1)................................................................... 177
11.3 Timer Operation ................................................................................................................. 178
11.3.1 Timer V Operation Modes.................................................................................... 182
11.3.2 Interrupt Sources ................................................................................................... 182
11.3.3 Application Examples ........................................................................................... 183
11.3.4 Application Notes.................................................................................................. 185
Section 12 Timer W ............................................................................................................. 191
12.1 Overview............................................................................................................................ 191
12.1.1 Features ................................................................................................................. 191
12.1.2 Block Diagrams..................................................................................................... 193
12.1.3 Input/Output Pins.................................................................................................. 194
12.1.4 Register Configuration.......................................................................................... 195
12.2 Register Description........................................................................................................... 196
12.2.1 Timer Mode Register W (TMRW) ....................................................................... 196
12.2.2 Timer Control Register W (TCRW)...................................................................... 197
12.2.3 Timer Interrupt Enable Register W (TIERW)...................................................... 199
12.2.4 Timer Status Register W (TSRW)........................................................................ 201
12.2.5 Timer I/O Control Register 0 (TIOR0)................................................................. 203
12.2.6 Timer I/O Control Register 1 (TIOR1)................................................................. 204
12.2.7 Timer Counter (TCNT)......................................................................................... 206
12.2.8 General Registers A to D (GRA to GRD)............................................................. 206
12.3 CPU Interface..................................................................................................................... 207
12.3.1 16-Bit Registers..................................................................................................... 207
12.3.2 8-Bit Registers....................................................................................................... 207
12.4 Operation............................................................................................................................ 208
12.4.1 Overview............................................................................................................... 208
12.4.2 Operation Timing.................................................................................................. 223
12.5 Usage Notes........................................................................................................................ 228
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Section 13 Watchdog Timer.............................................................................................. 237
13.1 Overview............................................................................................................................ 237
13.1.1 Features ................................................................................................................. 237
13.1.2 Block Diagram...................................................................................................... 237
13.1.3 Register Configuration.......................................................................................... 238
13.2 Register Descriptions.......................................................................................................... 238
13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 238
13.2.2 Timer Counter WD (TCWD)................................................................................ 240
13.2.3 Timer Mode Register WD (TMWD).................................................................... 241
13.3 Operation............................................................................................................................ 242
13.3.1 Watchdog Timer Operating Modes....................................................................... 243
Section 14 Serial Communication Interface 3.............................................................. 245
14.1 Overview............................................................................................................................ 245
14.1.1 Features ................................................................................................................. 245
14.1.2 Block Diagram...................................................................................................... 247
14.1.3 Pin Configuration.................................................................................................. 248
14.1.4 Register Configuration.......................................................................................... 248
14.2 Register Descriptions.......................................................................................................... 249
14.2.1 Receive Shift Register (RSR)................................................................................ 249
14.2.2 Receive Data Register (RDR)............................................................................... 249
14.2.3 Transmit Shift Register (TSR).............................................................................. 250
14.2.4 Transmit Data Register (TDR).............................................................................. 250
14.2.5 Serial Mode Register (SMR)................................................................................. 251
14.2.6 Serial Control Register 3 (SCR3).......................................................................... 253
14.2.7 Serial Status Register (SSR).................................................................................. 256
14.2.8 Bit Rate Register (BRR)........................................................................................ 260
14.3 Operation............................................................................................................................ 267
14.3.1 Asynchronous Mode ............................................................................................. 267
14.3.2 Synchronous Mode................................................................................................ 267
14.3.3 Interrupts and Continuous Transmission/Reception............................................. 269
14.4 Operation in Asynchronous Mode...................................................................................... 271
14.4.1 Data Transfer Format............................................................................................ 271
14.4.2 Clock ..................................................................................................................... 273
14.4.3 Data Transfer Operations...................................................................................... 273
14.5 Operation in Synchronous Mode........................................................................................ 280
14.5.1 Data Transfer Format............................................................................................ 281
14.5.2 Clock ..................................................................................................................... 281
14.5.3 Data Transfer Operations...................................................................................... 282
14.6 Multiprocessor Communication Function.......................................................................... 287
14.7 Interrupts ............................................................................................................................ 294
14.8 Usage Notes........................................................................................................................ 295
14.8.1 Relation between Writes to TDR and Bit TDRE.................................................. 295
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14.8.2 Operation when a Number of Receive Errors Occur Simultaneously.................. 295
14.8.3 Break Detection and Processing............................................................................ 296
14.8.4 Mark State and Break Detection........................................................................... 296
14.8.5 Receive Error Flags and Transmit Operation (Synchronous Mode Only)............ 296
14.8.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode.... 296
14.8.7 Relation between RDR Reads and Bit RDRF....................................................... 298
Section 15 I2C Bus Interface (IIC)................................................................................... 299
15.1 Overview............................................................................................................................ 299
15.1.1 Features ................................................................................................................. 299
15.1.2 Block Diagram...................................................................................................... 300
15.1.3 Pin Configuration.................................................................................................. 301
15.1.4 Register Configuration.......................................................................................... 302
15.2 Register Descriptions.......................................................................................................... 303
15.2.1 I2C Bus Data Register (ICDR).............................................................................. 303
15.2.2 Slave Address Register (SAR).............................................................................. 306
15.2.3 Second Slave Address Register (SARX).............................................................. 307
15.2.4 I2C Bus Mode Register (ICMR)............................................................................ 307
15.2.5 I
15.2.6 I
2
C Bus Control Register (ICCR).......................................................................... 310
2
C Bus Status Register (ICSR)............................................................................. 316
15.2.7 Timer Serial Control Register (TSCR).................................................................. 320
15.3 Operation............................................................................................................................ 321
15.3.1 I2C Bus Data Format.............................................................................................. 321
15.3.2 Master Transmit Operation................................................................................... 322
15.3.3 Master Receive Operation..................................................................................... 324
15.3.4 Slave Receive Operation....................................................................................... 326
15.3.5 Slave Transmit Operation...................................................................................... 328
15.3.6 IRIC Setting Timing and SCL Control ................................................................. 330
15.3.7 Noise Canceler...................................................................................................... 331
15.3.8 Sample Flowcharts................................................................................................ 331
15.4 Usage Notes........................................................................................................................ 336
Section 16 A/D Converter.................................................................................................. 341
16.1 Overview............................................................................................................................ 341
16.1.1 Features ................................................................................................................. 341
16.1.2 Block Diagram...................................................................................................... 342
16.1.3 Input Pins .............................................................................................................. 343
16.1.4 Register Configuration.......................................................................................... 344
16.2 Register Descriptions.......................................................................................................... 344
16.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 344
16.2.2 A/D Control/Status Register (ADCSR)................................................................ 345
16.2.3 A/D Control Register (ADCR).............................................................................. 347
16.3 CPU Interface..................................................................................................................... 348
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16.4 Operation............................................................................................................................ 350
16.4.1 Single Mode (SCAN = 0)...................................................................................... 350
16.4.2 Scan Mode (SCAN = 1)........................................................................................ 352
16.4.3 Input Sampling and A/D Conversion Time.......................................................... 354
16.4.4 External Trigger Input Timing.............................................................................. 355
16.5 Interrupts ............................................................................................................................ 356
16.6 Usage Notes........................................................................................................................ 356
Section 17 Power Supply Circuit..................................................................................... 359
17.1 Overview............................................................................................................................ 359
17.2 When Using the Internal Power Supply Step-Down Circuit.............................................. 359
17.3 When Not Using the Internal Power Supply Step-Down Circuit....................................... 360
Section 18 Electrical Characteristics............................................................................... 361
18.1 Absolute Maximum Ratings............................................................................................... 361
18.2 Electrical Characteristics (F-ZTAT™ Version)................................................................. 361
18.2.1 Power Supply Voltage and Operating Ranges...................................................... 361
18.2.2 DC Characteristics ................................................................................................ 363
18.2.3 AC Characteristics ................................................................................................ 368
18.2.4 A/D Converter Characteristics.............................................................................. 372
18.2.5 Watchdog Timer.................................................................................................... 373
18.2.6 Flash Memory Characteristics (Preliminary)........................................................ 374
18.3 Electrical Characteristics (Mask ROM Version)................................................................ 376
18.3.1 Power Supply Voltage and Operating Ranges...................................................... 376
18.3.2 DC Characteristics ................................................................................................ 378
18.3.3 AC Characteristics ................................................................................................ 383
18.3.4 A/D Converter Characteristics.............................................................................. 387
18.3.5 Watchdog Timer.................................................................................................... 388
18.4 Operation Timing ............................................................................................................... 389
18.5 Output Load Circuit............................................................................................................ 392
Appendix A Instruction Set................................................................................................ 393
A.1 Instruction List.................................................................................................................... 393
A.2 Operation Code Map .......................................................................................................... 408
A.3 Number of Execution States............................................................................................... 411
A.4 Combinations of Instructions and Addressing Modes........................................................ 418
Appendix B Internal I/O Registers.................................................................................. 419
B.1 Register Addresses ............................................................................................................. 419
B.2 Register Bits ....................................................................................................................... 422
Appendix C I/O Port Block Diagrams............................................................................ 425
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Appendix D Port States in the Different Processing States...................................... 442
Appendix E Model Names................................................................................................. 443
Appendix F Package Dimensions.................................................................................... 444
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Section 1 Overview
1.1 Features
Table 1.1 Features
Item Description
CPU H8/300H CPU (upward compatibility with H8/300 CPU at object level)
• General-register machine
Sixteen 16-bit registers (also usable as eight 16-bit registers plus
sixteen 8-bit registers or eight 32-bit registers)
• High-speed operation
Max. operation speed: 16 MHz
Add/subtract: 0.125 µs
Multiply/divide: 0.875 µs
• Address space: 64 kbytes
Interrupts
Clock pulse
generators
Power-down
modes
• Instruction features
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions
(8 bits × 8 bits, 16 bits × 16 bits)
Signed and unsigned divide instructions
(16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit
positions
• 11 external interrupt sources (NMI, IRQ3 to IRQ0, WKP5 to WKP0)
• 20 internal interrupt sources
• System clock pulse generator: 1 to 16 MHz
• Sub-system clock pulse generator: 32.768 kHz (for watch)
Transition possible between five modes
• Active mode
• Sleep mode
• Standby mode
• Subsleep mode
• Subactive mode
Gear function
• Module standby function
1
Page 18
Item Description
Memory
Type No. ROM RAM
HD64F3664 (Flash memory version) 32 kbytes 2,048 bytes
HD6433664 (Mask ROM version) 32 kbytes 1,024 bytes
HD6433663 (Mask ROM version) 24 kbytes 1,024 bytes
HD6433662 (Mask ROM version) 16 kbytes 512 bytes
HD6433661 (Mask ROM version) 12 kbytes 512 bytes
HD6433660 (Mask ROM version) 8 kbytes 512 bytes
I/O ports
Timers
• 29 I/O pins, including 8 large current ports (I
= 20 mA, @ VOL = 1.5 V
OL
• 8 input pins (also used for analog input)
• Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from the
system clock and four clock signals divided from the watch sub-clock
• Timer V: 8-bit timer
Count-up timer with selection of six internal clock signals or event input
from external pin
Compare-match waveform output
Externally triggerable
• Timer W: 16-bit timer
Counts any of four internal clock signals or external events
Maximum of four types of pulses can be input or output and processed
Output compare/input capture (4 output pins)
Output compare/input capture operation can be buffered
PWM mode can be set (maximum of three synchronous outputs)
• Watchdog timer: 8-bit timer
Reset signal generated by counter overflow
Operates independent from system clock by internal oscillation circuit
Serial
communication
interface
• Selectable between asynchronous mode or 8-bit clock synchronous mode
• Incorporate baud rate generator
• Multi-processor communication function (asynchronous)
2
Page 19
Item Description
2
C bus
I
interface
• Conforms to I
• Selectable between single master mode and slave mode
• Supports two slave addresses
2
C bus interface proposed by Philips Electronics
A/D converter
Package
• 10-bit resolution
• 8-channel analog input pins (selectable between single mode and scan mode)
• Conversion time: 7 µs
• Sample and hold function
Code Body Size Pin Pitch
QFP-64 (FP-64E) 10.0 × 10.0 mm 0.5 mm
QFP-64 (FP-64A) 14.0 × 14.0 mm 0.8 mm
SDIP-42 (DP-42S) 14.0 × 37.3 mm 1.78 mm
3
Page 20
1.2 Internal Block Diagram
VCLVSSVCCRES
P10/TMOW
P11
P12
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
P20/SCK3
P21/RXD
P22/TXD
P57/SCL
P56/SDA
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
P51/WKP1
P50/WKP0
TEST
NMI
X1
Subclock
generator
Port 1
Port 2Port 5
X2
OSC1
OSC2
System
clock
generator
CPU
H8/300H
Data bus (lower)
ROM
Timer W
Timer A
Timer V
A/D converter
RAM
2
I
C bus
interface
SCI3
Watchdog
timer
Address bus
Data bus (upper)
Port 7Port 8
P76/TMOV
P75/TMCIV
P74/TMRIV
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
= 1.5 V
OL
= 20 mA @ V
OL
CMOS large current port
I
4
Port B
CC
AV
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Figure 1.1 Block Diagram
Page 21
1.3 Pin Arrangement
NC
NC
P14/IRQ0
P15/IRQ1
P16/IRQ2
P17/IRQ3/TRGV
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
NC
NC
NCNCP22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTIOD
P83/FTIOC
P82/FTIOB
P81/FTIOA
P80/FTCI
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
H8/3664 Series
Top view
58
59
60
61
62
63
64
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
NMI
NC
NC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
NC
NC
P76/TMOV
P75/TMCIV
P74/TMRIV
P57/SCL
P56/SDA
P12
P11
P10/TMOW
P55/WKP5/ADTRG
P54/WKP4
P53/WKP3
P52/WKP2
NC
NC
NC
Note: Do not connect NC pins.
Figure 1.2 Pin Arrangement (FP-64E, FP-64A)
NC
CC
AV
X2
X1
CL
V
RES
V
TEST
SS
OSC2
OSC1
CC
V
P50/WKP0
P51/WKP1
NC
NC
5
Page 22
PB3/AN3
1
42
P17/IRQ3/TRGV
PB2/AN2
PB1/AN1
PB0/AN0
AV
CC
X2
X1
V
CL
RES
TEST
V
SS
OSC2
OSC1
V
CC
P50/WKP0
P51/WKP1
P52/WKP2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
H8/3664 Series
Top view
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P16/IRQ2
P15/IRQ1
P14/IRQ0
P22/TXD
P21/RXD
P20/SCK3
P87
P86
P85
P84/FTI0D
P83/FTI0C
P82/FTI0B
P81/FTI0A
P80/FTCI
NMI
P76/TMOV
P53/WKP3
P54/WKP4
P55/WKP5/ADTRG
P10/TMOW
18
19
20
21
25
24
23
22
P75/TMCIV
P74/TMRIV
P57/SCL
P56/SDA
Note: DP-42S has no P11, P12, PB4/AN4, PB5/AN5, PB6/AN6, and PB7/AN7 pins.
Figure 1.3 Pin Arrangement (DP-42S)
6
Page 23
1.4 Pin Functions
Table 1.2 Pin Functions
Type Symbol
Pin No.
FP-64E
FP-64A DP-42S I/O Name and Functions
Power
source pins
V
CC
12 14 Input Power supply: All VCC pins should
be connected to the user system
V
.
CC
V
SS
9 11 Input Ground: All VSS pins should be
connected to the user system GND
(0 V).
AV
CC
3 5 Input Analog power supply: This is the
power supply pin for the A/D
converter. When the A/D converter
is not used, connect this pin to the
user system V
V
CL
6 8 Input Internal step-down power supply:
CC
.
Connect a capacitor of around
0.1 µF between this pin and the V
SS
pin for stabilization.
Clock pins OSC1 11 13 Input System clock: These pins connect
to a crystal or ceramic oscillator, or
can be used to input an external
clock.
OSC2 10 12 Output
See section 5, Clock Pulse
Generators, for a typical connection
diagram.
X1 5 7 Input Subclock: These pins connect to a
X2 4 6 Output
System
RES 7 9 Input Reset: When this pin is driven low,
control
TEST 8 10 Input Test: This is a test pin, not for use
32.768-kHz crystal oscillator.
See section 5, Clock Pulse
Generators, for a typical connection
diagram.
the chip is reset.
in application systems. It should be
connected to V
SS
.
7
Page 24
Type Symbol
Pin No.
FP-64E
FP-64A DP-42S I/O Name and Functions
Interrupt
pins
NMI 35 27 Input Non-maskable interrupt request
input pin
IRQ0 to
IRQ3
51 to 54 39 to 42 Input IRQ interrupt request 0 to 3:
These are input pins for edgesensitive external interrupts, with a
selection of rising or falling edge.
WKP0 to
WKP5
13, 14,
19 to 22
15 to 20 Input WKP interrupt request 0 to 5:
These are input pins for edgesensitive external interrupts, with a
selection of rising or falling edge.
Timer A TMOW 23 21 Output Clock output: This is an output pin
for waveforms generated by the
timer A output circuit.
Timer V TMOV 30 26 Output Timer V output: This is an output
pin for waveforms generated by the
timer V output compare function.
TMCIV 29 25 Input Timer V event input: This is an
event input pin for input to the timer
V counter.
TMRIV 28 24 Input Timer V counter reset: This is a
counter reset input pin for timer V.
TRGV 54 42 Input Timer V counter trigger input:
This is a trigger input pin for the
timer V counter.
Timer W FTCI 36 28 Input Timer W clock input: This is an
external clock input pin for input to
the timer X counter.
I2C bus
inerface
FTIOA to
FTIOD
SDA 26 22 I/O I2C data I/O: Can directly drive a
37 to 40 29 to 32 I/O Timer W output compare A/input
capture/PWM output pin
bus by NMOS open-drain output.
SCL 27 23 I/O I2C clock I/O: Can directly drive a
bus by NMOS open-drain output.
8
Page 25
Type Symbol
Pin No.
FP-64E
FP-64A DP-42S I/O Name and Functions
Serial communication
interface
(SCI)
TXD 46 38 Output SCI3 transmit data output: This is
the data output pin.
RXD 45 37 Input SCI3 receive data input: This is
the data input pin.
SCK3 44 36 Output SCI3 clock I/O: This is the clock
I/O pin.
A/D
converter
AN7 to AN0 55 to 62 1 to 4 Input Analog input channels 7 to 0:
These are analog data input
channels to the A/D converter.
ADTRG 22 20 Input A/D converter trigger input: This
is the external trigger input pin to
the A/D converter.
I/O ports PB7 to PB0 55 to 62 1 to 4 Input Port B: This is an 8-bit input port.
P17 to P14,
P12 to P10
51 to 54,
23 to 25
39 to 42,21I/O Port 1: This is a 7-bit I/O port.
P22 to P20 44 to 46 36 to 38 I/O Port 2: This is a 3-bit I/O port.
P57 to P50 13, 14,
19 to 22,
15 to 20,
22, 23
I/O Port 5: This is an 8-bit I/O port.
26, 27
P76 to P74 28 to 30 24 to 26 I/O Port 7: This is a 3-bit I/O port.
P87 to P80 36 to 43 28 to 35 I/O Port 8: This is an 8-bit I/O port.
Other NC Non-connected pins: These pins
must be left unconnected.
9
Page 26
10
Page 27
Section 2 CPU
2.1 Features
The H8/3664 Series has an H8/300H CPU with an internal 32-bit architecture that is upwardcompatible with the H8/300 CPU, and supports only normal mode, which has a 64-kbyte address
space.
The H8/300H CPU has the following features.
• Upward compatibility with H8/300 CPU
Can execute H8/300 Series object programs
Additional eight 16-bit extended registers
32-bit transfer and arithmetic and logic instructions are added
Signed multiply and divide instructions are added
• General registers
Sixteen 16-bit general registers (also usable as sixteen 8-bit registers and eight 16-bit
registers or eight 32-bit registers)
• Sixty-two basic instructions
8/16/32-bit data transfer and arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, or @aa:24]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8, PC) or @(d:16, PC)]
Memory indirect [@@aa:8]
• 64-kbyte address space
• High-speed operation
All frequently-used instructions execute in two to four states
Maximum clock frequency: 16 MHz
8/16/32-bit register-register add/subtract: 2 states
8 × 8-bit register-register multiply: 14 states
16 ÷ 8-bit register-register divide: 14 states
11
Page 28
16 × 16-bit register-register multiply: 22 states
32 ÷ 16-bit register-register divide: 22 states
• Low-power mode
Transition to low-power state by SLEEP instruction
2.2 Address Space and Memory Map
The address space of the H8/3664 Series CPU is 64 kbytes, which includes the program area and
the data area.
Figures 2.1 and 2.2 show the memory map.
12
Page 29
H'0000
H'0033
H'0034
HD64F3664
(Flash memory version)
Interrupt vector
On-chip ROM
(32 kbytes)
H'0000
H'0033
H'0034
H'1FFF
HD6433660
(Mask ROM version)
Interrupt vector
On-chip ROM
(8 kbytes)
H'0000
H'0033
H'0034
H'2FFF
HD6433661
(Mask ROM version)
Interrupt vector
On-chip ROM
(12 kbytes)
H'7FFF
H'F780
H'FB7F
H'FB80
H'FF7F
H'FF80
H'FFFF
Not used
(1-kbyte work area
for flash memory
programming)
On-chip RAM
(2 kbytes)
(1-kbyte user area)
Internal I/O register
H'FD80
H'FF7F
H'FF80
H'FFFF
Not used
On-chip RAM
(512 bytes)
Internal I/O register
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
Figure 2.1 Memory Map (1)
13
Page 30
H'0000
H'0033
H'0034
HD6433662
(Mask ROM version)
Interrupt vector
On-chip ROM
(16 kbytes)
H'0000
H'0033
H'0034
HD6433663
(Mask ROM version)
Interrupt vector
On-chip ROM
(24 kbytes)
H'0000
H'0033
H'0034
HD6433664
(Mask ROM version)
Interrupt vector
H'3FFF
Not used
On-chip ROM
(32 kbytes)
H'5FFF
H'7FFF
Not used
Not used
H'FD80
On-chip RAM
(512 bytes)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
14
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
Figure 2.2 Memory Map (2)
H'FB80
On-chip RAM
(1 kbyte)
H'FF7F
H'FF80
Internal I/O register
H'FFFF
Page 31
2.3 Register Configuration
The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers:
general registers and control registers. Control registers are 24-bit program counter (PC) and 8-bit
condition code register (CCR).
General Registers (ERn)
0707015
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7
Control Registers (CR)
Legend
SP:
PC:
CCR:
I:
UI:
H:
U:
N:
Z:
V:
C:
Stack pointer
Program counter
Condition code register
Interrupt mask bit
User bit or interrupt mask bit
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
E0
E1
E2
E3
E4
E5
E6
E7
23 0
PC
(SP)
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
CCR
7
6543210
IUIHUNZVC
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
Figure 2.3 CPU Internal Registers
15
Page 32
2.3.1 General Registers
The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used without distinction between data registers and address registers. When a
general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register.
When the general registers are used as 32-bit registers or as address registers, they are designated
by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum of sixteen 8bit registers.
Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected
independently.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
E registers
(extended registers)
E0 to E7
ER registers
ER0 to ER7
R registers
R0 to R7
RH registers
R0H to R7H
RL registers
R0L to R7L
Figure 2.4 Usage of General Registers
16
Page 33
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the
stack.
Free area
SP (ER7)
Stack area
Figure 2.5 Relationship between Stack Pointer and Stack Area
2.3.2 Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant PC
bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. The PC
is initialized when the start address is loaded by the vector address generated during reset
exception-handling sequence.
2.3.3 Condition Code Register (CCR)
This 8-bit register contains internal CPU status information, including the interrupt mask bit (I)
and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. The I bit is initialized
to 1 by reset exception-handling sequence, but other bits are not initialized.
Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted
regardless of the I bit setting.
Bit 6—User Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC,
and XORC instructions.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is
set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L,
SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or
borrow at bit 27, and cleared to 0 otherwise.
17
Page 34
Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and
XORC instructions.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of data.
Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC,
STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional
branch (Bcc) instructions.
For the action of each instruction on the flag bits, see appendix A.1, Instruction List.
18
Page 35
2.4 Data Formats
The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
2.4.1 General Register Data Formats
Figures 2.6 and 2.7 show the data formats in general registers.
General
Data Type Data Format
1-bit data
1-bit data
Register
RnH
RnL
70
6543210
7
Don’t care
Don’t care
70
76543210
43
Lower digitUpper digit
Don’t care
Don’t care
Don’t care
7
70
MSB LSB
43
Lower digitUpper digit
Don’t care
0
4-bit BCD data
4-bit BCD data
Byte data
Byte data
70
RnH
RnL
70
RnH
MSB LSB
RnL
Figure 2.6 General Register Data Formats (1)
19
Page 36
Word data
General
RegisterData Type Data Format
15 0
Rn
MSB LSB
15 0
Word data
Longword data
Notation
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
En
ERn
MSB LSB
31 16
MSB
15 0
Figure 2.7 General Register Data Formats (2)
LSB
20
Page 37
2.4.2 Memory Data Formats
Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and
longword data on memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When ER7 (SP) is used as an address register to access the stack, the operand size should be word
size or longword size.
AddressData Type Data Format
70
1-bit data
Byte data
Word data
Longword data
Address L
Address 2M
Address 2M + 1
Address 2N
Address 2N + 1
76543210Address L
MSB LSB
MSB
LSB
MSB
Address 2N + 2
Address 2N + 3
LSB
Figure 2.8 Memory Data Formats
21
Page 38
2.5 Instruction Set
2.5.1 Instruction Set Overview
The H8/300H CPU has 62 types of instructions. Tables 2.1 to 2.8 summarize the instructions in
each functional category. The operation notation used in these tables is defined next.
Operation Notation
Rd General register (destination)*
Rs General register (source)*
Rn General register*
ERn General register (32-bit register or address register)
(EAd) Destination operand
(EAs) Source operand
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
PC Program counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
× Multiplication
÷ Division
∧ AND logical
∨ OR logical
⊕ Exclusive OR logical
→ Move
¬ NOT (logical complement)
:3/:8/:16/:24 3-, 8-, 16-, or 24-bit length
Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to
R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).
22
Page 39
Table 2.1 Data Transfer Instructions
Instruction Size* Function
MOV B/W/L (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
MOVFPE B (EAs) → Rd
Cannot be used in the H8/3664 Series.
MOVTPE B Rs → (EAs)
Cannot be used in the H8/3664 Series.
POP W/L @SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to
MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L
@SP+, ERn.
PUSH W/L Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L
ERn, @–SP.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
23
Page 40
Table 2.2 Arithmetic Operation Instructions
Instruction Size* Function
ADD, SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or
on immediate data and data in a general register. (Immediate byte
data cannot be subtracted from data in a general register. Use the
SUBX or ADD instruction.)
ADDX, SUBX B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on data in two
general registers, or on immediate data and data in a general
register.
INC, DEC B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte
operands can be incremented or decremented by 1 only.)
ADDS, SUBS L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit
register.
DAA, DAS B Rd decimal adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register
by referring to CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either
16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16
bits → 16-bit quotient and 16-bit remainder.
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits
→ 16-bit quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and sets CCR according to the
result.
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Instruction Size* Function
NEG B/W/L 0 – Rd → Rd
Takes the two’s complement (arithmetic complement) of data in a
general register.
EXTS W/L Rd (sign extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by extending the sign bit.
EXTU W/L Rd (zero extension) → Rd
Extends byte data in the lower 8 bits of a 16-bit register to word data,
or extends word data in the lower 16 bits of a 32-bit register to
longword data, by padding with zeros.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Table 2.3 Logic Operation Instructions
Instruction Size* Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT B/W/L ¬ Rd → Rd
Takes the one’s complement of general register contents.
Note: *Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.4 Shift Instructions
Instruction Size* Function
SHAL,
SHAR
SHLL,
SHLR
ROTL,
ROTR
ROTXL,
ROTXR
Note: *Size refers to the operand size.
B: Byte
W: Word
B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
B/W/L Rd (shift) → Rd
Performs a logical shift on general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents.
B/W/L Rd (rotate) → Rd
Rotates general register contents through the carry bit.
L: Longword
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Table 2.5 Bit Manipulation Instructions
Instruction Size* Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1.
The bit number is specified by 3-bit immediate data or the lower 3
bits of a general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0.
The bit number is specified by 3-bit immediate data or the lower 3
bits of a general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The
bit number is specified by 3-bit immediate data or the lower 3 bits of
a general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and
sets or clears the Z flag accordingly. The bit number is specified by
3-bit immediate data or the lower 3 bits of a general register.
BAND B C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIAND B C ∧ [¬ (<bit-No.> of <EAd>)] → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR B C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIOR B C ∨ [¬ (<bit-No.> of <EAd>)] → C
ORs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
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Instruction Size* Function
BXOR B C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register
or memory operand and stores the result in the carry flag.
BIXOR B C ⊕ [¬ (<bit-No.> of <EAd>)] → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BLD B (<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to
the carry flag.
BILD B ¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or
memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST B C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register
or memory operand.
BIST B C → ¬ (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a
general register or memory operand.
The bit number is specified by 3-bit immediate data.
Note: *Size refers to the operand size.
B: Byte
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Table 2.6 Branching Instructions
Instruction Size Function
Bcc* — Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA (BT) Always (true) Always
BRN (BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
Bcc (BHS) Carry clear (high or same) C = 0
BCS (BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greater or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z ∨ (N ⊕ V) = 0
BLE Less or equal Z ∨ (N ⊕ V) = 1
JMP — Branches unconditionally to a specified address
BSR — Branches to a subroutine at a specified address
JSR — Branches to a subroutine at a specified address
RTS — Returns from a subroutine
Note: *Conditional branch instructions are generally called the Bcc instructions.
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Table 2.7 System Control Instructions
Instruction Size* Function
TRAPA — Starts trap-instruction exception handling
RTE — Returns from an exception-handling routine
SLEEP — Causes a transition to the power-down state
LDC B/W (EAs) → CCR
Moves the source operand contents to the condition code register.
The condition code register size is one byte, but in transfer from
memory, data is read by word access.
STC B/W CCR → (EAd)
Transfers the CCR contents to a destination location. The condition
code register size is one byte, but in transfer to memory, data is
written by word access.
ANDC B CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data.
NOP — PC + 2 → PC
Only increments the program counter.
Note: *Size refers to the operand size.
B: Byte
W: Word
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Table 2.8 Block Transfer Instruction
Instruction Size Function
EEPMOV.B — if R4L ≠ 0 then
repeat @ER5+ → @ER6+, R4L – 1 → R4L
until R4L = 0
else next;
EEPMOV.W — if R4 ≠ 0 then
repeat @ER5+ → @ER6+, R4 – 1 → R4
until R4 = 0
else next;
Transfers a data block according to parameters set in general
registers R4L or R4, ER5, and ER6.
R4L or R4: Size of block (bytes)
ER5: Starting source address
ER6: Starting destination address
Execution of the next instruction begins as soon as the transfer is
completed.
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2.5.2 Basic Instruction Formats
The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (OP field), a register field (r field), an effective address extension (EA field), and a condition
field (cc field).
Operation Field: Indicates the function of the instruction, the addressing mode, and the operation
to be carried out on the operand. The operation field always includes the first 4 bits of the
instruction. Some instructions have two operation fields.
Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers
by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field.
Effective Address Extension: 8, 16, or 32 bits specifying immediate data, an absolute address, or
a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits
are 0 (H'00).
Condition Field: Specifies the branching condition of Bcc instructions.
Figure 2.9 shows examples of instruction formats.
Operation field only
op
Operation field and register fields
op rn rm
Operation field, register fields, and effective address extension
op rn rm
EA (disp)
Operation field, effective address extension, and condition field
op cc EA (disp)
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm
BRA d:8
32
Figure 2.9 Instruction Formats
Page 49
2.6 Addressing Modes and Effective Address Calculation
The following describes the H8/300H CPU. In the H8/3664 Series, the upper eight bits are ignored
in the generated 24-bit address, so the effective address is 16 bits.
2.6.1 Addressing Modes
The H8/300H CPU supports the eight addressing modes listed in table 2.9. Each instruction uses a
subset of these addressing modes. Addressing modes that can be used differ depending on the
instruction. For details, refer to appendix A, CPU Instruction Set. Arithmetic and logic instructions
can use the register direct and immediate modes. Data transfer instructions can use all addressing
modes except program-counter relative and memory indirect. Bit manipulation instructions use
register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and
register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing
mode to specify a bit number in the operand.
Table 2.9 Addressing Modes
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn)
4 Register indirect with post-increment
Register indirect with pre-decrement
5 Absolute address @aa:8/@aa:16/@aa:24
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-counter relative @(d:8, PC)/@(d:16, PC)
8 Memory indirect @@aa:8
@ERn+
@–ERn
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1 Register Direct—Rn: The register field of the instruction code specifies an 8-, 16-, or 32-bit
register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers.
R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit
registers.
2 Register Indirect—@ERn: The register field of the instruction code specifies an address
register (ERn), the lower 24 bits of which contain the address of the operand.
3 Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn): A 16-bit or 24-bit
displacement contained in the instruction code is added to the contents of an address register
(ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the
address of a memory operand. A 16-bit displacement is sign-extended when added.
4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn:
• Register indirect with post-increment—@ERn+
The register field of the instruction code specifies an address register (ERn) the lower 24 bits
of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is
added to the address register contents (32 bits) and the sum is stored in the address register.
The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or
longword access, the register value should be even.
• Register indirect with pre-decrement—@–ERn
The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field
in the instruction code, and the lower 24 bits of the result become the address of a memory
operand. The result is also stored in the address register. The value subtracted is 1 for byte
access, 2 for word access, or 4 for longword access. For word or longword access, the resulting
register value should be even.
5 Absolute Address—@aa:8, @aa:16, or @aa:24: The instruction code contains the absolute
address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long
(@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all
assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A
24-bit absolute address can access the entire address space. Table 2.10 indicates the accessible
address ranges.
Table 2.10 Absolute Address Access Ranges
Absolute Address Access Range
8 bits (@aa:8) H'FF00 to H'FFFF
16 bits (@aa:16) H'0000 to H'FFFF
24 bits (@aa:24) H'0000 to H'FFFF
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6 Immediate—#xx:8, #xx:16, or #xx:32: The instruction code contains 8-bit (#xx:8), 16-bit
(#xx:16), or 32-bit (#xx:32) immediate data as an operand.
The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data
implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate
data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data
specifying a vector address.
7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and
BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is signextended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The
PC value to which the displacement is added is the address of the first byte of the next instruction,
so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768
bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an
even number.
8 Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
instruction code contains an 8-bit absolute address specifying a memory operand. This memory
operand contains a branch address. The memory operand is accessed by longword access. The first
byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The
upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to
255 (H'0000 to H'00FF). Note that the first part of this range is also the exception vector area.
Specified by @aa:8
Dummy
Branch address
Figure 2.10 Memory-Indirect Branch Address Specification
2.6.2 Effective Address Calculation
Table 2.11 explains how an effective address (EA) is calculated in each addressing mode. In the
H8/3664 Series, the upper 8 bits of the calculated address are ignored in order to generate a 16-bit
effective address.
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Table 2.11 Effective Address Calculation
No.
Addressing Mode and
Instruction Format
Effective Address
Calculation Effective Address
1 Register direct (Rn)
op rm rn
2 Register indirect (@ERn)
rop
3 Register indirect with displacement
@(d:16, ERn)/@(d:24, ERn)
op r
disp
31 0
General register contents
31 0
General register contents
Operand is general
register contents
23
23 0
0
Sign extension disp
4 Register indirect with post-increment
or pre-decrement
Register indirect with post-increment
@ERn+
31 0
op
r
Register indirect with pre-decrement
@–ERn
31 0
General register contents
1, 2, or 4
General register contents
23
23 0
0
op
r
36
1, 2, or 4
1 for a byte operand, 2 for a word
operand, 4 for a longword operand
Page 53
Addressing Mode and
No.
Instruction Format
5 Absolute address
@aa:8
Effective Address
Calculation Effective Address
@aa:8
op abs
@aa:16
op
@aa:24
op
6 Immediate
#xx:8, #xx:16, or #xx:32
abs
abs
23
H'FFFF
23
Sign
exten-
sion
23
08 7
016 15
0
Operand is immediate
data
op
IMM
7 Program-counter relative
@(d:8, PC) or @(d:16, PC)
op disp
23
Sign
exten-
sion
PC contents
disp
0
23
0
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Addressing Mode and
No.
Instruction Format
8 Memory indirect @@aa:8
op abs
Effective Address
Calculation Effective Address
23 8 7
H'0000
15
Memory
contents
abs
0
0
0
H'00
Legend:
r, rm, rn: Register field
op: Operation field
disp: Displacement
IMM: Immediate data
abs: Absolute address
Note: In the H8/3664 Series, the upper 8 bits of the calculation result are ignored.
016 1523
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2.7 Basic Bus Cycle
CPU operation is synchronized by a system clock (ø) or a subclock (ø
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of ø or ø
). For details on these
SUB
SUB
to
the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.7.1 Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle
ø or ø
T1 state
SUB
T2 state
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
Figure 2.11 On-Chip Memory Access Cycle
Address
Read data
Write data
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2.7.2 Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits
or 16 bits depending on the register. For description on the data bus width of each register, refer to
appendix B, Internal I/O Registers. Registers with 16-bit data bus width can be accessed by word
size only. Registers with 8-bit data bus width can be accessed by byte or word size. When a
register with 8-bit data bus width is accessed by word size, access is completed in two cycles. In
two-state access, the operation timing is the same as that for on-chip memory.
Figure 2.12 shows the operation timing in the case of three-state access to an on-chip peripheral
module.
Bus cycle
ø or ø
Internal
address bus
Internal
read signal
Internal
data bus
(read access)
Internal
write signal
Internal
data bus
(write access)
SUB
T1 state
T2 state T3 state
Address
Read data
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (3-State Access)
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2.8 CPU States
2.8.1 Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active mode and subactive mode.
In the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states
are shown in figure 2.13. Figure 2.14 shows the state transitions. For details on program execution
state and program halt state, refer to section 6, Power-Down Modes. For details on exception
processing, refer to section 3, Exception Handling.
CPU state Reset state
The CPU is initialized
Program
execution state
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Exception-
handling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Sleep mode
Standby mode
Subsleep mode
Power-down
modes
Note: See section 6, Power-Down Modes, for details on the modes and their transitions.
Figure 2.13 CPU Operation States
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Reset state
Reset cleared
Exception-handling state
Reset occurs
Reset
occurs
Program halt state
Reset
occurs
SLEEP instruction executed
Interrupt
source
Program execution state
Interrupt
source
Exceptionhandling
complete
Figure 2.14 State Transitions
2.9 Application Notes
2.9.1 Notes on Data Access to Empty Areas
The address space of the H8/3664 Series CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an
application program, the following results will occur.
• Data transfer from CPU to empty area
The transferred data will be lost. This action may also cause the CPU to misoperate.
• Data transfer from empty area to CPU
Unpredictable data is transferred.
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2.9.2 Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation Operation
1 Read Read byte data at the designated address
2 Modify Modify a designated bit in the read data
3 Write Write the altered byte data to the designated address
Bit Manipulation in Two Registers Assigned to the Same Address
Example 1: Timer load register and timer counter (This applies to timers B and C. It does not
apply to the H8/3664 Series.)
Figure 2.15 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation Operation
1 Read Timer counter data is read (one byte)
2 Modify The CPU modifies (sets or resets) the designated bit in the instruction
3 Write The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.
R
Count clock Timer counter
Figure 2.15 Timer Configuration Example
Reload
Timer load register
R:W:Read
Write
W
Internal bus
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Example 2: BSET instruction executed designating port 5
P57 and P56 are designated as input pins, with a low-level signal input at P57 and a high-level
signal input at P56. The remaining pins, P55 to P50, are output pins and output low-level signals. In
this example, the BSET instruction is used to change pin P50 to high-level output.
[A: Prior to executing BSET]
P5
7
P5
6
P5
5
P5
4
P5
3
P5
2
P5
1
P5
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 00111111
PDR5 10000000
[B: BSET instruction executed]
BSET #0, @PDR5
The BSET instruction is executed designating port 5.
[C: After executing BSET]
P5
7
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
P5
6
High
level
P5
5
Low
level
P5
4
Low
level
P5
3
Low
level
P5
2
Low
level
P5
1
Low
level
P5
0
High
level
PCR5 00111111
PDR5 0 1000001
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 5.
Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input).
P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. Finally, the CPU
writes this value (H'41) to PDR5, completing execution of BSET.
As a result of this operation, bit 0 in PDR5 becomes 1, and P50 outputs a high-level signal.
However, bits 7 and 6 of PDR5 end up with different values.
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To avoid this problem, store a copy of the PDR5 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR5.
[A: Prior to executing BSET]
MOV.B #80, R0L
MOV.B R0L, @RAM0
The PDR5 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR5.
MOV.B R0L, @PDR5
P5
7
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000000
RAM0 10000000
P5
6
High
level
P5
5
Low
level
P5
4
Low
level
P5
3
Low
level
P5
2
Low
level
P5
1
Low
level
P5
0
Low
level
[B: BSET instruction executed]
BSET #0, @RAM0
The BSET instruction is executed designating the PDR5
work area (RAM0).
[C: After executing BSET]
MOV.B @RAM0, R0L
The work area (RAM0) value is written to PDR5.
MOV.B R0L, @PDR5
P5
7
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000001
RAM0 10000001
P5
6
High
level
P5
5
Low
level
P5
4
Low
level
P5
3
Low
level
P5
2
Low
level
P5
1
Low
level
P5
0
High
level
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Bit Manipulation in a Register Containing a Write-Only Bit
Example 3: BCLR instruction executed designating port 5 control register PCR5
As in the examples above, P57 and P56 are input pins, with a low-level signal input at P57 and a
high-level signal input at P56. The remaining pins, P55 to P50, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P50 to an input port. It is
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P5
7
P5
6
P5
5
P5
4
P5
3
P5
2
P5
1
P5
0
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR5 00111111
PDR5 10000000
[B: BCLR instruction executed]
BCLR #0, @PCR5
The BCLR instruction is executed designating PCR5.
[C: After executing BCLR]
P5
7
Input/output Output Output Output Output Output Output Output Input
Pin state Low
level
P5
6
High
level
P5
5
Low
level
P5
4
Low
level
P5
3
Low
level
P5
2
Low
level
P5
1
Low
level
P5
0
High
level
PCR5 1 1 111110
PDR5 10000000
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR5. Since PCR5 is a write-only
register, the CPU reads a value of H'FF, even though the PCR5 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR5 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR5 becomes 0, making P50 an input port. However, bits 7
and 6 in PCR5 change to 1, so that P57 and P56 change from input pins to output pins.
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To avoid this problem, store a copy of the PCR5 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR5.
[A: Prior to executing BCLR]
MOV.B #3F, R0L
MOV.B R0L, @RAM0
The PCR5 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR5.
MOV.B R0L, @PCR5
P5
7
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111111
PDR5 10000000
RAM0 00111111
P5
6
High
level
P5
5
Low
level
P5
4
Low
level
P5
3
Low
level
P5
2
Low
level
P5
1
Low
level
P5
0
Low
level
[B: BCLR instruction executed]
BCLR #0, @RAM0
The BCLR instruction is executed designating the PCR5
work area (RAM0).
[C: After executing BCLR]
MOV.B @RAM0, R0L
The work area (RAM0) value is written to PCR5.
MOV.B R0L, @PCR5
P5
7
Input/output Input Input Output Output Output Output Output Output
Pin state Low
level
PCR5 00111110
PDR5 10000000
RAM0 00111110
P5
6
High
level
P5
5
Low
level
P5
4
Low
level
P5
3
Low
level
P5
2
Low
level
P5
1
Low
level
P5
0
High
level
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2.9.3 Notes on Use of the EEPMOV Instruction
• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
→
R5
←
R6
R5 + R4L
→
←
R6 + R4L
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
→
R5
R5 + R4L
→
H'FFFF
Not allowed
←
R6
←
R6 + R4L
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Section 3 Exception Handling
3.1 Overview
3.1.1 Exception Handling Types
Exception handling is performed in the H8/3664 Series when a reset, interrupt, or trap instruction
occurs. Table 3.1 shows these three types of exception handling. A trap instruction can always be
accepted when the program is being executed.
Table 3.1 Exception Handling Types
Exception Source Time of Start of Exception Handling
Reset Exception handling starts as soon as the reset state is cleared
Interrupt When an interrupt is requested, exception handling starts after the present
instruction or the exception handling in progress is completed
Trap instruction Execution handling starts up when a TRAP instruction is executed
3.2 Reset
As soon as the RES pin is set to low, all processing is stopped and the chip enters the reset state.
The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by
the reset. To make sure the chip is reset properly, when turning the power on, the RES pin should
be held at low until the clock pulse generator output stabilizes. When resetting during operation,
the RES pin should be held at low for at least 10 system clock cycles. Reset exception handling
begins when the RES pin is held at low for a given period, then returned to the high level.
3.2.1 Reset Sequence
A reset is the highest-priority exception handling. The sequence of the reset exception handling
takes place as follows.
1. Set the I bit of the condition code register (CCR).
2. The CPU generates the reset exception handling vector address (H'0000 to H'0001), and
transfers the address to PC as a start address. Then a program starts executing from the
address indicated in PC. Figure 3.1 shows the reset sequence.
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3.2.2 Reset by Watchdog Timer
When the watchdog timer overflows, the chip enters the reset state and reset exception handling
begins. The same reset exception handling is carried out as for input at the RES pin. For details on
the watchdog timer, see section 13, Watchdog Timer.
3.2.3 Interrupt Immediately after Reset
After a reset, if the CPU was to accept an interrupt before the stack pointer (SP) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in control over the program
being lost. To prevent this, immediately after reset exception handling all interrupts including
NMI are masked. For this reason, the initial program instruction is always executed immediately
after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
Reset cleared
Initial program
Vector fetch
Internal
processing
instruction prefetch
RES
ø
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus (16 bits)
(1)
(2) (3)
(2)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) Initial program instruction
50
Figure 3.1 Reset Sequence
Page 67
3.3 Interrupts
3.3.1 Interrupt and Vector Address
The interrupt sources that start the interrupt exception handling include 11 external interrupts and
20 internal interrupts. Table 3.2 shows the interrupts, their priorities, and their vector addresses.
When more than one interrupt is requested, handling is performed from the interrupt with the
highest priority.
NMI is the highest-priority interrupt, and cannot be masked by the I bit in CCR. All other external
interrupts excluding NMI and internal interrupts excluding address break are masked by the I bit
in CCR, and kept masked while the I bit is set to 1.
Table 3.2 Interrupt Priorities and Their Vector Addresses
Interrupt Source Interrupt Vector Number Vector Address Priority
RES
Watchdog timer
(Reserved by (Reserved by system) 1 H'0002 to H'0003
system)
External pin NMI 7 H'000E to H'000F
Trap instruction Trap instruction #0 8 H'0010 to H'0011
executed
Address break Break conditions satisfied 12 H'0018 to H'0019
Sleep instruction
executed
Reset 0 H'0000 to H'0001 High
2 H'0004 to H'0005
3 H'0006 to H'0007
4 H'0008 to H'0009
5 H'000A to H'000B
6 H'000C to H'000D
Trap instruction #1 9 H'0012 to H'0013
Trap instruction #2 10 H'0014 to H'0015
Trap instruction #3 11 H'0016 to H'0017
Transferred directly 13 H'001A to H'001B
External pin IRQ0 14 H'001C to H'001D
IRQ1 15 H'001E to H'001F
IRQ2 16 H'0020 to H'0021
IRQ3 17 H'0022 to H'0023
WKP5 18 H'0024 to H'0025
Timer A Timer A overflow 19 H'0026 to H'0027 Low
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Interrupt Source Interrupt Vector Number Vector Address Priority
(Reserved by
(Reserved by system) 20 H'0028 to H'0029 High
system)
Timer W Input capture A / compare
match A
Input capture B / compare
match B
Input capture C / compare
match C
Input capture D / compare
match D
Timer W overflow
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
SCI3 SCI3 transmit end
SCI3 transmit data empty
21 H'002A to H'002B
22 H'002C to H'002D
23 H'002E to H'002F
SCI3 receive data full
SCI3 overrun error
SCI3 framing error
SCI3 parity error
IIC Data transfer end
24 H'0030 to H'0031
Address inequality
Stop conditions detected
A/D converter A/D conversion end 25 H'0032 to H'0033 Low
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3.4 Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3 Interrupt Control Registers
Name Abbreviation R/W Initial Value Address
Interrupt edge select register 1 IEGR1 R/W H'70 H'FFF2
Interrupt edge select register 2 IEGR2 R/W H'C0 H'FFF3
Interrupt enable register 1 IENR1 R/W H'10 H'FFF4
Interrupt flag register 1 IRR1 R/W* H'30 H'FFF6
Wakeup interrupt flag register IWPR R/W* H'C0 H'FFF8
Note: *Write is enabled only for writing of 0 to clear a flag.
3.4.1 Interrupt Edge Select Register 1 (IEGR1)
Bit 76543210
NMIEG — — — IEG3 IEG2 IEG1 IEG0
Initial value 01110000
Read/Write R/W — — — R/W R/W R/W R/W
IEGR1 is an 8-bit read/write register used to designate whether pins NMI and IRQ3 to IRQ0 are
set to rising edge sensing or falling edge sensing. Upon reset, IEGR1 is initialized to H'70.
Bit 7—NMI Edge Select (NMIEG): Bit 7 selects the input sensing of pin NMI.
Bit 7: NMIEG Description
0 Falling edge of NMI pin input is detected (initial value)
1 Rising edge of NMI pin input is detected
Bits 6 to 4—Reserved Bits: Bits 6 to 4 are reserved; they are always read as 1, and cannot be
modified.
Bit 3—IRQ3 Edge Select (IEG3): Bit 3 selects the input sensing of pin IRQ3.
Bit 3: IEG3 Description
0 Falling edge of IRQ3 pin input is detected (initial value)
1 Rising edge of IRQ3 pin input is detected
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Bit 2—IRQ2 Edge Select (IEG2): Bit 2 selects the input sensing of pin IRQ2.
Bit 2: IEG2 Description
0 Falling edge of IRQ2 pin input is detected (initial value)
1 Rising edge of IRQ2 pin input is detected
Bit 1—IRQ1 Edge Select (IEG1): Bit 1 selects the input sensing of pin IRQ1.
Bit 1: IEG1 Description
0 Falling edge of IRQ1 pin input is detected (initial value)
1 Rising edge of IRQ1 pin input is detected
Bit 0—IRQ0 Edge Select (IEG0): Bit 0 selects the input sensing of pin IRQ0.
Bit 0: IEG0 Description
0 Falling edge of IRQ0 pin input is detected (initial value)
1 Rising edge of IRQ0 pin input is detected
3.4.2 Interrupt Edge Select Register 2 (IEGR2)
Bit 76543210
— — WPEG5 WPEG4 WPEG3 WPEG2 WPEG1 WPEG0
Initial value 11000000
Read/Write — — R/W R/W R/W R/W R/W R/W
IEGR2 is an 8-bit read/write register used to designate whether pins WKP5 to WKP0 are set to
rising edge sensing or falling edge sensing. Upon reset, IEGR2 is initialized to H'C0.
Bits 7 and 6—Reserved Bits: Bits 7 and 6 are reserved; they are always read as 1, and cannot be
modified.
Bit 5—WKP5 Edge Select (WPEG5): Bit 5 selects the input sensing of pins WKP5 and ADTRG.
Bit 5: WPEG5 Description
0 Falling edge of WKP5 (ADTRG) pin input is detected (initial value)
1 Rising edge of WKP5 (ADTRG) pin input is detected
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Bits 4 to 0—WKP4 to WKP0 Edge Select (WPEG4 to WPEG0): Bits 4 to 0 select the input
sensing of pins WKP4 to WKP0.
Bit n: WPEGn Description
0 Falling edge of WKPn pin input is detected (initial value)
1 Rising edge of WKPn pin input is detected
(n = 4 to 0)
3.4.3 Interrupt Enable Register 1 (IENR1)
Bit 76543210
IENDT IENTA IENWP — IEN3 IEN2 IEN1 IEN0
Initial value 00010000
Read/Write R/W R/W R/W — R/W R/W R/W R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Upon reset, IENR1
is initialized to H'10.
Bit 7—Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer
interrupt requests.
Bit 7: IENDT Description
0 Disables direct transfer interrupt requests (initial value)
1 Enables direct transfer interrupt requests
Bit 6—Timer A Interrupt Enable (IENTA): Bit 6 enables or disables timer A overflow interrupt
requests.
Bit 6: IENTA Description
0 Disables timer A interrupt requests (initial value)
1 Enables timer A interrupt requests
Bit 5—Wakeup Interrupt Enable (IENWP): Bit 5 enables or disables WKP5 to WKP0 interrupt
requests.
Bit 5: IENWP Description
0 Disables interrupt requests from pins WKP5 to WKP0 (initial value)
1 Enables interrupt requests from pins WKP5 to WKP0
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Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—IRQ3 to IRQ0 Interrupt Enable (IEN3 to IEN0): Bits 3 to 0 enable or disable
IRQ3 to IRQ0 interrupt requests.
Bit n: IENn Description
0 Disables interrupt requests from pin IRQn (initial value)
1 Enables interrupt requests from pin IRQn
(n = 3 to 0)
3.4.4 Interrupt Flag Register 1 (IRR1)
Bit 76543210
IRRDT IRRTA — — IRRI3 IRRI2 IRRI1 IRRI0
Initial value 00110000
Read/Write R/W R/W — — R/W R/W R/W R/W
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, a timer A, or IRQ3 to IRQ0 interrupt is requested. The flags are not cleared automatically
when an interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IRR1 is
initialized to H'30.
Bit 7—Direct Transfer Interrupt Request Flag (IRRDT)
Bit 7: IRRDT Description
0 Clearing conditions: (initial value)
When IRRDT = 1, it is cleared by writing 0
1 Setting conditions:
When a direct transfer is made by executing a SLEEP instruction while DTON
= 1 in SYSCR2
Bit 6—Timer A Interrupt Request Flag (IRRTA)
Bit 6: IRRTA Description
0 Clearing conditions: (initial value)
When IRRTA = 1, it is cleared by writing 0
1 Setting conditions:
When the timer A counter value overflows from H'FF to H'00
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Bits 5 and 4—Reserved Bits: Bits 5 and 4 are reserved: they are always read as 1 and cannot be
modified.
Bit 4—Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified.
Bits 3 to 0—IRQ3 to IRQ0 Interrupt Request Flags (IRRI3 to IRRI0)
Bit n: IRRIn Description
0 Clearing conditions: (initial value)
When IRRIn = 1, it is cleared by writing 0
1 Setting conditions:
When pin IRQ
is input
is designated for interrupt input and the designated signal edge
n
(n = 3 to 0)
3.4.5 Wakeup Interrupt Flag Register (IWPR)
Bit 76543210
— — IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0
Initial value 11000000
Read/Write — — R/W R/W R/W R/W R/W R/W
IWPR is an 8-bit read/write register, in which a corresponding flag is set to 1 when the designated
signal edge is input at pin WKP5 to WKP0. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag. Upon reset, IWPR is initialized to
H'C0.
Bits 7 and 6— Bits 7 and 6 are reserved; they are always read as 1, and cannot be modified.
Bits 5 to 0—WKP5 to WKP0 Interrupt Request Flags (IWPF5 to IWPF0)
Bit n: IWPFn Description
0 Clearing conditions: (initial value)
When IWPFn = 1, it is cleared by writing 0
1 Setting conditions:
When pin WKPn is designated for interrupt input and the designated signal
edge is input
(n = 5 to 0)
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3.5 Interrupt Sources
3.5.1 External Interrupts
There are 11 external interrupts: NMI, IRQ3 to IRQ0, and WKP5 to WKP0.
• NMI Interrupt
NMI interrupt is requested by input signal to pin NMI. This interrupt is detected by either
rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1.
NMI is the highest-priority interrupt, and can always be accepted without depending on the I
bit value in CCR. When NMI interrupt exception handling is accepted, the I bit is set to 1 in
CCR.
• IRQ3 to IRQ0 Interrupts
IRQ3 to IRQ0 interrupts are requested by input signals to pins IRQ3 to IRQ0. These four
interrupts are given different vector addresses, and are detected individually by either rising
edge sensing or falling edge sensing, depending on the settings of bits IEG3 to IEG0 in IEGR1.
When pins IRQ3 to IRQ0 are designated for interrupt input in PMR1 and the designated signal
edge is input, the corresponding bit in IRR1 is set to 1, requesting the CPU of an interrupt.
When IRQ3 to IRQ0 interrupt is accepted, the I bit is set to 1 in CCR. These interrupts can be
masked by setting bits IEN3 to IEN0 in IENR1.
• WKP5 to WKP0 Interrupts
WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six
interrupts have the same vector addresses, and are detected individually by either rising edge
sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in
IEGR2.
When pins WKP5 to WKP0 are designated for interrupt input in PMR5 and the designated
signal edge is input, the corresponding bit in IWPR is set to 1, requesting the CPU of an
interrupt. When a WKP5 to WKP0 interrupt is accepted, the I bit is set to 1 in CCR. These
interrupts can be masked by setting bit IENWP in IENR1.
3.5.2 Internal Interrupts
There are 20 internal interrupts that can be requested by the on-chip peripheral modules. Each onchip peripheral module has a flag to show the interrupt request status and the enable bit to enable
or disable the interrupt. For timer A interrupt requests and direct transfer interrupt requests
generated by execution of a SLEEP instruction, this function is included in IRR1 and IENR1.
Table 3.2 shows the order of priority of interrupts and their vector addresses.
When an on-chip peripheral module requests an interrupt, the corresponding interrupt request
status flag is set to 1, requesting the CPU of an interrupt. When this interrupt is accepted, the I bit
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is set to 1 in CCR. These interrupts can be masked by writing 0 to clear the corresponding enable
bit.
3.5.3 Interrupt Operations
Interrupts are controlled by an interrupt controller.
Interrupt operation is described as follows.
1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request
signal is sent to the interrupt controller.
2. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to
table 3.2 for a list of interrupt priorities.)
3. The CPU accepts the NMI and address break without depending on the I bit value. Other
interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the
interrupt request is held pending.
4. If the CPU accepts the interrupt after processing of the current instruction is completed,
interrupt exception handling will begin. First, both PC and CCR are pushed onto the stack. The
state of the stack at this time is shown in figure 3.2. The PC value pushed onto the stack is the
address of the first instruction to be executed upon return from interrupt handling.
5. Then, the I bit of CCR is set to 1, masking further interrupts excluding the NMI and address
break. Upon return from interrupt handling, the values of I bit and other bits in CCR will be
restored and returned to the values prior to the start of interrupt exception handling.
6. Next, the CPU generates the vector address corresponding to the accepted interrupt, and
transfers the address to PC as a start address of the interrupt handling-routine. Then a program
starts executing from the address indicated in PC.
Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and
the stack area is in the on-chip RAM.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt flag register, always do so while interrupts are masked (I =
1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception handling for the
interrupt will be executed after the clear instruction has been executed.
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SP – 4
SP (R7)
CCR
SP – 3
SP – 2
SP – 1
SP (R7)
Notation:
PC
:
H
PC
:
L
CCR:
SP:
Notes:
SP + 1
SP + 2
SP + 3
SP + 4
CCR
PC
PC
*3
H
L
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
After completion of interrupt
exception handling
saved to stack
Upper 8 bits of program counter (PC)
Lower 8 bits of program counter (PC)
Condition code register
Stack pointer
1.2.PC shows the address of the first instruction to be executed upon return from the interrupt
handling routine.
Register contents must always be saved and restored by word length, starting from
an even-numbered address.
3. Ignored when returning from the interrupt handling routine.
Figure 3.2 Stack State after Completion of Interrupt Exception Handling
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Prefetch instruction of
interrupt-handling routine
Internal
processing
Vector fetch
Stack access
(9)
Instruction
Interrupt is
accepted
Interrupt level
decision and wait for
Internal
processing
prefetch
end of instruction
Interrupt
request signal
(3) (9)(8)(6)(5)
(4) (1) (7) (10)
(2)
(1)
ø
Internal
address bus
Internal read
signal
Internal write
signal
Internal data bus
Figure 3.3 Interrupt Sequence
(16 bits)
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
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3.5.4 Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handling-routine is executed.
Table 3.4 Interrupt Wait States
Item States
Waiting time for completion of executing instruction* 1 to 13
Saving of PC and CCR to stack 4
Vector fetch 2
Instruction fetch 4
Internal processing 4
Total 15 to 27
Note: * Not including EEPMOV instruction.
3.6 Trap Instruction
When a TRAP instruction is executed, trap instruction exception handling starts up. A TRAP
instruction generates vector addresses corresponding to the vector numbers 0 to 3 designated in the
instruction code.
3.7 Application Notes
3.7.1 Notes on Stack Area Use
When word data is accessed in the H8/3664 Series, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.4.
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SP
→
SP
→
PC
H
PC
L
SP
→
R1L
PC
H'FEFC
L
H'FEFD
H'FEFF
BSR instruction
SP set to H'FEFF Stack accessed beyond SP
MOV. B R1L, @–R7
Contents of PC are lost
H
Notation:
PC
:
Upper byte of program counter
H
PC
:
Lower byte of program counter
L
R1L:
SP:
General register R1L
Stack pointer
Figure 3.4 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
3.7.2 Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQ3 to IRQ1, and WKP5 to WKP0, the interrupt request flag may be set to 1 at the
time the pin function is switched, even if no valid interrupt is input at the pin. Table 3.5 shows the
conditions under which interrupt request flags are set to 1 in this way.
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Table 3.5 Conditions under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1 Conditions
IRR1 IRRI3 When bit IRQ3 in PMR1 is changed from 0 to 1 while pin IRQ3 is low and bit IEG3 in
IEGR1 = 0.
When bit IRQ3 in PMR1 is changed from 1 to 0 while pin IRQ3 is low and bit IEG3 in
IEGR1 = 1.
IRRI2 When bit IRQ2 in PMR1 is changed from 0 to 1 while pin IRQ2 is low and bit IEG2 in
IEGR1 = 0.
When bit IRQ2 in PMR1 is changed from 1 to 0 while pin IRQ2 is low and bit IEG2 in
IEGR1 = 1.
IRRI1 When bit IRQ1 in PMR1 is changed from 0 to 1 while pin IRQ1 is low and bit IEG1 in
IEGR1 = 0.
When bit IRQ1 in PMR1 is changed from 1 to 0 while pin IRQ1 is low and bit IEG1 in
IEGR1 = 1.
IRRI0 When bit IRQ0 in PMR1 is changed from 0 to 1 while pin IRQ0 is low and bit IEG0 in
IEGR1 = 0.
When bit IRQ0 in PMR1 is changed from 1 to 0 while pin IRQ0 is low and bit IEG0 in
IEGR1 = 1.
IWPR IWPF5 When bit WKP5 in PMR5 is changed from 0 to 1 while pin WKP5 is low and bit
WPEG5 in IEGR2 = 0.
When bit WKP5 in PMR5 is changed from 1 to 0 while pin WKP5 is low and bit
WPEG5 in IEGR2 = 1.
IWPF4 When bit WKP4 in PMR5 is changed from 0 to 1 while pin WKP4 is low and bit
WPEG4 in IEGR2 = 0.
When bit WKP4 in PMR5 is changed from 1 to 0 while pin WKP4 is low and bit
WPEG4 in IEGR2 = 1.
IWPF3 When bit WKP3 in PMR5 is changed from 0 to 1 while pin WKP3 is low and bit
WPEG3 in IEGR2 = 0.
When bit WKP3 in PMR5 is changed from 1 to 0 while pin WKP3 is low and bit
WPEG3 in IEGR2 = 1.
IWPF2 When bit WKP2 in PMR5 is changed from 0 to 1 while pin WKP2 is low and bit
WPEG2 in IEGR2 = 0.
When bit WKP2 in PMR5 is changed from 1 to 0 while pin WKP2 is low and bit
WPEG2 in IEGR2 = 1.
IWPF1 When bit WKP1 in PMR5 is changed from 0 to 1 while pin WKP1 is low and bit
WPEG1 in IEGR2 = 0.
When bit WKP1 in PMR5 is changed from 1 to 0 while pin WKP1 is low and bit
WPEG1 in IEGR2 = 1.
IWPF0 When bit WKP0 in PMR5 is changed from 0 to 1 while pin WKP0 is low and bit
WPEG0 in IEGR2 = 0.
When bit WKP0 in PMR5 is changed from 1 to 0 while pin WKP0 is low and bit
WPEG0 in IEGR2 = 1.
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Figure 3.5 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.
An alternative method to avoid the setting of interrupt request flags when pin functions are
switched is to keep the pins at the high level so that the conditions in table 3.5 do not occur.
Interrupts masked. (Another possibility
CCR I bit 1
Set port mode register bit
←
is to disable the relevant interrupt in
interrupt enable register 1.)
Execute NOP instruction
Clear interrupt request flag to 0
CCR I bit 0
←
Figure 3.5 Port Mode Register Setting and Interrupt Request Flag
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Interrupt mask cleared
Clearing Procedure
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Section 4 Address Break
4.1 Overview
The address break simplifies on-board program debugging. It requests an address break interrupt
when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR.
Break conditions that can be set include instruction execution at a specific address and a
combination of access and data at a specific address. With the address break function, the
execution start point of a program containing a bug is detected and execution is branched to the
correcting program.
4.1.1 Block Diagram
Figure 4.1 shows a block diagram of the address break.
Internal address bus
Interrupt
generation
control circuit
Notation:
BARH, BARL: Break address register
BDRH, BDRL: Break data register
ABRKCR: Address break control register
ABRKSR: Address break status register
Comparator
BARH BARL
ABRKCR
ABRKSR
Internal data bus
BDRH BDRL
Comparator
Interrupt
Figure 4.1 Block Diagram of an Address Break
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4.1.2 Register Configuration
Table 4.1 shows the address break register configuration.
Table 4.1 Address Break Registers
Name Abbrev. R/W Initial Value Address
Address break control register ABRKCR R/W H'80 H'FFC8
Address break status register ABRKSR R/W H'3F H'FFC9
Break address register (H) BARH R/W H'FF H'FFCA
Break address register (L) BARL R/W H'FF H'FFCB
Break data register (H) BDRH R/W Undefined H'FFCC
Break data register (L) BDRL R/W Undefined H'FFCD
4.2 Register Descriptions
4.2.1 Address Break Control Register (ABRKCR)
Bit 76543210
RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0
Initial value 10000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
ABRKCR is an 8-bit read/write register that sets address break conditions.
Bit 7—RTE Interrupt Enable (RTINTE): Bit 7 enables or disables an interrupt after RTE
instruction execution.
Bit 7: RTINTE Description
0 Disables an interrupt after RTE instruction execution (one instruction is
executed)
1 Enables an interrupt after RTE instruction execution (Initial value)
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Bits 6 and 5—Condition Select (CSEL1, CSEL0): Bits 6 and 5 set address break conditions.
When CSEL1=0 and CSEL0=0, data is not compared regardless of the values of DCMP1 and
DCMP0.
Bit 6: CSEL1 Bit 5: CSEL0 Description
0 0 Instruction execution cycle (Initial value)
1 CPU data read cycle
1 0 CPU data write cycle
1 CPU data read/write cycle
Bits 4 to 2—Address Compare Condition Select (ACMP2 to ACMP0): Bits 4 to 2 set
comparison condition between the address set in BAR and the internal address bus.
Bit 4:
ACMP2
0 0 0 Compare 16-bit addresses (Initial value)
1 **Reserved
Note: * Don’t care.
Bit 3:
ACMP1
1 0 Compares upper 8-bit addresses
Bit 2:
ACMP0 Description
1 Compares upper 12-bit addresses
1 Compares upper 4-bit addresses
Bits 1 and 0—Data Compare Condition Select (DCMP1, DCMP0): Bits 1 and 0 set the
comparison condition between the data set in BDR and the internal data bus.
Bit 1: DCMP1 Bit 0: DCMP0 Description
0 0 No data comparison (Initial value)
1 Compares lower 8-bit data between BDRL and data bus
1 0 Compares upper 8-bit data between BDRH and data bus
1 Compares 16-bit data between BDR and data bus
When an address break is set in the data read cycle or data write cycle, the data bus used will
depend on the combination of the byte/word access and address. Table 4.2 shows the access and
data bus used.
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Table 4.2 Access and Data Bus Used
Word Access Byte Access
Even Address Odd Address Even Address Odd Address
ROM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
RAM space Upper 8 bits Lower 8 bits Upper 8 bits Upper 8 bits
I/O register space
(except H'FF86 to H'FF8F)
I/O register space
(H'FF86 to H'FF8F)
Note: * When the I/O register space, except H'FF86 to H'FF8F, is accessed by word, byte access
occurs twice.
Upper 8 bits* Upper 8 bits* Upper 8 bits Upper 8 bits
Upper 8 bits Lower 8 bits — —
4.2.2 Address Break Status Register (ABRKSR)
Bit 76543210
ABIF ABIE ——————
Initial value 00111111
Read/Write R/W R/W ——————
ABRKSR is an 8-bit read/write register that consists of the address break interrupt flag and the
address break interrupt enable bit.
Bit 7—Address Break Interrupt Flag (ABIF): Bit 7 indicates an address break interrupt.
Bit 7: ABIF Description
0 An address break interrupt request is not generated
[Clearing condition]
When 0 is written after ABIF=1 is read (Initial value)
1 An address break interrupt request is generated
[Set condition]
When the condition set in ABRKCR is satisfied
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Bit 6—Address Break Interrupt Enable (ABIE): Bit 6 enables or disables an address break
interrupt.
Bit 6: ABIE Description
0 Disables an address break interrupt request (Initial value)
1 Enables an address break interrupt request
Bits 5 to 0—Reserved Bits: Bits 5 to 0 are reserved; they are always read as 1 and cannot be
modified.
4.2.3 Break Address Registers (BARH, BARL)
Bit 76543210
BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0
Initial value 11111111
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 76543210
BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0
Initial value 11111111
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
BAR (BARH, BARL) is a 16-bit read/write register that sets the address for generating an address
break interrupt. When setting the address break condition to the instruction execution cycle, set
the first byte address of the instruction.
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4.2.4 Break Data Registers (BDRH, BDRL)
Bit 76543210
BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0
Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 76543210
BDRL7 BDRL6 BDRL5 BDRL4 BDRL3 BDRL2 BDRL1 BDRL0
Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
BDR (BDRH, BDRL) is a 16-bit read/write register that sets the data for generating an address
break interrupt. BDRH is compared with the upper 8-bit data bus. BDRL is compared with the
lower 8-bit data bus. When memory or registers are accessed by byte, the upper 8-bit data bus is
used for even and odd addresses in the data transmission. Therefore, comparison data must be set
in BDRH for byte access. For word access, the data bus used depends on the address. See section
4.2.1, Address Break Control Register, for details.
4.3 Operation
When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the
combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR,
the address break function generates an interrupt request to the CPU. When the interrupt request
is accepted, interrupt exception handling starts after the instruction being executed ends. The
address break interrupt is not masked because of the I bit in CCR of the CPU.
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Figures 4.2 to 4.4 show the operation examples of the address break interrupt setting.
When the address break is specified in instruction execution cycle
Register setting
• ABRKCR = H'80
• BAR = H'025A
NOP
instruc-
tion
prefetch
φ
Address
bus
Interrupt
request
0258
Figure 4.2 Address Break Interrupt Operation Example (1)
Program
0258
025A
*
025C
0260
0262
:
NOP
instruc-
tion
prefetch
025A 025C 025E SP-2 SP-4
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
MOV
instruc-
tion 1
prefetch
Interrupt acceptance
MOV
instruc-
tion 2
prefetch
Underline indicates the address
to be stacked.
Internal
processing Stack save
When the address break is specified in the data read cycle
Register setting
• ABRKCR = H'A0
• BAR = H'025A
MOV
instruc-
tion 1
prefetch
φ
Address
bus
Interrupt
request
025C
Program
0258
025A
025C
*
0260
0262
:
MOV
instruc-
tion 2
prefetch
025E 0260 025A 0262 0264 SP-2
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
NOP
instruc-
tion
prefetch
MOV
instruc-
tion
execution
Underline indicates the address
to be stacked.
NOP
instruc-
tion
prefetch
Interrupt acceptance
Next
instru-
ction
prefetch
Internal
processing
Stack
save
Figure 4.3 Address Break Interrupt Operation Example (2)
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When the interrupt acceptance is prohibited after the RTE (RTB) instruction
Register setting
• ABRKCR = H'10
Interrupt
Interrupt
RTE
instruc-
tion
prefetch
φ
Address
bus
Interrupt
request
039C
MOV
instruc-
tion
execution
Program
0258
025A
025C
0260
0262
:
NOP
instruc-
tion
prefetch
039E SP SP+2 025C 025E
NOP
instruc-
tion
prefetch
NOP
NOP
MOV.W @H'025A,R0
NOP
NOP
:
Stack
resumption
Internal
processing
Internal
processing
:
039A
039C
039E
:
MOV
instruc-
tion 1
prefetch
Vector
fetch
Underline indicates the
address to be stacked.
:
NOP
RTE
NOP
:
instruc-
prefetch
Internal
processingStack restore
MOV
tion 2
Interrupt request
is prohibited
NOP
instruc-
tion
prefetch
0260
Continues
to the
lower
φ
Address
bus
Interrupt
request
025A
Interrupt acceptance
0262 SP-2 SP-4 XXXX
Figure 4.4 Address Break Interrupt Operation Example (3)
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Section 5 Clock Pulse Generators
5.1 Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
5.1.1 Block Diagram
Figure 5.1 shows a block diagram of the clock pulse generators.
ø
OSC
ø
OSC
OSC
ø
ø
ø
OSC
OSC
OSC
OSC
/8
/16
/32
/64
)
System
clock
divider
1
2
System
clock
oscillator
System clock pulse generator
ø
(f
OSC
OSC
)
Duty
correction
circuit
ø
(f
OSC
OSC
ø
Prescaler S
(13 bits)
ø/2
to
ø/8192
ø
/2
X
1
X
2
Subclock
oscillator
Subclock pulse generator
ø
W
)
(f
W
Subclock
divider
W
ø
/4
W
/8
ø
W
ø
SUB
Prescaler W
(5 bits)
/8
ø
W
to
øW/128
Figure 5.1 Block Diagram of Clock Pulse Generators
5.1.2 System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are ø and ø
the clock signals have names: ø is the system clock, ø
is the subclock, ø
SUB
is the oscillator
OSC
. Four of
SUB
clock, and øW is the watch clock.
The clock signals available for use by peripheral modules are ø/2, ø/4, ø/8, ø/16, ø/32, ø/64, ø/128,
ø/256, ø/512, ø/1024, ø/2048, ø/4096, ø/8192, øW/8, øW/16, øW/32, øW/64, and øW/128. The clock
requirements differ from one module to another.
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5.2 System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.
Connecting a Crystal Oscillator: Figure 5.2 shows a typical method of connecting a crystal
oscillator. An AT-cut parallel-resonance crystal resonator should be used.
C
1
OSC
1
OSC
2
C
2
Figure 5.2 Typical Connection to Crystal Oscillator
Figure 5.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the
C = C = 12 pF ±20%
12
characteristics given in table 5.1 should be used.
C
S
OSC
L
S
1
C
0
R
S
OSC
2
Figure 5.3 Equivalent Circuit of Crystal Oscillator
Table 5.1 Crystal Oscillator Parameters
Frequency 2 MHz 4 MHz 8 MHz 10 MHz 16 MHz
RS (max) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω
C0 (max) 7 pF 7 pF 7 pF 7 pF 7 pF
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Connecting a Ceramic Oscillator: Figure 5.4 shows a typical method of connecting a ceramic
oscillator.
C
1
OSC
1
C
2
OSC
2
C1 = 30 pF ±10%
C
= 30 pF ±10%
2
Figure 5.4 Typical Connection to Ceramic Oscillator
Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic
oscillator, pay careful attention to the following points.
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 5.5.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.
To be avoided
C
C
2
1
Signal A
Signal B
OSC
OSC
1
2
Figure 5.5 Board Design of Oscillator Circuit
External Clock Input Method: Connect an external clock signal to pin OSC1, and leave pin
OSC2 open. Figure 5.6 shows a typical connection. The duty cycle of the external clock signal
must be 45 to 55%.
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OSC
1
External clock input
OSC
2
Open
Figure 5.6 Example of External Clock Input
5.3 Subclock Generator
Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock
divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 5.7. Follow the same
precautions as noted under 5.2 Notes on Board Design.
C
1
X
1
X
2
C
2
C = C = 15 pF (typ.)
12
Figure 5.7 Typical Connection to 32.768-kHz Crystal Oscillator
Figure 5.8 shows the equivalent circuit of the 32.768-kHz crystal oscillator.
L
S
X
1
CO = 1.5 pF (typ.)
R
= 14 kΩ (typ.)
S
f
= 32.768 kHz
W
Note: Constants are reference values.
C
S
C
O
R
S
Figure 5.8 Equivalent Circuit of 32.768-kHz Crystal Oscillator
X
2
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Page 95
Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X1 to
VCL or VSS and leave pin X2 open, as shown in figure 5.9.
V
or V
CL
X
1
SS
X
2
Open
Figure 5.9 Pin Connection when not Using Subclock
5.4 Prescalers
This LSI is equipped with two on-chip prescalers having different input clocks (prescaler S and
prescaler W). Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. Its
prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a
5-bit counter using a 32.768-kHz signal divided by 4 (øW/4) as its input clock. Its prescaled
outputs are used by timer A as a time base for timekeeping.
Prescaler S (PSS): Prescaler S is a 13-bit counter using the system clock (ø) as its input clock. It
is incremented once per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, subactive mode, and subsleep mode, the system clock pulse generator stops.
Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be
set separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is determined by the division factor
designated by MA1 and MA0 in SYSCR1.
Prescaler W (PSW): Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (øW/4)
as its input clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, subactive mode, or subsleep mode, prescaler W continues functioning so
long as clock signals are supplied to pins X1 and X2.
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Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
5.5 Usage Notes
5.5.1 Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user, referring to the examples shown in this section. Oscillator circuit constants will differ
depending on the oscillator element, stray capacitance in its interconnecting circuit, and other
factors. Suitable constants should be determined in consultation with the oscillator element
manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding
its maximum rating.
5.5.2 Notes on Board Design
When using a crystal resonator (ceramic resonator), place the resonator and its load capacitors as
close as possible to the OSC1 and OSC2 pins. Other signal lines should be routed away from the
oscillator circuit to prevent induction from interfering with correct oscillation (see figure 5.10).
Signal A Signal BAvoid
C
1
OSC
1
C
2
OSC
2
Figure 5.10 Example of Incorrect Board Design
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Page 97
Section 6 Power-down Modes
6.1 Overview
This LSI has six modes of operation after a reset. These include a normal active mode and four
power-down modes, in which power dissipation is significantly reduced. The module standby
mode reduces power dissipation by selectively halting on-chip module functions. Table 6.1
summarizes the six operating modes.
Table 6.1 Operating Modes
Operating Mode Description
Active mode The CPU and all on-chip peripheral modules are operable on
the system clock. The system clock frequency can be selected
from øosc, øosc/8, øosc/16, øosc/32, and øosc/64. For details,
see 6.2.2, System Control Register 2.
Subactive mode The CPU and all on-chip peripheral modules are operable on
the subclock. The subclock frequency can be selected from
øw/2, øw/4, and øw/8.
Sleep mode The CPU halts. On-chip peripheral functions are operable on
the system clock.
Subsleep mode The CPU halts. On-chip peripheral functions are operable on
the subclock.
Standby mode The CPU and all on-chip peripheral modules halt. When the
clock time-base function is selcted, timer A is operable.
Module standby mode The on-chip peripheral modules specified by software stop
operating. For details, see 6.2.3, Module Standby Control
Register 1.
6.1.1 Register Configuration
Table 6.2 shows the power-down mode register configuration.
Table 6.2 Power-down Mode Registers
Name Abbreviation R/W Initial Value Address
System control register 1 SYSCR1 R/W H'00 H'FFF0
System control register 2 SYSCR2 R/W H'00 H'FFF1
Module standby control
register 1
MSTCR1 R/W H'00 H'FFF9
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6.2 Register Descriptions
6.2.1 System Control Register 1 (SYSCR1)
Bit 76543210
SSBY STS2 STS1 STS0 NESEL — — —
Initial value 00000000
Read/Write R/W R/W R/W R/W R/W — — —
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'00.
Bit 7—Software Standby (SSBY): This bit designates the transition to the sleep mode, subsleep
mode, or standby mode.
Bit 7: SSBY Description
0 When a SLEEP instruction is executed in the active mode, a transition is made
to the sleep mode or subsleep mode. (Initial value)
1 When a SLEEP instruction is executed in the active mode, a transition is made
to the standby mode.
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the
CPU and peripheral modules wait for stable clock operation after exiting from the standby mode,
subactive mode, or subsleep mode to the active mode or sleep mode due to an interrupt. The
designation should be made according to the clock frequency so that the waiting time is at least 10
ms.
Bit 6: STS2 Bit 5: STS1 Bit 4: STS0 Description
0 0 0 Wait time = 8,192 states (Initial value)
1 Wait time = 16,384 states
1 0 Wait time = 32,768 states
1 Wait time = 65,536 states
1 0 0 Wait time = 131,072 states
1 0 Wait time = 128 states
82
1 Wait time = 1,024 states
1 Wait time = 16 states
Page 99
Bit 3—Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency
at which the watch clock signal (øW) generated by the subclock pulse generator is sampled, in
relation to the oscillator clock (ø
) generated by the system clock pulse generator. When ø
OSC
OSC
= 2
to 10 MHz, clear NESEL to 0.
Bit 3: NESEL Description
0 Sampling rate is ø
1 Sampling rate is ø
/16 (Initial value)
OSC
/4
OSC
Bits 2 to 0—Reserved Bits: Bits 2 to 0 are reserved: they are always read as 0 and cannot be
modified.
6.2.2 System Control Register 2 (SYSCR2)
Bit 76543210
SMSEL LSON DTON MA2 MA1 MA0 SA1 SA0
Initial value 00000000
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Upon reset, SYSCR2 is initialized to H'00.
Bit 7—Sleep Mode Selection (SMSEL): This bit chooses the transition to the sleep mode or
subsleep mode when the SLEEP instruction is executed. The transition after the SLEEP instruction
is executed depends on a combination of this and other control bits.
Bit 7: SMSEL Description
0 A transition is made to sleep mode. (Initial value)
1 A transition is made to subsleep mode.
Bit 6—Low Speed on Flag (LSON): This bit chooses the system clock (ø) or subclock (ø
SUB
) as
the CPU operating clock. The resulting operation mode after the SLEEP instruction is executed
depends on the combination of other control bits.
Bit 6: LSON Description
0 The CPU operates on the system clock (ø) (Initial value)
1 The CPU operates on the subclock (ø
SUB
)
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Bit 5—Direct Transfer on Flag (DTON): This bit designates whether to make direct transitions
between the active and subactive modes when a SLEEP instruction is executed. The mode to
which the transition is made after the SLEEP instruction is executed depends on a combination of
this and other control bits.
Bit 5: DTON Description
0 When a SLEEP instruction is executed, a transition is made to standby mode,
sleep mode, or subsleep mode. (Initial value)
1 When a SLEEP instruction is executed, a direct transition is made to active
mode if LSON = 0, or to subactive mode if LSON = 1.
Bits 4 to 2—Active Mode Clock Select (MA2 to MA0): These bits select the operating clock
frequency in the active and sleep modes. The operating clock frequency changes to the set
frequency after the SLEEP instruction is executed.
Bit 4: MA2 Bit 3: MA1 Bit 2: MA0 Description
0 **ø
100ø
1ø
10ø
1ø
osc
osc
osc
osc
osc
/8
/16
/32
/64
(Initial value)
Note: * Don’t care
Bits 1 and 0— Subactive Mode Clock Select (SA1, SA0): These bits select the operating clock
frequency in the subactive and subsleep modes. The operating clock frequency changes to the set
frequency after the SLEEP instruction is executed.
Bit 1: SA1 Bit 0: SA0 Description
00ø
1ø
1 * øW/2
Note: * Don’t care
/8 (Initial value)
W
/4
W
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