Hitachi HD6433060, HD6433064B, HD6433062B, HD6433061B, HD6433060B Hardware Manual

...

Page 1

To all our customers

Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp. Customer Support Dept. April 1, 2003

Page 2

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliabl e, but there is always the possibility that trouble may occur with them. Trouble with semicondu ctors may lead to personal injury , fire or propert y da mage. Remember to give due consideration to safety when making your circuit designs, with appropriate measu res such as (i) placement of substitutive, auxiliar y circuits, (ii) use of nonflammable material or (iii) preve n tion ag ain st any malf u nc tio n or mishap.

Notes regar ding these ma terials

1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.

2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party 's rights, originating in th e u se of any product data, diagrams, charts, programs, algorithms, or circuit applicatio n examples contained in these materials.

3. All information contained in these materials, including product data, diag rams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product informati o n be fore purcha si ng a product lis ted herein. The informa tion described here may contain technic a l inaccuracie s or typograph ical errors. Renesas Technology Corp oration assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas .com).

4. When usi ng any or all of the inf ormation contained in thes e m aterials, inc l ud i ng product data, diagrams, ch ar t s , programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibi lity for any damage, liability or other loss resulting from th e information contained herein.

5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Te chnology Corporation product dis tributor when considering the use of a product contained herein for any specific purposes, such as apparat us or system s for tra nsp or ta tio n, veh icul ar, medica l, aer o space, nucle ar, or unders ea repeater use.

6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.

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8. Please contact Renesas Technology Corporation for further details on these materials or the products contained the rein.

Page 3

Hitachi Single-Chip Microcomputer

The revision list can be viewed directly by  clicking the title page.  The revision list summarizes the locations of  revisions and additions. Details should always  be checked by referring to the relevant text.

H8/3062 Series

H8/3062 HD6433062 H8/3061 HD6433061 H8/3060 HD6433060

H8/3062B Series

H8/3064B HD6433064B H8/3062B HD6433062B H8/3061B HD6433061B H8/3060B HD6433060B

H8/3062F-ZTAT™

HD64F3062, HD64F3062R, HD64F3062B

H8/3064F-ZTAT™

HD64F3064B

Hardware Manual

ADE-602-136D Rev. 5.0 3/18/03 Hitachi, Ltd.

Page 4

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products.

Page 5

Preface

The H8/3062 Series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core.

The on-chip peripheral functions include ROM, RAM, 16-bit timers, 8-bit timers, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), a D/A converter, an A/D converter, and I/O ports, providing an ideal configuration as a microcomputer for embedding in sophisticated control systems. Flash memory (F-ZTAT™*) and mask ROM are available as on-chip ROM, enabling users to respond quickly and flexibly to changing application specifications and the demands of the transition from initial to full-fledged volume production.

Note: * F-ZTAT is a trademark of Hitachi, Ltd.

Intended Readership: This manual is intended for users undertaking the design of an application

system using the H8/3062 Series. Readers using this manual require a basic knowledge of electrical circuits, logic circuits, and microcomputers.

Purpose: The purpose of this manual is to give users an understanding of the hardware

functions and electrical characteristics of the H8/3062 Series. Details of execution instructions can be found in the H8/300H Series Programming Manual, which should be read in conjunction with the present manual.

Using this Manual:

• For an overall understanding of the H8/3062 Series's functions

Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system control functions, peripheral functions, and electrical characteristics.

• For a detailed understanding of CPU functions

Refer to the separate publication H8/300H Series Programming Manual.

Note on bit notation: Bits are shown in high-to-low order from left to right.

Related Material: The latest information is available at our Web Site. Please make sure that

you have the most up-to-date information available. (http://www.hitachisemiconductor.com/)

Page 6

User's Manuals on the H8/3062:

Manual Title ADE No.

H8/3062 Hardware Manual This manual H8/300H Series Programming Manual ADE-602-053

Users manuals for development tools:

Manual Title ADE No.

C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual ADE-702-247 H8S, H8/300 Series Simulator/Debugger User’s Manual ADE-702-037 Hitachi Embedded Workshop User’s Manual ADE-702-201 H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging

Interface User’s Manual

ADE-702-231

Application Note:

Manual Title ADE No.

H8/300H for CPU Application Note ADE-502-033 H8/300H On-Chip Supporting Modules Application Note ADE-502-035 H8/300H Technical Q&A ADE-502-038

Page 7

Comparison of H8/3062 Series Product Specifications

There are 11 members of the H8/3062 Series: the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062F-ZTAT B-mask version, and H8/3064F-ZTAT B-mask version (all with on-chip flash memory), and the H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version.

The specifications of these products are compared below.

H8/3064 Mask ROM

H8/3062 Mask

H8/3062F-ZTAT H8/3062F-ZTAT

Product specifications

Product code

Pin arrangement

RAM size 4 kbytes H8/3062:

On-chip singlepower-supply flash memory

HD64F3062 HD64F3062R HD6433062

See figures 1.2 and 1.3, Pin Arrangement, in section 1 H8/3064F-ZTAT

R-Mask Version

H8/3062F-ZTAT version with address output functions added

ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version

Mask ROM version

HD6433061 HD6433060

4 kbytes H8/3061:

4 kbytes H8/3060:

2 kbytes

H8/3064F-ZTAT B-Mask Version

On-chip largecapacity singlepower-supply flash memory

Internal stepdown circuit

HD64F3064B HD64F3062B HD6433064B

B-mask version has V

pin, and

requires connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

8 kbytes 4 kbytes H8/3064B:

H8/3062F-ZTAT B-Mask Version

H8/3062F-ZTAT high-speed operation version

H8/3062F-ZTAT B-mask version has V

pin, and

requires connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

B-Mask Version, H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, H8/3060 Mask ROM B-Mask Version

Mask ROM version

HD6433062B HD6433061B HD6433060B

H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version have V

pin, and require

connection of external capacitor

See figures 1.4 and 1.5, Pin Arrangement, in section 1

8 kbytes H8/3062B:

4 kbytes H8/3061B:

4 kbytes H8/3060B:

2 kbytes

Page 8

H8/3062F-ZTAT H8/3062F-ZTAT

ROM size 128 kbytes H8/3062:

Address output functions

Flash memory

Mask ROM — — See section 17,

Electrical characteristics (operating frequency)

Compatible with previous H8/300H Series

See section 17, ROM — See 18.1.1,

See table 22.1, Comparison of H8/3062 Series Electrical Characteristics, in section 22

R-Mask Version

Address update mode 1 or 2 selectable

See 6.3.5, Address Output Method, in section 6

1 to 20 MHz 2 to 25 MHz

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version

128 kbytes H8/3061:

96 kbytes H8/3060:

64 kbytes

ROM

H8/3064 Mask ROM B-Mask Version,

H8/3062 Mask ROM H8/3064F-ZTAT B-Mask Version

256 kbytes 128 kbytes H8/3064B:

Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version, in section 18

— — Mask ROM B-mask

H8/3062F-ZTAT B-Mask Version

See 19.1.1, Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version, in section 19

B-Mask Version,

H8/3061 Mask ROM

B-Mask Version,

H8/3060 Mask ROM

B-Mask Version

256 kbytes

H8/3062B:

128 kbytes

H8/3061B:

96 kbytes

H8/3060B:

64 kbytes

—

version of H8/3064:

see section 18.

Mask ROM B-mask

versions of H8/3062,

H8/3061, and

H8/3060: see section

19.

Page 9

H8/3062 Mask

H8/3062F-ZTAT H8/3062F-ZTAT

Registers See table B.1, Comparison of H8/3062 Series Internal I/O Register Specifications,

Usage notes

in appendix B See appendix

B.1, Address List

See 1.4, H8/3062F-ZTAT R-Mask Version Usage Note, in section 1

R-Mask Version

See appendix B.1, Address List

ROM Version, H8/3061 Mask ROM Version, H8/3060 Mask ROM Version

See appendix B.1, Address List

H8/3064F-ZTAT B-Mask Version

See appendix B.2, Address List

See 1.5, H8/3064F-ZTAT B-Mask Version, and H8/3062F-ZTAT B-Mask Version Usage Note, in section 1

H8/3062F-ZTAT B-Mask Version

See appendix B.3, Address List

H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, H8/3060 Mask ROM B-Mask Version

Mask ROM B-mask version of H8/3064: see appendix B.2, Address List.

Mask ROM B-mask versions of H8/3062, H8/3061, and H8/3060: see appendix B.3, Address List.

Page 10

Page 11

List of Items Revised or Added for This Version

Description

Section Page Item

All — All The H8/3064 mask ROM

1. Overview 18 1.3.3 Pin Assignments in Each Mode

25 1.5.2 Product Type

Names and Markings

27 1.5.4 Notes on

Changeover to Mask ROM Version or Mask ROM B-Mask Version

6. Bus Controller 139 6.3.1 Area Division

(See Manual for Details)

B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM Bmask version are added to the product line-up.

Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A)

• (V

)*4 is added to modes 2

to 7 in the first row.

Table 1.7 Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3064FZTAT, and H8/3064F-ZTAT B-Mask Version Markings

• The marking examples of H8/3062F-ZTAT B-mask version and H8/3064FZTAT B-mask version are amended.

• Title is amended.

• Note (2) is added.

• Figure 6.3 Memory Map in

16-Mbyte Mode (H8/3060 Mask ROM Version, H8/3060 Mask ROM B-Mask Version) (2) is added.

• The Memory Map in 16Mbyte Mode (H8/3064FZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version) is moved from figure 6.3 (2) to figure

6.3 (3).

Page 12

Description

Section Page Item

12. Serial Communication Interface

14. A/D Converter 447 14.1.1 Features The high-speed conversion

17. ROM [H8/3062FZTAT, H8/3062F-ZTAT R-Mask Version, On-Chip Mask ROM Models]

18. H8/3064 Internal Voltage Step-Down Version ROM [H8/3064F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version]

19. H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]

394 12.3.2 Operation in

Asynchronous Mode

482 17.2.4 Register

Configuration

523 to 574 All The title of the section is

572 18.12 Mask ROM

(H8/3064 Mask ROM B-Mask Version) Overview

573 18.13 Notes on Ordering

Mask ROM Version Chips

574 18.14 Notes on

Converting the F-ZTAT Application Software to the Mask ROM Versions

575 to 626 All

594 19.5.1 Boot Mode The start address of the

(See Manual for Details)

Figure 12.4 Sample Flowchart for SCI Initialization

• Note is added.

time is amended. Note 3 is deleted.

changed from Flash Memory [H8/3064F-ZTAT B-Mask Version].

Newly added.

• The title of the section is changed from Flash Memory.

• Descriptions on the mask ROM B-mask versions of H8/3062, H8/3061, and H8/3060 are added.

programming control program is amended to H'FFF520.

Page 13

Section Page Item

19. H8/3062 Internal Voltage Step-Down Version ROM [H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]

20. Clock Pulse Generator

21. Power-Down State 644 21.4.3 Selection of

22. Electrical Characteristics

624 19.12 Mask ROM

(H8/3062 Mask ROM BMask Version, H8/3061 Mask ROM B-Mask Version, H8/3060 Mask ROM B-Mask Version) Overview

625 19.13 Notes on Ordering

Mask ROM Version Chips

626 19.14 Notes on

Converting the F-ZTAT Application Software to the Mask ROM Versions

628 20.2.1 Connecting a

Crystal Resonator

634 20.5.3 Usage Notes Table 20.7 Comparison of

Waiting Time for Exit from Software Standby Mode

695 22.3 Electrical

Characteristics of H8/3064F-ZTAT B-Mask Version

22.3.1 Absolute Maximum Ratings

696, 699 22.3.2 DC

Characteristics

Description (See Manual for Details)

Newly added.

• Moved from 19.12.

• Table is amended.

Table 20.1 (1) Damping Resistance Value

• Note is amended.

H8/3062 Series Operating Frequency Ranges is amended.

Table 21.3 Clock Frequency and Waiting Time for Clock to Settle

• The value 13.1 is specified for the recommended setting for DIV = 1, DIV0 = 1, and 32468 states

Table 22.21 Absolute Maximum Ratings

The operating temperature rating is amended

Table22.22 DC Characteristics, and Table

22.23 Permissible Output

Currents

• A new condition is added.

Page 14

Section Page Item

22. Electrical Characteristics

701, 702, 703, 705

707 22.3.4 A/D Conversion

708 22.3.5 D/A Conversion

709 22.3.6 Flash Memory

711 to 723 22.4 Electrical

724 to 739 22.5 Electrical

724 22.5.1 Absolute

725 22.5.2 DC

730, 731, 732, 734

22.3.3 AC Characteristics

Characteristics

Characteristics of H8/3064 Mask ROM BMask Version

Characteristics of H8/3062F-ZTAT B-Mask Version

Maximum Ratings

Characteristics

22.5.3 AC Characteristics

Description (See Manual for Details)

Table 22.24 Clock Timing, Table 22.25 Control Signal Timing, Table 22.26 Bus Timing, and Table 22.27 Timing of On-Chip Supporting Modules

• A new condition is added. Table 22.28 A/D Conversion

Characteristics

• A new condition is added. Table 22.29 D/A conversion

Characteristics

• A new condition is added. Table 22.30 Flash Memory

Characteristics

• A new condition is added. Newly added

The section is moved from

22.4.

Table 22.40 Absolute Maximum Ratings

The operating temperature rating is amended

Table22.41 DC Characteristics, and Table

22.42 Permissible Output Currents

• A new condition is added. Table 22.43 Clock Timing,

Table 22.44 Control Signal Timing, Table 22.45 Bus Timing, and Table 22.46 Timing of On-Chip Supporting Modules

• A new condition is added.

Page 15

Section Page Item

22. Electrical Characteristics

736 22.5.4 A/D Conversion

Characteristics

737 22.5.5 D/A Conversion

Characteristics

738 22.5.6 Flash Memory

Characteristics

740 to 752 22.6 Electrical

Characteristics of H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version

753 to 761 22.7 Operational Timing The section is moved from

Appendix 906 C.7 Port 7 Block

Diagram

Description (See Manual for Details)

Table 22.47 A/D Conversion Characteristics

• A new condition is added.

Table 22.48 D/A conversion Characteristics

• A new condition is added.

Table 22.49 Flash Memory Characteristics

• A new condition is added.

Newly added

22.5.

• Figure C.7(a) Port 7 Block Diagram (Pins P7

to P75) is

amended.

• Figure C.7(b) Port 7 Block Diagram (Pins P7

to P77) is

amended.

Page 16

Page 17

Section 1 Overview........................................................................................................... 1

1.1 Overview............................................................................................................................ 1

1.2 Block Diagram................................................................................................................... 7

1.3 Pin Description.................................................................................................................. 8

1.3.1 Pin Arrangement .................................................................................................. 8

1.3.2 Pin Functions........................................................................................................ 13

1.3.3 Pin Assignments in Each Mode............................................................................ 18

1.4 Notes on H8/3062F-ZTAT R-Mask Version .................................................................... 22

1.4.1 Pin Arrangement .................................................................................................. 22

1.4.2 Product Type Names and Markings ..................................................................... 23

1.4.3 Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version. 23

1.5 Notes on H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask Version,

H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version ....... 24

1.5.1 Pin Arrangement.................................................................................................. 25

1.5.2 Product Type Names and Markings ..................................................................... 25

1.5.3 VCL Pin.................................................................................................................. 26

1.5.4 Notes on Changeover to On-Chip Mask ROM Versions and

On-Chip Mask ROM B-Mask Versions............................................................... 27

1.6 Setting Oscillation Settling Wait Time.............................................................................. 28

1.7 Caution on Crystal Resonator Connection........................................................................ 28

Section 2 CPU..................................................................................................................... 29

2.1 Overview............................................................................................................................ 29

2.1.1 Features ................................................................................................................ 29

2.1.2 Differences from H8/300 CPU............................................................................. 30

2.2 CPU Operating Modes ...................................................................................................... 31

2.3 Address Space.................................................................................................................... 31

2.4 Register Configuration ......................................................................................................32

2.4.1 Overview.............................................................................................................. 32

2.4.2 General Registers.................................................................................................. 33

2.4.3 Control Registers.................................................................................................. 34

2.4.4 Initial CPU Register Values...................................................................................... 35

2.5 Data Formats...................................................................................................................... 36

2.5.1 General Register Data Formats ............................................................................ 36

2.5.2 Memory Data Formats.......................................................................................... 37

2.6 Instruction Set.................................................................................................................... 39

2.6.1 Instruction Set Overview...................................................................................... 39

2.6.2 Instructions and Addressing Modes ..................................................................... 40

Page 18

2.6.3 Tables of Instructions Classified by Function...................................................... 41

2.6.4 Basic Instruction Formats..................................................................................... 50

2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 51

2.7 Addressing Modes and Effective Address Calculation..................................................... 53

2.7.1 Addressing Modes................................................................................................ 53

2.7.2 Effective Address Calculation.............................................................................. 55

2.8 Processing States ............................................................................................................... 59

2.8.1 Overview.............................................................................................................. 59

2.8.2 Program Execution State...................................................................................... 59

2.8.3 Exception-Handling State .................................................................................... 60

2.8.4 Exception Handling Operation ............................................................................. 61

2.8.5 Bus-Released State............................................................................................... 62

2.8.6 Reset State............................................................................................................ 62

2.8.7 Power-Down State................................................................................................ 63

2.9 Basic Operational Timing.................................................................................................. 63

2.9.1 Overview.............................................................................................................. 63

2.9.2 On-Chip Memory Access Timing ........................................................................ 63

2.9.3 On-Chip Supporting Module Access Timing....................................................... 64

2.9.4 Access to External Address Space ....................................................................... 65

Section 3 MCU Operating Modes ................................................................................ 67

3.1 Overview............................................................................................................................ 67

3.1.1 Operating Mode Selection.................................................................................... 67

3.1.2 Register Configuration ......................................................................................... 68

3.2 Mode Control Register (MDCR)....................................................................................... 68

3.3 System Control Register (SYSCR).................................................................................... 69

3.4 Operating Mode Descriptions............................................................................................ 72

3.4.1 Mode 1.................................................................................................................. 72

3.4.2 Mode 2.................................................................................................................. 72

3.4.3 Mode 3.................................................................................................................. 72

3.4.4 Mode 4.................................................................................................................. 72

3.4.5 Mode 5.................................................................................................................. 72

3.4.6 Mode 6.................................................................................................................. 73

3.4.7 Mode 7.................................................................................................................. 73

3.5 Pin Functions in Each Operating Mode............................................................................. 73

3.6 Memory Map in Each Operating Mode............................................................................. 74

3.6.1 Comparison of H8/3062 Series Memory Maps.................................................... 74

3.6.2 Reserved Areas..................................................................................................... 75

Section 4 Exception Handling........................................................................................ 85

4.1 Overview............................................................................................................................ 85

4.1.1 Exception Handling Types and Priority ............................................................... 85

4.1.2 Exception Handling Operation ............................................................................. 85

Page 19

4.1.3 Exception Vector Table........................................................................................ 86

4.2 Reset.................................................................................................................................. 88

4.2.1 Overview.............................................................................................................. 88

4.2.2 Reset Sequence..................................................................................................... 88

4.2.3 Interrupts after Reset ............................................................................................ 91

4.3 Interrupts............................................................................................................................ 92

4.4 Trap Instruction ................................................................................................................. 92

4.5 Stack Status after Exception Handling.............................................................................. 93

4.6 Notes on Stack Usage........................................................................................................94

Section 5 Interrupt Controller........................................................................................ 97

5.1 Overview............................................................................................................................ 97

5.1.1 Features ................................................................................................................ 97

5.1.2 Block Diagram...................................................................................................... 98

5.1.3 Pin Configuration ................................................................................................. 99

5.1.4 Register Configuration ......................................................................................... 99

5.2 Register Descriptions......................................................................................................... 99

5.2.1 System Control Register (SYSCR) ...................................................................... 99

5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 100

5.2.3 IRQ Status Register (ISR) .................................................................................... 105

5.2.4 IRQ Enable Register (IER) .................................................................................. 106

5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 107

5.3 Interrupt Sources................................................................................................................ 108

5.3.1 External Interrupts................................................................................................ 108

5.3.2 Internal Interrupts................................................................................................. 109

5.3.3 Interrupt Exception Handling Vector Table ......................................................... 109

5.4 Interrupt Operation............................................................................................................ 113

5.4.1 Interrupt Handling Process ................................................................................... 113

5.4.2 Interrupt Exception Handling Sequence .............................................................. 118

5.4.3 Interrupt Response Time ...................................................................................... 119

5.5 Usage Notes....................................................................................................................... 120

5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 120

5.5.2 Instructions that Inhibit Interrupts........................................................................ 121

5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 121

Section 6 Bus Controller.................................................................................................. 123

6.1 Overview............................................................................................................................ 123

6.1.1 Features ................................................................................................................ 123

6.1.2 Block Diagram...................................................................................................... 124

6.1.3 Pin Configuration ................................................................................................. 125

6.1.4 Register Configuration ......................................................................................... 126

6.2 Register Descriptions......................................................................................................... 126

6.2.1 Bus Width Control Register (ABWCR) ............................................................... 126

iii

Page 20

6.2.2 Access State Control Register (ASTCR).............................................................. 127

6.2.3 Wait Control Registers H and L (WCRH, WCRL).............................................. 128

6.2.4 Bus Release Control Register (BRCR) ................................................................ 132

6.2.5 Bus Control Register (BCR) ................................................................................ 133

6.2.6 Chip Select Control Register (CSCR).................................................................. 135

6.2.7 Address Control Register (ADRCR).................................................................... 136

6.3 Operation ........................................................................................................................... 137

6.3.1 Area Division........................................................................................................ 137

6.3.2 Bus Specifications................................................................................................ 141

6.3.3 Memory Interfaces................................................................................................ 142

6.3.4 Chip Select Signals............................................................................................... 142

6.3.5 Address Output Method ....................................................................................... 143

6.4 Basic Bus Interface............................................................................................................ 145

6.4.1 Overview.............................................................................................................. 145

6.4.2 Data Size and Data Alignment ............................................................................. 145

6.4.3 Valid Strobes........................................................................................................ 146

6.4.4 Memory Areas...................................................................................................... 147

6.4.5 Basic Bus Control Signal Timing......................................................................... 148

6.4.6 Wait Control......................................................................................................... 155

6.5 Idle Cycle........................................................................................................................... 157

6.5.1 Operation.............................................................................................................. 157

6.5.2 Pin States in Idle Cycle ........................................................................................ 159

6.6 Bus Arbiter ........................................................................................................................ 159

6.6.1 Operation.............................................................................................................. 160

6.7 Register and Pin Input Timing .......................................................................................... 162

6.7.1 Register Write Timing.......................................................................................... 162

6.7.2 BREQ Pin Input Timing....................................................................................... 163

Section 7 I/O Ports ............................................................................................................ 165

7.1 Overview............................................................................................................................ 165

7.2 Port 1.................................................................................................................................. 169

7.2.1 Overview.............................................................................................................. 169

7.2.2 Register Descriptions............................................................................................ 169

7.3 Port 2.................................................................................................................................. 172

7.3.1 Overview.............................................................................................................. 172

7.3.2 Register Descriptions............................................................................................ 173

7.4 Port 3.................................................................................................................................. 176

7.4.1 Overview.............................................................................................................. 176

7.4.2 Register Descriptions............................................................................................ 176

7.5 Port 4.................................................................................................................................. 178

7.5.1 Overview.............................................................................................................. 178

7.5.2 Register Descriptions............................................................................................ 179

7.6 Port 5.................................................................................................................................. 181

Page 21

7.6.1 Overview.............................................................................................................. 181

7.6.2 Register Descriptions............................................................................................ 182

7.7 Port 6.................................................................................................................................. 184

7.7.1 Overview.............................................................................................................. 184

7.7.2 Register Descriptions............................................................................................ 185

7.8 Port 7.................................................................................................................................. 188

7.8.1 Overview.............................................................................................................. 188

7.8.2 Register Description............................................................................................. 189

7.9 Port 8.................................................................................................................................. 190

7.9.1 Overview.............................................................................................................. 190

7.9.2 Register Descriptions............................................................................................ 191

7.10 Port 9.................................................................................................................................. 195

7.10.1 Overview.............................................................................................................. 195

7.10.2 Register Descriptions............................................................................................ 196

7.11 Port A................................................................................................................................. 200

7.11.1 Overview.............................................................................................................. 200

7.11.2 Register Descriptions............................................................................................ 202

7.12 Port B................................................................................................................................. 212

7.12.1 Overview.............................................................................................................. 212

7.12.2 Register Descriptions............................................................................................ 214

Section 8 16-Bit Timer..................................................................................................... 221

8.1 Overview............................................................................................................................ 221

8.1.1 Features ................................................................................................................ 221

8.1.2 Block Diagrams.................................................................................................... 223

8.1.3 Pin Configuration ................................................................................................. 226

8.1.4 Register Configuration ......................................................................................... 227

8.2 Register Descriptions......................................................................................................... 228

8.2.1 Timer Start Register (TSTR)................................................................................ 228

8.2.2 Timer Synchro Register (TSNC).......................................................................... 229

8.2.3 Timer Mode Register (TMDR) ............................................................................ 230

8.2.4 Timer Interrupt Status Register A (TISRA) ......................................................... 233

8.2.5 Timer Interrupt Status Register B (TISRB).......................................................... 235

8.2.6 Timer Interrupt Status Register C (TISRC).......................................................... 238

8.2.7 Timer Counters (16TCNT)................................................................................... 240

8.2.8 General Registers (GRA, GRB) ........................................................................... 241

8.2.9 Timer Control Registers (16TCR)........................................................................ 242

8.2.10 Timer I/O Control Register (TIOR) ..................................................................... 244

8.2.11 Timer Output Level Setting Register C (TOLR).................................................. 246

8.3 CPU Interface.................................................................................................................... 248

8.3.1 16-Bit Accessible Registers.................................................................................. 248

8.3.2 8-Bit Accessible Registers.................................................................................... 250

8.4 Operation ........................................................................................................................... 251

Page 22

8.4.1 Overview.............................................................................................................. 251

8.4.2 Basic Functions .................................................................................................... 251

8.4.3 Synchronization.................................................................................................... 259

8.4.4 PWM Mode.......................................................................................................... 261

8.4.5 Phase Counting Mode .......................................................................................... 265

8.4.6 16-Bit Timer Output Timing ................................................................................ 267

8.5 Interrupts............................................................................................................................ 268

8.5.1 Setting of Status Flags.......................................................................................... 268

8.5.2 Timing of Clearing of Status Flags ...................................................................... 270

8.5.3 Interrupt Sources .................................................................................................. 271

8.6 Usage Notes....................................................................................................................... 272

Section 9 8-Bit Timers ..................................................................................................... 285

9.1 Overview............................................................................................................................ 285

9.1.1 Features ................................................................................................................ 285

9.1.2 Block Diagram...................................................................................................... 287

9.1.3 Pin Configuration ................................................................................................. 288

9.1.4 Register Configuration ......................................................................................... 289

9.2 Register Descriptions......................................................................................................... 290

9.2.1 Timer Counters (8TCNT)..................................................................................... 290

9.2.2 Time Constant Registers A (TCORA) ................................................................. 291

9.2.3 Time Constant Registers B (TCORB).................................................................. 292

9.2.4 Timer Control Register (8TCR) ........................................................................... 293

9.2.5 Timer Control/Status Registers (8TCSR) ............................................................ 296

9.3 CPU Interface.................................................................................................................... 301

9.3.1 8-Bit Registers...................................................................................................... 301

9.4 Operation ........................................................................................................................... 303

9.4.1 8TCNT Count Timing.......................................................................................... 303

9.4.2 Compare Match Timing ....................................................................................... 304

9.4.3 Input Capture Signal Timing................................................................................ 305

9.4.4 Timing of Status Flag Setting............................................................................... 306

9.4.5 Operation with Cascaded Connection .................................................................. 307

9.4.6 Input Capture Setting............................................................................................ 310

9.5 Interrupt ............................................................................................................................. 311

9.5.1 Interrupt Sources .................................................................................................. 311

9.5.2 A/D Converter Activation .................................................................................... 312

9.6 8-Bit Timer Application Example..................................................................................... 312

9.7 Usage Notes....................................................................................................................... 313

9.7.1 Contention between 8TCNT Write and Clear...................................................... 313

9.7.2 Contention between 8TCNT Write and Increment .............................................. 314

9.7.3 Contention between TCOR Write and Compare Match ...................................... 315

9.7.4 Contention between TCOR Read and Input Capture ........................................... 316

9.7.5 Contention between Counter Clearing by Input Capture and Counter Increment 317

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9.7.6 Contention between TCOR Write and Input Capture .......................................... 318

9.7.7 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode

(Cascaded Connection) ........................................................................................ 319

9.7.8 Contention between Compare Matches A and B ................................................. 320

9.7.9 8TCNT Operation and Internal Clock Source Switchover .................................. 320

Section 10 Programmable Timing Pattern Controller (TPC).................................. 323

10.1 Overview............................................................................................................................ 323

10.1.1 Features ................................................................................................................ 323

10.1.2 Block Diagram...................................................................................................... 324

10.1.3 Pin Configuration ................................................................................................. 325

10.1.4 Register Configuration ......................................................................................... 326

10.2 Register Descriptions......................................................................................................... 327

10.2.1 Port A Data Direction Register (PADDR) ........................................................... 327

10.2.2 Port A Data Register (PADR) .............................................................................. 327

10.2.3 Port B Data Direction Register (PBDDR)............................................................ 328

10.2.4 Port B Data Register (PBDR)............................................................................... 328

10.2.5 Next Data Register A (NDRA) ............................................................................ 329

10.2.6 Next Data Register B (NDRB)............................................................................. 331

10.2.7 Next Data Enable Register A (NDERA).............................................................. 333

10.2.8 Next Data Enable Register B (NDERB) .............................................................. 334

10.2.9 TPC Output Control Register (TPCR) ................................................................. 335

10.2.10 TPC Output Mode Register (TPMR) ................................................................... 337

10.3 Operation ........................................................................................................................... 339

10.3.1 Overview.............................................................................................................. 339

10.3.2 Output Timing...................................................................................................... 340

10.3.3 Normal TPC Output ............................................................................................. 341

10.3.4 Non-Overlapping TPC Output ............................................................................. 343

10.3.5 TPC Output Triggering by Input Capture ............................................................ 345

10.4 Usage Notes....................................................................................................................... 346

10.4.1 Operation of TPC Output Pins ............................................................................. 346

10.4.2 Note on Non-Overlapping Output........................................................................ 346

Section 11 Watchdog Timer ............................................................................................. 349

11.1 Overview............................................................................................................................ 349

11.1.1 Features ................................................................................................................ 349

11.1.2 Block Diagram...................................................................................................... 350

11.1.3 Pin Configuration ................................................................................................. 350

11.1.4 Register Configuration ......................................................................................... 351

11.2 Register Descriptions......................................................................................................... 351

11.2.1 Timer Counter (TCNT) ........................................................................................ 351

11.2.2 Timer Control/Status Register (TCSR)................................................................ 352

11.2.3 Reset Control/Status Register (RSTCSR)............................................................ 354

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11.2.4 Notes on Register Rewriting ................................................................................ 355

11.3 Operation ........................................................................................................................... 357

11.3.1 Watchdog Timer Operation.................................................................................. 357

11.3.2 Interval Timer Operation...................................................................................... 358

11.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 358

11.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) .................................. 359

11.4 Interrupts............................................................................................................................ 360

11.5 Usage Notes....................................................................................................................... 360

Section 12 Serial Communication Interface................................................................ 361

12.1 Overview............................................................................................................................ 361

12.1.1 Features ................................................................................................................ 361

12.1.2 Block Diagram...................................................................................................... 363

12.1.3 Pin Configuration ................................................................................................. 364

12.1.4 Register Configuration ......................................................................................... 365

12.2 Register Descriptions......................................................................................................... 366

12.2.1 Receive Shift Register (RSR)............................................................................... 366

12.2.2 Receive Data Register (RDR) .............................................................................. 366

12.2.3 Transmit Shift Register (TSR).............................................................................. 367

12.2.4 Transmit Data Register (TDR)............................................................................. 367

12.2.5 Serial Mode Register (SMR)................................................................................ 368

12.2.6 Serial Control Register (SCR).............................................................................. 371

12.2.7 Serial Status Register (SSR)................................................................................. 375

12.2.8 Bit Rate Register (BRR)....................................................................................... 380

12.3 Operation ........................................................................................................................... 388

12.3.1 Overview.............................................................................................................. 388

12.3.2 Operation in Asynchronous Mode........................................................................ 391

12.3.3 Multiprocessor Communication........................................................................... 400

12.3.4 Synchronous Operation........................................................................................ 407

12.4 SCI Interrupts .................................................................................................................... 415

12.5 Usage Notes....................................................................................................................... 416

12.5.1 Notes on Use of SCI............................................................................................. 416

Section 13 Smart Card Interface...................................................................................... 421

13.1 Overview............................................................................................................................ 421

13.1.1 Features ................................................................................................................ 421

13.1.2 Block Diagram...................................................................................................... 422

13.1.3 Pin Configuration ................................................................................................. 422

13.1.4 Register Configuration ......................................................................................... 423

13.2 Register Descriptions......................................................................................................... 424

13.2.1 Smart Card Mode Register (SCMR) .................................................................... 424

13.2.2 Serial Status Register (SSR)................................................................................. 426

13.2.3 Serial Mode Register (SMR)................................................................................ 427

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13.2.4 Serial Control Register (SCR).............................................................................. 428

13.3 Operation ........................................................................................................................... 429

13.3.1 Overview.............................................................................................................. 429

13.3.2 Pin Connections.................................................................................................... 429

13.3.3 Data Format.......................................................................................................... 430

13.3.4 Register Settings................................................................................................... 432

13.3.5 Clock .................................................................................................................... 434

13.3.6 Transmitting and Receiving Data......................................................................... 436

13.4 Usage Notes....................................................................................................................... 443

Section 14 A/D Converter ................................................................................................. 447

14.1 Overview............................................................................................................................ 447

14.1.1 Features ................................................................................................................ 447

14.1.2 Block Diagram...................................................................................................... 448

14.1.3 Pin Configuration ................................................................................................. 449

14.1.4 Register Configuration ......................................................................................... 450

14.2 Register Descriptions......................................................................................................... 450

14.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 450

14.2.2 A/D Control/Status Register (ADCSR)................................................................ 451

14.2.3 A/D Control Register (ADCR)............................................................................. 453

14.3 CPU Interface.................................................................................................................... 454

14.4 Operation ........................................................................................................................... 456

14.4.1 Single Mode (SCAN = 0)..................................................................................... 456

14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 458

14.4.3 Input Sampling and A/D Conversion Time.......................................................... 460

14.4.4 External Trigger Input Timing ............................................................................. 461

14.5 Interrupts............................................................................................................................ 462

14.6 Usage Notes....................................................................................................................... 462

Section 15 D/A Converter ................................................................................................. 467

15.1 Overview............................................................................................................................ 467

15.1.1 Features ................................................................................................................ 467

15.1.2 Block Diagram...................................................................................................... 468

15.1.3 Pin Configuration ................................................................................................. 469

15.1.4 Register Configuration ......................................................................................... 469

15.2 Register Descriptions......................................................................................................... 470

15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 470

15.2.2 D/A Control Register (DACR)............................................................................. 470

15.2.3 D/A Standby Control Register (DASTCR).......................................................... 472

15.3 Operation ........................................................................................................................... 472

15.4 D/A Output Control ........................................................................................................... 474

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Section 16 RAM................................................................................................................... 475

16.1 Overview............................................................................................................................ 475

16.1.1 Block Diagram...................................................................................................... 476

16.1.2 Register Configuration ......................................................................................... 476

16.2 System Control Register (SYSCR).................................................................................... 477

16.3 Operation ........................................................................................................................... 478

Section 17 ROM [H8/3062F-ZTAT, H8/3062F-ZTAT ROM Version,

On-Chip Mask ROM Models]

17.1 Overview............................................................................................................................ 479

17.2 Overview of Flash Memory (H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version)...... 480

17.2.1 Features ................................................................................................................ 480

17.2.2 Block Diagram...................................................................................................... 481

17.2.3 Pin Configuration ................................................................................................. 482

17.2.4 Register Configuration ......................................................................................... 482

17.3 Flash Memory Register Descriptions ................................................................................ 483

17.3.1 Flash Memory Control Register (FLMCR).......................................................... 483

17.3.2 Erase Block Register (EBR)................................................................................. 486

17.3.3 RAM Control Register (RAMCR) ....................................................................... 487

17.3.4 Flash Memory Status Register (FLMSR)............................................................. 489

17.4 On-Board Programming Mode.......................................................................................... 490

17.4.1 Boot Mode............................................................................................................ 493

17.4.2 User Program Mode ............................................................................................. 498

17.5 Flash Memory Programming/Erasing................................................................................ 500

17.5.1 Program Mode...................................................................................................... 501

17.5.2 Program-Verify Mode.......................................................................................... 502

17.5.3 Erase Mode........................................................................................................... 504

17.5.4 Erase-Verify Mode............................................................................................... 504

17.6 Flash Memory Protection.................................................................................................. 506

17.6.1 Hardware Protection............................................................................................. 506

17.6.2 Software Protection.............................................................................................. 508

17.6.3 Error Protection.................................................................................................... 508

17.6.4 NMI Input Disabling Conditions............................................................................ 510

17.7 Flash Memory Emulation in RAM.................................................................................... 511

17.8 Flash Memory PROM Mode ............................................................................................. 513

17.8.1 Socket Adapters and Memory Map...................................................................... 513

17.8.2 Notes on Use of PROM Mode.............................................................................. 514

17.9 Flash Memory Programming and Erasing Precautions ..................................................... 515

17.10 Mask ROM (H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

H8/3060 Mask ROM Version) Overview.......................................................................... 520

17.10.1 Block Diagram ..................................................................................................... 520

17.11 Notes on Ordering Mask ROM Version Chips.................................................................. 521

17.12 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 522

.................................................................... 479

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Section 18 H8/3064 Internal Voltage Step-Down Version ROM

[H8/3064F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version]

18.1 Overview............................................................................................................................ 523

18.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version....... 524

18.2 Features.............................................................................................................................. 525

18.2.1 Block Diagram...................................................................................................... 526

18.2.2 Pin Configuration ................................................................................................. 527

18.2.3 Register Configuration ......................................................................................... 527

18.3 Register Descriptions......................................................................................................... 528

18.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 528

18.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 531

18.3.3 Erase Block Register 1 (EBR1)............................................................................ 532

18.3.4 Erase Block Register 2 (EBR2)............................................................................ 532

18.3.5 RAM Control Register (RAMCR) ....................................................................... 533

18.4 Overview of Operation...................................................................................................... 535

18.4.1 Mode Transitions.................................................................................................. 535

18.4.2 On-Board Programming Modes ........................................................................... 537

18.4.3 Flash Memory Emulation in RAM....................................................................... 539

18.4.4 Block Configuration............................................................................................. 540

18.5 On-Board Programming Mode.......................................................................................... 541

18.5.1 Boot Mode............................................................................................................ 542

18.5.2 User Program Mode.............................................................................................. 547

18.6 Flash Memory Programming/Erasing................................................................................ 549

18.6.1 Program Mode...................................................................................................... 551

18.6.2 Program-Verify Mode.......................................................................................... 552

18.6.3 Erase Mode........................................................................................................... 556

18.6.4 Erase-Verify Mode............................................................................................... 556

18.7 Flash Memory Protection .................................................................................................. 558

18.7.1 Hardware Protection............................................................................................. 558

18.7.2 Software Protection.............................................................................................. 559

18.7.3 Error Protection.................................................................................................... 559

18.8 Flash Memory Emulation in RAM.................................................................................... 562

18.9 NMI Input Disabling Conditions....................................................................................... 564

18.10 Flash Memory PROM Mode............................................................................................. 565

18.10.1 Socket Adapters and Memory Map...................................................................... 565

18.10.2 Notes on Use of PROM Mode.............................................................................. 566

18.11 Flash Memory Programming and Erasing Precautions..................................................... 566

18.12 Mask ROM (H8/3064 Mask ROM B-Mask Version) Overview...................................... 572

18.12.1 Block Diagram...................................................................................................... 572

18.13 Notes on Ordering Mask ROM Version Chips.................................................................. 573

18.14 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Version. 574

.................................................. 523

Page 28

Section 19 H8/3062 Internal Voltage Step-Down Version ROM

[H8/3062F-ZTAT B-Mask Version, Mask ROM B-Mask Versions of H8/3062, H8/3061, and H8/3060]

19.1 Overview............................................................................................................................ 575

19.1.1 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version......... 576

19.2 Features.............................................................................................................................. 577

19.2.1 Block Diagram...................................................................................................... 578

19.2.2 Pin Configuration ................................................................................................. 579

19.2.3 Register Configuration ......................................................................................... 579

19.3 Register Descriptions......................................................................................................... 580

19.3.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 580

19.3.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 583

19.3.3 Erase Block Register (EBR)................................................................................. 584

19.3.4 RAM Control Register (RAMCR) ....................................................................... 585

19.4 Overview of Operation...................................................................................................... 587

19.4.1 Mode Transitions.................................................................................................. 587

19.4.2 On-Board Programming Modes ........................................................................... 589

19.4.3 Flash Memory Emulation in RAM....................................................................... 591

19.4.4 Block Configuration............................................................................................. 592

19.5 On-Board Programming Mode.......................................................................................... 593

19.5.1 Boot Mode............................................................................................................ 594

19.5.2 User Program Mode ............................................................................................. 599

19.6 Flash Memory Programming/Erasing................................................................................ 601

19.6.1 Program Mode...................................................................................................... 603

19.6.2 Program-Verify Mode.......................................................................................... 604

19.6.3 Erase Mode........................................................................................................... 608

19.6.4 Erase-Verify Mode............................................................................................... 608

19.7 Flash Memory Protection .................................................................................................. 610

19.7.1 Hardware Protection............................................................................................. 610

19.7.2 Software Protection.............................................................................................. 611

19.7.3 Error Protection.................................................................................................... 611

19.8 Flash Memory Emulation in RAM.................................................................................... 614

19.9 NMI Input Disabling Conditions....................................................................................... 615

19.10 Flash Memory PROM Mode............................................................................................. 616

19.10.1 Socket Adapters and Memory Map...................................................................... 616

19.10.2 Notes on Use of PROM Mode.............................................................................. 617

19.11 Flash Memory Programming and Erasing Precautions..................................................... 618

19.12 Mask ROM (H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask

Version, H8/3060 Mask ROM B-Mask Version) Overview............................................. 624

19.12.1 Block Diagram...................................................................................................... 624

19.13 Notes on Ordering Mask ROM Version Chips.................................................................. 625

19.14 Notes when Converting the F-ZTAT Application Software to the Mask-ROM Versions 626

........................................................ 575

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Section 20 Clock Pulse Generator .................................................................................. 627

20.1 Overview............................................................................................................................ 627

20.1.1 Block Diagram...................................................................................................... 627

20.2 Oscillator Circuit ............................................................................................................... 628

20.2.1 Connecting a Crystal Resonator........................................................................... 628

20.2.2 External Clock Input ............................................................................................ 630

20.3 Duty Adjustment Circuit.................................................................................................... 632

20.4 Prescalers........................................................................................................................... 632

20.5 Frequency Divider............................................................................................................. 632

20.5.1 Register Configuration ......................................................................................... 633

20.5.2 Division Control Register (DIVCR) .................................................................... 633

20.5.3 Usage Notes.......................................................................................................... 634

Section 21 Power-Down State.......................................................................................... 635

21.1 Overview............................................................................................................................ 635

21.2 Register Configuration ...................................................................................................... 637

21.2.1 System Control Register (SYSCR) ...................................................................... 637

21.2.2 Module Standby Control Register H (MSTCRH)................................................ 639

21.2.3 Module Standby Control Register L (MSTCRL)................................................. 640

21.3 Sleep Mode........................................................................................................................ 642

21.3.1 Transition to Sleep Mode ..................................................................................... 642

21.3.2 Exit from Sleep Mode .......................................................................................... 642

21.4 Software Standby Mode .................................................................................................... 642

21.4.1 Transition to Software Standby Mode.................................................................. 642

21.4.2 Exit from Software Standby Mode....................................................................... 643

21.4.3 Selection of Waiting Time for Exit from Software Standby Mode...................... 643

21.4.4 Sample Application of Software Standby Mode.................................................. 645

21.4.5 Usage Note ........................................................................................................... 645

21.4.6 Cautions on Clearing the software Standby Mode of F-ZTAT Version.............. 646

21.5 Hardware Standby Mode ................................................................................................... 647

21.5.1 Transition to Hardware Standby Mode ................................................................ 647

21.5.2 Exit from Hardware Standby Mode ..................................................................... 647

21.5.3 Timing for Hardware Standby Mode ................................................................... 647

21.6 Module Standby Function.................................................................................................. 648

21.6.1 Module Standby Timing....................................................................................... 648

21.6.2 Read/Write in Module Standby............................................................................ 648

21.6.3 Usage Notes.......................................................................................................... 648

21.7 System Clock Output Disabling Function ......................................................................... 649

Section 22 Electrical Characteristics.............................................................................. 651

22.1 Electrical Characteristics of H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

and H8/3060 Mask ROM Version..................................................................................... 652

22.1.1 Absolute Maximum Ratings................................................................................. 652

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22.1.2 DC Characteristics................................................................................................ 653

22.1.3 AC Characteristics................................................................................................ 664

22.1.4 A/D Conversion Characteristics........................................................................... 670

22.1.5 D/A Conversion Characteristics........................................................................... 672

22.2 Electrical Characteristics of H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version... 673

22.2.1 Absolute Maximum Ratings................................................................................. 673

22.2.2 DC Characteristics................................................................................................ 674

22.2.3 AC Characteristics................................................................................................ 682

22.2.4 A/D Conversion Characteristics........................................................................... 688

22.2.5 D/A Conversion Characteristics........................................................................... 690

22.2.6 Flash Memory Characteristics.............................................................................. 691

22.3 Electrical Characteristics of H8/3064F-ZTAT B-Mask Version ...................................... 695

22.3.1 Absolute Maximum Ratings................................................................................. 695

22.3.2 DC Characteristics................................................................................................ 696

22.3.3 AC Characteristics................................................................................................ 701

22.3.4 A/D Conversion Characteristics........................................................................... 707

22.3.5 D/A Conversion Characteristics........................................................................... 708

22.3.6 Flash Memory Characteristics.............................................................................. 709

22.4 Electrical Characteristics of H8/3064 Mask ROM B-Mask Version ................................ 711

22.4.1 Absolute Maximum Ratings................................................................................. 711

22.4.2 DC Characteristics................................................................................................ 712

22.4.3 AC Characteristics................................................................................................ 716

22.4.4 A/D Conversion Characteristics........................................................................... 722

22.4.5 D/A Conversion Characteristics........................................................................... 723

22.5 Electrical Characteristics of H8/3062F-ZTAT B-Mask Version ...................................... 724

22.5.1 Absolute Maximum Ratings................................................................................. 724

22.5.2 DC Characteristics................................................................................................ 725

22.5.3 AC Characteristics................................................................................................ 730

22.5.4 A/D Conversion Characteristics........................................................................... 736

22.5.5 D/A Conversion Characteristics........................................................................... 737

22.5.6 Flash Memory Characteristics.............................................................................. 738

22.6 Electrical Characteristics of H8/3062 Mask ROM B-Mask Version,

H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version........ 740

22.6.1 Absolute Maximum Ratings................................................................................. 740

22.6.2 DC Characteristics................................................................................................ 741

22.6.3 AC Characteristics................................................................................................ 745

22.6.4 A/D Conversion Characteristics........................................................................... 751

22.6.5 D/A Conversion Characteristics........................................................................... 752

22.7 Operational Timing............................................................................................................ 753

22.7.1 Clock Timing........................................................................................................ 753

22.7.2 Control Signal Timing.......................................................................................... 754

22.7.3 Bus Timing........................................................................................................... 756

22.7.4 TPC and I/O Port Timing ..................................................................................... 760

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22.7.5 Timer Input/Output Timing.................................................................................. 760

22.7.6 SCI Input/Output Timing ..................................................................................... 761

Appendix A Instruction Set.............................................................................................. 763

A.1 Instruction List................................................................................................................... 763

A.2 Operation Code Maps........................................................................................................ 778

A.3 Number of States Required for Execution......................................................................... 781

Appendix B Internal I/O Registers................................................................................ 790

B.1 Address List

(H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, H8/3062 Mask ROM Version,

H8/3061 Mask ROM Version, H8/3060 Mask ROM Version) ........................................ 791

B.2 Address List

(H8/3064F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version).................. 801

B.3 Address List

(H8/3062F-ZTAT B-Mask Version, H8/3062 Mask ROM B-Mask Version,

H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version)...... 811

B.4 Functions............................................................................................................................ 821

Appendix C I/O Port Block Diagrams.......................................................................... 896

C.1 Port 1 Block Diagram........................................................................................................ 896

C.2 Port 2 Block Diagram........................................................................................................ 897

C.3 Port 3 Block Diagram........................................................................................................ 898

C.4 Port 4 Block Diagram........................................................................................................ 899

C.5 Port 5 Block Diagram........................................................................................................ 900

C.6 Port 6 Block Diagrams ...................................................................................................... 901

C.7 Port 7 Block Diagrams ...................................................................................................... 906

C.8 Port 8 Block Diagrams ...................................................................................................... 907

C.9 Port 9 Block Diagrams ...................................................................................................... 911

C.10 Port A Block Diagrams...................................................................................................... 917

C.11 Port B Block Diagrams...................................................................................................... 920

Appendix D Pin States....................................................................................................... 926

D.1 Port States in Each Mode .................................................................................................. 926

D.2 Pin States at Reset.............................................................................................................. 930

Appendix E Timing of Transition to and Recovery from Hardware

Standby Mode

.............................................................................................. 933

Appendix F Product Code Lineup................................................................................. 934

Appendix G Package Dimensions.................................................................................. 936

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Appendix H Comparison of H8/300H Series Product Specifications................. 939

H.1 Differences between H8/3067 and H8/3062 Series, H8/3048 Series,

H8/3007 and H8/3006, and H8/3002................................................................................. 939

H.2 Comparison of Pin Functions of 100-Pin Package Products (FP-100B, TFP-100B)........ 942

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Figures

Figure 1.1 Block Diagram.................................................................................................... 7

Figure 1.2 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and

H8/3060 Mask ROM Version (FP-100B or TFP-100B Package, Top View).... 9

Figure 1.3 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, and

H8/3060 Mask ROM Version (FP-100A Package, Top View).......................... 10

Figure 1.4 Pin Arrangement of H8/3064F-ZTAT B-Mask Version,

H8/3062F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version (FP-100B or TFP-100B Package,

Top View) .......................................................................................................... 11

Figure 1.5 Pin Arrangement of H8/3064F-ZTAT B-Mask Version,

H8/3062F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version,

and H8/3060 Mask ROM B-Mask Version (FP-100A Package, Top View)..... 12

Figure 1.6 H8/3062F-ZTAT B-Mask Version, H8/3064F-ZTAT B-Mask Version, and

On-Chip Mask ROM B-Mask Versions............................................................. 26

Figure 1.7 Example of Board Pattern Providing for External Capacitor............................. 27

Figure 2.1 CPU Operating Modes ....................................................................................... 31

Figure 2.2 Memory Map...................................................................................................... 31

Figure 2.3 CPU Registers.................................................................................................... 32

Figure 2.4 Usage of General Registers................................................................................ 33

Figure 2.5 Stack................................................................................................................... 34

Figure 2.6 General Register Data Formats.......................................................................... 36

Figure 2.7 General Register Data Formats.......................................................................... 37

Figure 2.8 Memory Data Formats........................................................................................ 38

Figure 2.9 Instruction Formats ............................................................................................ 51

Figure 2.10 Memory-Indirect Branch Address Specification................................................ 55

Figure 2.11 Processing States ................................................................................................ 59

Figure 2.12 Classification of Exception Sources................................................................... 60

Figure 2.13 State Transitions ................................................................................................. 61

Figure 2.14 Stack Structure after Exception Handling.......................................................... 62

Figure 2.15 On-Chip Memory Access Cycle ........................................................................ 64

Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1)............ 64

Figure 2.17 Access Cycle for On-Chip Supporting Modules................................................ 65

Figure 2.18 Pin States during Access to On-Chip Supporting Modules................................ 65

Figure 3.1 Memory Map of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,

H8/3062F-ZTAT B-Mask Version, H8/3062 Mask ROM Version, and

H8/3062 Mask ROM B-Mask Version in Each Operating Mode...................... 76

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Figure 3.2 Memory Map of H8/3061 Mask ROM Version and H8/3061 Mask ROM

B-Mask Version in Each Operating Mode......................................................... 78

Figure 3.3 Memory Map of H8/3060 Mask ROM Version and H8/3060 Mask ROM

B-Mask Version in Each Operating Mode......................................................... 80

Figure 3.4 H8/3064F-ZTAT B-Mask Version and H8/3064 Mask ROM B-Mask Version

Memory Map in Each Operating Mode.............................................................. 82

Figure 4.1 Exception Sources.............................................................................................. 86

Figure 4.2 Reset Sequence (Modes 1 and 3)........................................................................ 89

Figure 4.3 Reset Sequence (Modes 2 and 4)........................................................................ 90

Figure 4.4 Reset Sequence (Mode 6)................................................................................... 91

Figure 4.5 Interrupt Sources and Number of Interrupts....................................................... 92

Figure 4.6 Stack after Completion of Exception Handling.................................................. 93

Figure 4.7 Operation when SP Value is Odd....................................................................... 95

Figure 5.1 Interrupt Controller Block Diagram................................................................... 98

Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5........................................................ 108

Figure 5.3 Timing of Setting of IRQnF............................................................................... 109

Figure 5.4 Process Up to Interrupt Acceptance when UE = 1............................................. 114

Figure 5.5 Interrupt Masking State Transitions (Example)................................................. 116

Figure 5.6 Process Up to Interrupt Acceptance when UE = 0............................................. 117

Figure 5.7 Interrupt Exception Handling Sequence ............................................................ 118

Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction.................... 120

Figure 6.1 Block Diagram of Bus Controller ...................................................................... 124

Figure 6.2 Access Area Map for Each Operating Mode...................................................... 137

Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3062F-ZTAT, H8/3062F-ZTAT B-Mask

Version, H8/3062 Mask ROM Version, H8/3061 Mask ROM Version, H8/3062

Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version) (1)....... 138

Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3060 Mask ROM Version,

H8/3060 Mask ROM B-Mask Version) (2)........................................................ 139

Figure 6.3 Memory Map in 16-Mbyte Mode (H8/3064F-ZTAT B-Mask Version,

H8/3064 Mask ROM B-Mask Version) (3)........................................................ 140

Figure 6.4 CSn Signal Output Timing (n = 0 to 7).............................................................. 142

Figure 6.5 Sample Address Output in Each Address Update Mode (Basic Bus Interface,

3-State Space)..................................................................................................... 143

Figure 6.6 Example of Consecutive External Space Accesses in Address Update Mode 2 144

Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Area)........................ 145

Figure 6.8 Access Sizes and Data Alignment Control (16-Bit Access Area)...................... 146

Figure 6.9 Bus Control Signal Timing for 8-Bit, Three-State-Access Area........................ 148

Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area.......................... 149

Figure 6.11 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (1)

(Byte Access to Even Address).......................................................................... 150

Figure 6.12 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (2)

(Byte Access to Odd Address) ........................................................................... 151

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Figure 6.13 Bus Control Signal Timing for 16-Bit, Three-State-Access Area (3)

(Word Access).................................................................................................... 152

Figure 6.14 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (1)

(Byte Access to Even Address).......................................................................... 153

Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2)

(Byte Access to Odd Address) ........................................................................... 154

Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3)

(Word Access).................................................................................................... 155

Figure 6.17 Example of Wait State Insertion Timing............................................................ 156

Figure 6.18 Example of Idle Cycle Operation (ICIS1 = 1).................................................... 157

Figure 6.19 Example of Idle Cycle Operation (ICIS0 = 1).................................................... 158

Figure 6.20 Example of Idle Cycle Operation....................................................................... 158

Figure 6.21 Example of External Bus Master Operation ...................................................... 161

Figure 6.22 ASTCR Write Timing ........................................................................................ 162

Figure 6.23 DDR Write Timing............................................................................................. 162

Figure 6.24 BRCR Write Timing .......................................................................................... 163

Figure 7.1 Port 1 Pin Configuration .................................................................................... 169

Figure 7.2 Port 2 Pin Configuration .................................................................................... 172

Figure 7.3 Port 3 Pin Configuration .................................................................................... 176

Figure 7.4 Port 4 Pin Configuration .................................................................................... 178

Figure 7.5 Port 5 Pin Configuration .................................................................................... 181

Figure 7.6 Port 6 Pin Configuration .................................................................................... 185

Figure 7.7 Port 7 Pin Configuration .................................................................................... 188

Figure 7.8 Port 8 Pin Configuration .................................................................................... 190

Figure 7.9 Port 9 Pin Configuration .................................................................................... 195

Figure 7.10 Port A Pin Configuration.................................................................................... 201

Figure 7.11 Port B Pin Configuration.................................................................................... 213

Figure 8.1 16-bit timer Block Diagram (Overall)................................................................ 223

Figure 8.2 Block Diagram of Channels 0 and 1 .................................................................. 224

Figure 8.3 Block Diagram of Channel 2.............................................................................. 225

Figure 8.4 16TCNT Access Operation [CPU → 16TCNT (Word)].................................... 248

Figure 8.5 Access to Timer Counter (CPU Reads 16TCNT, Word)................................... 248

Figure 8.6 Access to Timer Counter H (CPU Writes to 16TCNTH, Upper Byte).............. 249

Figure 8.7 Access to Timer Counter L (CPU Writes to 16TCNTL, Lower Byte).............. 249

Figure 8.8 Access to Timer Counter H (CPU Reads 16TCNTH, Upper Byte)................... 249

Figure 8.9 Access to Timer Counter L (CPU Reads 16TCNTL, Lower Byte) ................... 250

Figure 8.10 16TCR Access (CPU Writes to 16TCR)............................................................ 250

Figure 8.11 16TCR Access (CPU Reads 16TCR)................................................................. 250

Figure 8.12 Counter Setup Procedure (Example).................................................................. 252

Figure 8.13 Free-Running Counter Operation....................................................................... 253

Figure 8.14 Periodic Counter Operation................................................................................ 253

Figure 8.15 Count Timing for Internal Clock Sources .......................................................... 254

Figure 8.16 Count Timing for External Clock Sources (when Both Edges are Detected).... 254

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Figure 8.17 Setup Procedure for Waveform Output by Compare Match (Example)............ 255

Figure 8.18 0 and 1 Output (TOA = 1, TOB = 0).................................................................. 256

Figure 8.19 Toggle Output (TOA = 1, TOB = 0) .................................................................. 256

Figure 8.20 Output Compare Output Timing ........................................................................ 257

Figure 8.21 Setup Procedure for Input Capture (Example) ................................................... 258

Figure 8.22 Input Capture (Example).................................................................................... 258

Figure 8.23 Input Capture Signal Timing.............................................................................. 259

Figure 8.24 Setup Procedure for Synchronization (Example) ............................................... 260

Figure 8.25 Synchronization (Example)................................................................................ 261

Figure 8.26 Setup Procedure for PWM Mode (Example) ..................................................... 262

Figure 8.27 PWM Mode (Example 1) ................................................................................... 263

Figure 8.28 PWM Mode (Example 2) ................................................................................... 264

Figure 8.29 Setup Procedure for Phase Counting Mode (Example)...................................... 265

Figure 8.30 Operation in Phase Counting Mode (Example).................................................. 266

Figure 8.31 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ............ 266

Figure 8.32 Timing for Setting 16-Bit Timer Output Level by Writing to TOLR................ 267

Figure 8.33 Timing of Setting of IMFA and IMFB by Compare Match............................... 268

Figure 8.34 Timing of Setting of IMFA and IMFB by Input Capture .................................. 269

Figure 8.35 Timing of Setting of OVF .................................................................................. 270

Figure 8.36 Timing of Clearing of Status Flags .................................................................... 270

Figure 8.37 Contention between 16TCNT Write and Clear.................................................. 272

Figure 8.38 Contention between 16TCNT Word Write and Increment ................................ 273

Figure 8.39 Contention between 16TCNT Byte Write and Increment.................................. 274

Figure 8.40 Contention between General Register Write and Compare Match .................... 275

Figure 8.41 Contention between 16TCNT Write and Overflow ........................................... 276

Figure 8.42 Contention between General Register Read and Input Capture......................... 277

Figure 8.43 Contention between Counter Clearing by Input Capture and Counter

Increment............................................................................................................ 278

Figure 8.44 Contention between General Register Write and Input Capture........................ 279

Figure 9.1 Block Diagram of 8-Bit Timer Unit (Two Channels: Group 0)......................... 287

Figure 9.2 8TCNT Access Operation (CPU Writes to 8TCNT, Word) .............................. 301

Figure 9.3 8TCNT Access Operation (CPU Reads 8TCNT, Word).................................... 301

Figure 9.4 8TCNT0 Access Operation (CPU Writes to 8TCNT0, Upper Byte)................. 301

Figure 9.5 8TCNT1 Access Operation (CPU Writes to 8TCNT1, Lower Byte) ................ 302

Figure 9.6 8TCNT0 Access Operation (CPU Reads 8TCNT0, Upper Byte)...................... 302

Figure 9.7 8TCNT1 Access Operation (CPU Reads 8TCNT1, Lower Byte)...................... 302

Figure 9.8 Count Timing for Internal Clock Input.............................................................. 303

Figure 9.9 Count Timing for External Clock Input (Both-Edge Detection)........................ 304

Figure 9.10 Timing of Timer Output ..................................................................................... 304

Figure 9.11 Timing of Clear by Compare Match .................................................................. 305

Figure 9.12 Timing of Clear by Input Capture ...................................................................... 305

Figure 9.13 Timing of Input Capture Input Signal ................................................................ 306

Figure 9.14 CMF Flag Setting Timing when Compare Match Occurs.................................. 306

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Figure 9.15 CMFB Flag Setting Timing when Input Capture Occurs .................................. 307

Figure 9.16 Timing of OVF Setting ...................................................................................... 307

Figure 9.17 Example of Pulse Output.................................................................................... 312

Figure 9.18 Contention between 8TCNT Write and Clear.................................................... 313

Figure 9.19 Contention between 8TCNT Write and Increment ............................................ 314

Figure 9.20 Contention between TCOR Write and Compare Match .................................... 315

Figure 9.21 Contention between TCOR Read and Input Capture ......................................... 316

Figure 9.22 Contention between Counter Clearing by Input Capture and Counter

Increment............................................................................................................ 317

Figure 9.23 Contention between TCOR Write and Input Capture ........................................ 318

Figure 9.24 Contention between 8TCNT Byte Write and Increment in 16-Bit Count Mode 319

Figure 10.1 TPC Block Diagram ........................................................................................... 324

Figure 10.2 TPC Output Operation........................................................................................ 339

Figure 10.3 Timing of Transfer of Next Data Register Contents and Output (Example) ..... 340

Figure 10.4 Setup Procedure for Normal TPC Output (Example) ........................................ 341

Figure 10.5 Normal TPC Output Example (Five-Phase Pulse Output)................................. 342

Figure 10.6 Setup Procedure for Non-Overlapping TPC Output (Example) ........................ 343

Figure 10.7 Non-Overlapping TPC Output Example (Four-Phase Complementary

Non-Overlapping Pulse Output)......................................................................... 344

Figure 10.8 TPC Output Triggering by Input Capture (Example) ........................................ 345

Figure 10.9 Non-Overlapping TPC Output ........................................................................... 346

Figure 10.10 Non-Overlapping Operation and NDR Write Timing........................................ 347

Figure 11.1 WDT Block Diagram ......................................................................................... 350

Figure 11.2 Format of Data Written to TCNT and TCSR ..................................................... 355

Figure 11.3 Format of Data Written to RSTCSR .................................................................. 356

Figure 11.4 Operation in Watchdog Timer Mode ................................................................. 357

Figure 11.5 Interval Timer Operation.................................................................................... 358

Figure 11.6 Timing of Setting of OVF .................................................................................. 358

Figure 11.7 Timing of Setting of WRST Bit and Internal Reset ........................................... 359

Figure 11.8 Contention between TCNT Write and Count up................................................ 360

Figure 12.1 SCI Block Diagram ............................................................................................ 363

Figure 12.2 Data Format in Asynchronous Communication

(Example: 8-Bit Data with Parity and 2 Stop Bits)............................................ 391

Figure 12.3 Phase Relationship between Output Clock and Serial Data (Asynchronous

Mode) ................................................................................................................. 393

Figure 12.4 Sample Flowchart for SCI Initialization ............................................................ 394

Figure 12.5 Sample Flowchart for Transmitting Serial Data ................................................ 395

Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode

(8-Bit Data with Parity and One Stop Bit) ......................................................... 396

Figure 12.7 Sample Flowchart for Receiving Serial Data ..................................................... 397

Figure 12.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 400 Figure 12.9 Example of Communication among Processors using Multiprocessor Format

(Sending Data H'AA to Receiving Processor A)................................................ 401

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Figure 12.10 Sample Flowchart for Transmitting Multiprocessor Serial Data ....................... 402

Figure 12.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and

One Stop Bit)...................................................................................................... 403

Figure 12.12 Sample Flowchart for Receiving Multiprocessor Serial Data............................ 404

Figure 12.13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and

One Stop Bit)...................................................................................................... 406

Figure 12.14 Data Format in Synchronous Communication................................................... 407

Figure 12.15 Sample Flowchart for SCI Initialization ............................................................ 408

Figure 12.16 Sample Flowchart for Serial Transmitting......................................................... 409

Figure 12.17 Example of SCI Transmit Operation.................................................................. 410

Figure 12.18 Sample Flowchart for Serial Receiving.............................................................. 411

Figure 12.19 Example of SCI Receive Operation ................................................................... 413

Figure 12.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving .......... 414

Figure 12.21 Receive Data Sampling Timing in Asynchronous Mode................................... 417

Figure 12.22 Example of Synchronous Transmission............................................................. 418

Figure 12.23 Operation when Switching from SCK Pin Function to Port Pin Function......... 419

Figure 12.24 Operation when Switching from SCK Pin Function to Port Pin Function

(Example of Preventing Low-Level Output)...................................................... 420

Figure 13.1 Block Diagram of Smart Card Interface ............................................................ 422

Figure 13.2 Smart Card Interface Connection Diagram........................................................ 430

Figure 13.3 Smart Card Interface Data Format ..................................................................... 431

Figure 13.4 Timing of TEND Flag Setting............................................................................ 437

Figure 13.5 Sample Transmission Processing Flowchart...................................................... 438

Figure 13.6 Relation Between Transmit Operation and Internal Registers ........................... 439

Figure 13.7 Timing of TEND Flag Setting............................................................................ 439

Figure 13.8 Sample Reception Processing Flowchart ........................................................... 440

Figure 13.9 Timing for Fixing Cock Output.......................................................................... 441

Figure 13.10 Procedure for Stopping and Restarting the Clock.............................................. 442

Figure 13.11 Receive Data Sampling Timing in Smart Card Interface Mode ........................ 443

Figure 13.12 Retransmission in SCI Receive Mode................................................................ 445

Figure 13.13 Retransmission in SCI Transmit Mode.............................................................. 445

Figure 14.1 A/D Converter Block Diagram .......................................................................... 448

Figure 14.2 A/D Data Register Access Operation (Reading H'AA40).................................. 455

Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)....... 457

Figure 14.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN

Selected)............................................................................................................. 459

Figure 14.5 A/D Conversion Timing..................................................................................... 460

Figure 14.6 External Trigger Input Timing ........................................................................... 461

Figure 14.7 Example of Analog Input Protection Circuit...................................................... 463

Figure 14.8 Analog Input Pin Equivalent Circuit.................................................................. 463

Figure 14.9 A/D Converter Accuracy Definitions (1) ........................................................... 464

Figure 14.10 A/D Converter Accuracy Definitions (2)........................................................... 465

Figure 14.11 Analog Input Circuit (Example)......................................................................... 466

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Figure 15.1 D/A Converter Block Diagram .......................................................................... 468

Figure 15.2 Example of D/A Converter Operation................................................................ 473

Figure 16.1 RAM Block Diagram ......................................................................................... 476

Figure 17.1 Block Diagram of Flash Memory....................................................................... 481

Figure 17.2 Example of ROM Area/RAM Area Overlap...................................................... 488

Figure 17.3 Boot Mode.......................................................................................................... 491

Figure 17.4 User Program Mode (Example).......................................................................... 492

Figure 17.5 System Configuration When Using Boot Mode ................................................ 493

Figure 17.6 Boot Mode Execution Procedure........................................................................ 494

Figure 17.7 Measurement of Low Period of Host’s Transmit Data ...................................... 495

Figure 17.8 RAM Areas in Boot Mode ................................................................................. 496

Figure 17.9 User Program Mode Execution Procedure (Example) ....................................... 499

Figure 17.10 FLMCR Bit Settings and State Transitions........................................................ 501

Figure 17.11 Program/Program-Verify Flowchart (32-byte Programming)............................ 503

Figure 17.12 Erase/Erase-Verify Flowchart (Single-Block Erasing)...................................... 505

Figure 17.13 Flash Memory State Transitions (Modes 5 and 7 (On-Chip ROM Enabled),

High Level Applied to FWE Pin)....................................................................... 509

Figure 17.14 Example of RAM Overlap Operation ................................................................ 511

Figure 17.15 Memory Map in PROM Mode........................................................................... 514

Figure 17.16 Power-On/Off Timing (Boot Mode) .................................................................. 517

Figure 17.17 Power-On/Off Timing (User Program Mode).................................................... 518

Figure 17.18 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User

Program Mode) .................................................................................................. 519

Figure 17.19 ROM Block Diagram (H8/3062 Mask ROM Version)...................................... 520

Figure 17.20 Mask ROM Addresses and Data........................................................................ 521

Figure 18.1 Block Diagram of Flash Memory....................................................................... 526

Figure 18.2 Flash Memory Related State Transitions ........................................................... 536

Figure 18.3 Reading Overlap RAM Data in User Mode/User Program Mode ..................... 539

Figure 18.4 Writing Overlap RAM Data in User Program Mode ......................................... 540

Figure 18.5 System Configuration When Using Boot Mode ................................................ 542

Figure 18.6 Boot Mode Execution Procedure........................................................................ 543

Figure 18.7 RAM Areas in Boot Mode ................................................................................. 545

Figure 18.8 Example of User Program Mode Execution Procedure ..................................... 548

Figure 18.9 FLMCR1 Bit Settings and State Transitions...................................................... 550

Figure 18.10 Program/Program-Verify Flowchart (128-Byte Programming)......................... 555

Figure 18.11 Erase/Erase-Verify Flowchart (Single-Block Erasing)...................................... 557

Figure 18.12 Flash Memory State Transitions (When High Level is Applied to FWE Pin

in Mode 5 or 7 (On-Chip ROM Enabled))......................................................... 561

Figure 18.13 Flowchart of Flash Memory Emulation in RAM............................................... 562

Figure 18.14 Example of RAM Overlap Operation ................................................................ 563

Figure 18.15 Memory Map in PROM Mode........................................................................... 565

Figure 18.16 Power-On/Off Timing (Boot Mode) .................................................................. 569

Figure 18.17 Power-On/Off Timing (User Program Mode).................................................... 570

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Figure 18.18 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User

Program Mode) .................................................................................................. 571

Figure 18.19 ROM Block Diagram (H8/3064 Mask ROM B-Mask Version)........................ 572

Figure 18.20 Mask ROM Addresses and Data........................................................................ 573

Figure 19.1 Block Diagram of Flash Memory....................................................................... 578

Figure 19.2 Example of ROM Area/RAM Area Overlap...................................................... 586

Figure 19.3 Flash Memory Related State Transitions ........................................................... 588

Figure 19.4 Reading Overlap RAM Data in User Mode/User Program Mode ..................... 591

Figure 19.5 Writing Overlap RAM Data in User Program Mode ......................................... 592

Figure 19.6 System Configuration When Using Boot Mode ................................................ 594

Figure 19.7 Boot Mode Execution Procedure........................................................................ 595

Figure 19.8 RAM Areas in Boot Mode ................................................................................. 597

Figure 19.9 Example of User Program Mode Execution Procedure ..................................... 600

Figure 19.10 FLMCR1 Bit Settings and State Transitions...................................................... 602

Figure 19.11 Program/Program-Verify Flowchart (128-Byte Programming)......................... 607

Figure 19.12 Erase/Erase-Verify Flowchart (Single-Block Erasing)...................................... 609

Figure 19.13 Flash Memory State Transitions (When High Level is Applied to FWE Pin

in Mode 5 or 7 (On-Chip ROM Enabled))......................................................... 613

Figure 19.14 Example of RAM Overlap Operation ................................................................ 614

Figure 19.15 Memory Map in PROM Mode........................................................................... 617

Figure 19.16 Power-On/Off Timing (Boot Mode) .................................................................. 621

Figure 19.17 Power-On/Off Timing (User Program Mode).................................................... 622

Figure 19.18 Mode Transition Timing (Example: Boot Mode → User Mode ↔ User

Program Mode) .................................................................................................. 623

Figure 19.19 ROM Block Diagram (H8/3062 Mask ROM B-Mask Version)........................ 624

Figure 19.20 Mask ROM Addresses and Data........................................................................ 625

Figure 20.1 Block Diagram of Clock Pulse Generator.......................................................... 627

Figure 20.2 Connection of Crystal Resonator (Example)...................................................... 628

Figure 20.3 Crystal Resonator Equivalent Circuit................................................................. 629

Figure 20.4 Oscillator Circuit Block Board Design Precautions........................................... 629

Figure 20.5 External Clock Input (Examples) ....................................................................... 630

Figure 20.6 External Clock Input Timing.............................................................................. 632

Figure 20.7 External Clock Output Settling Delay Timing ................................................... 632

Figure 21.1 NMI Timing for Software Standby Mode (Example)........................................ 645

Figure 21.2 Hardware Standby Mode Timing ....................................................................... 647

Figure 21.3 Starting and Stopping of System Clock Output ................................................. 649

Figure 22.1 Darlington Pair Drive Circuit (Example) ........................................................... 662

Figure 22.2 Sample LED Circuit ........................................................................................... 663

Figure 22.3 Output Load Circuit............................................................................................ 669

Figure 22.4 Darlington Pair Drive Circuit (Example) ........................................................... 680

Figure 22.5 Sample LED Circuit ........................................................................................... 681

Figure 22.6 Output Load Circuit............................................................................................ 687

Figure 22.7 Darlington Pair Drive Circuit (Example) ........................................................... 699

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Figure 22.8 Sample LED Circuit ........................................................................................... 700

Figure 22.9 Output Load Circuit............................................................................................ 706

Figure 22.10 Darlington Pair Drive Circuit (Example)........................................................... 715

Figure 22.11 Sample LED Circuit........................................................................................... 715

Figure 22.12 Output Load Circuit............................................................................................ 721

Figure 22.13 Darlington Pair Drive Circuit (Example)........................................................... 728

Figure 22.14 Sample LED Circuit........................................................................................... 729

Figure 22.15 Output Load Circuit............................................................................................ 735

Figure 22.16 Darlington Pair Drive Circuit (Example)........................................................... 744

Figure 22.17 Sample LED Circuit........................................................................................... 744

Figure 22.18 Output Load Circuit............................................................................................ 750

Figure 22.19 Oscillator Settling Timing.................................................................................. 753

Figure 22.20 Reset Input Timing............................................................................................. 754

Figure 22.21 Reset Output Timing.......................................................................................... 754

Figure 22.22 Interrupt Input Timing........................................................................................ 755

Figure 22.23 Basic Bus Cycle: Two-State Access .................................................................. 757

Figure 22.24 Basic Bus Cycle: Three-State Access ................................................................ 758

Figure 22.25 Basic Bus Cycle: Three-State Access with One Wait State............................... 759

Figure 22.26 Bus-Release Mode Timing................................................................................. 759

Figure 22.27 TPC and I/O Port Input/Output Timing.............................................................. 760

Figure 22.28 Timer Input/Output Timing................................................................................ 760

Figure 22.29 Timer External Clock Input Timing................................................................... 761

Figure 22.30 SCI Input Clock Timing..................................................................................... 761

Figure 22.31 SCI Input/Output Timing in Synchronous Mode............................................... 761

Figure C.1 Port 1 Block Diagram......................................................................................... 896

Figure C.2 Port 2 Block Diagram......................................................................................... 897

Figure C.3 Port 3 Block Diagram......................................................................................... 898

Figure C.4 Port 4 Block Diagram......................................................................................... 899

Figure C.5 Port 5 Block Diagram......................................................................................... 900

Figure C.6 (a) Port 6 Block Diagram (Pin P60).......................................................................... 901

Figure C.6 (b) Port 6 Block Diagram (Pin P61).......................................................................... 902

Figure C.6 (c) Port 6 Block Diagram (Pin P62).......................................................................... 903

Figure C.6 (d) Port 6 Block Diagram (Pins P63 to P66)............................................................. 904

Figure C.6 (e) Port 6 Block Diagram (Pin P67).......................................................................... 905

Figure C.7 (a) Port 7 Block Diagram (Pins P70 to P75).............................................................. 906

Figure C.7 (b) Port 7 Block Diagram (Pins P76 and P77)........................................................... 906

Figure C.8 (a) Port 8 Block Diagram (Pin P80).......................................................................... 907

Figure C.8 (b) Port 8 Block Diagram (Pins P81 and P82)........................................................... 908

Figure C.8 (c) Port 8 Block Diagram (Pin P83).......................................................................... 909

Figure C.8 (d) Port 8 Block Diagram (Pin P84).......................................................................... 910

Figure C.9 (a) Port 9 Block Diagram (Pin P90).......................................................................... 911

Figure C.9 (b) Port 9 Block Diagram (Pin P91).......................................................................... 912

Figure C.9 (c) Port 9 Block Diagram (Pin P92).......................................................................... 913

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Figure C.9 (d) Port 9 Block Diagram (Pin P93).......................................................................... 914

Figure C.9 (e) Port 9 Block Diagram (Pin P94).......................................................................... 915

Figure C.9 (f) Port 9 Block Diagram (Pin P95).......................................................................... 916

Figure C.10 (a) Port A Block Diagram (Pins PA0 and PA1)........................................................ 917

Figure C.10 (b) Port A Block Diagram (Pins PA2 and PA3)........................................................ 918

Figure C.10 (c) Port A Block Diagram (Pins PA4 to PA7).......................................................... 919

Figure C.11 (a) Port B Block Diagram (Pins PB0 and PB2)......................................................... 920

Figure C.11 (b) Port B Block Diagram (Pins PB1 and PB3)......................................................... 921

Figure C.11 (c) Port B Block Diagram (Pin PB4)........................................................................ 922

Figure C.11 (d) Port B Block Diagram (Pin PB5)........................................................................ 923

Figure C.11 (e) Port B Block Diagram (Pin PB6)........................................................................ 924

Figure C.11 (f) Port B Block Diagram (Pin PB7)........................................................................ 925

Figure D.1 Reset during Memory Access (Modes 1 and 2)................................................. 930

Figure D.2 Reset during Memory Access (Modes 3 and 4)................................................. 931

Figure D.3 Reset during Memory Access (Mode 5) ............................................................ 932

Figure D.4 Reset during Operation (Modes 6 and 7)........................................................... 932

Figure G.1 Package Dimensions (FP-100B)........................................................................ 936

Figure G.2 Package Dimensions (TFP-100B)...................................................................... 937

Figure G.3 Package Dimensions (FP-100A)........................................................................ 938

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Tables

Table 1.1 Features................................................................................................................ 2

Table 1.2 Comparison of H8/3062 Series Pin Arrangements.............................................. 8

Table 1.3 Pin Functions........................................................................................................ 13

Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A) .................. 18

Table 1.5 Differences in H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version

Markings............................................................................................................... 23

Table 1.6 Differences between H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,

and On-Chip Mask ROM Versions...................................................................... 24

Table 1.7 Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT B-Mask

Version, and H8/3064F-ZTAT B-Mask Version Markings................................. 25

Table 2.1 Instruction Classification...................................................................................... 39

Table 2.2 Instructions and Addressing Modes..................................................................... 40

Table 2.3 Data Transfer Instructions.................................................................................... 42

Table 2.4 Arithmetic Operation Instructions........................................................................ 43

Table 2.5 Logic Operation Instructions................................................................................ 45

Table 2.6 Shift Instructions.................................................................................................. 45

Table 2.7 Bit Manipulation Instructions............................................................................... 46

Table 2.8 Branching Instructions.......................................................................................... 48

Table 2.9 System Control Instructions................................................................................. 49

Table 2.10 Block Transfer Instruction.................................................................................... 50

Table 2.11 Addressing Modes................................................................................................ 53

Table 2.12 Absolute Address Access Ranges ........................................................................ 54

Table 2.13 Effective Address Calculation.............................................................................. 56

Table 2.14 Exception Handling Types and Priority ............................................................... 60

Table 3.1 Operating Mode Selection.................................................................................... 67

Table 3.2 Registers............................................................................................................... 68

Table 3.3 Pin Functions in Each Mode................................................................................ 73

Table 3.4 Address Maps in Mode 5...................................................................................... 74

Table 4.1 Exception Types and Priority............................................................................... 85

Table 4.2 Exception Vector Table........................................................................................ 87

Table 5.1 Interrupt Pins........................................................................................................99

Table 5.2 Interrupt Controller Registers............................................................................... 99

Table 5.3 Interrupt Sources, Vector Addresses, and Priority............................................... 110

Table 5.4 UE, I, and UI Bit Settings and Interrupt Handling............................................... 113

Table 5.5 Interrupt Response Time...................................................................................... 119

Table 6.1 Bus Controller Pins.............................................................................................. 125

Table 6.2 Bus Controller Registers...................................................................................... 126

Table 6.3 Bus Specifications for Each Area (Basic Bus Interface)...................................... 141

Table 6.4 Data Buses Used and Valid Strobes..................................................................... 146

Table 6.5 Pin States in Idle Cycle........................................................................................ 159

Table 7.1 Port Functions ...................................................................................................... 165

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Table 7.2 Port 1 Registers.................................................................................................... 169

Table 7.3 Port 2 Registers.................................................................................................... 173

Table 7.4 Input Pull-Up Transistor States (Port 2)............................................................... 175

Table 7.5 Port 3 Registers.................................................................................................... 176

Table 7.6 Port 4 Registers.................................................................................................... 179

Table 7.7 Input Pull-Up Transistor States (Port 4)............................................................... 181

Table 7.8 Port 5 Registers.................................................................................................... 182

Table 7.9 Input Pull-Up Transistor States (Port 5)............................................................... 184

Table 7.10 Port 6 Registers .................................................................................................... 185

Table 7.11 Port 6 Pin Functions in Modes 1 to 5 ................................................................... 187

Table 7.12 Port 7 Data Register.............................................................................................. 189

Table 7.13 Port 8 Registers .................................................................................................... 191

Table 7.14 Port 8 Pin Functions in Modes 1 to 5 ................................................................... 193

Table 7.15 Port 8 Pin Functions in Modes 6 and 7 ................................................................ 194

Table 7.16 Port 9 Registers .................................................................................................... 196

Table 7.17 Port 9 Pin Functions ............................................................................................. 198

Table 7.18 Port A Registers.................................................................................................... 202

Table 7.19 Port A Pin Functions (Modes 1, 2, 6, and 7)........................................................ 204

Table 7.20 Port A Pin Functions (Modes 3 to 5).................................................................... 206

Table 7.21 Port A Pin Functions (Modes 1 to 7).................................................................... 209

Table 7.22 Port B Registers.................................................................................................... 214

Table 7.23 Port B Pin Functions (Modes 1 to 5).................................................................... 216

Table 7.24 Port B Pin Functions (Modes 6 and 7) ................................................................. 218

Table 8.1 16-bit timer Functions.......................................................................................... 222

Table 8.2 16-bit timer Pins................................................................................................... 226

Table 8.3 16-bit timer Registers........................................................................................... 227

Table 8.4 PWM Output Pins and Registers.......................................................................... 261

Table 8.5 Up/Down Counting Conditions............................................................................ 266

Table 8.6 16-bit timer Interrupt Sources.............................................................................. 271

Table 8.7 (a) 16-bit timer Operating Modes (Channel 0).......................................................... 281

Table 8.7 (b) 16-bit timer Operating Modes (Channel 1).......................................................... 282

Table 8.7 (c) 16-bit timer Operating Modes (Channel 2).......................................................... 283

Table 9.1 8-Bit Timer Pins................................................................................................... 288

Table 9.2 8-Bit Timer Registers........................................................................................... 289

Table 9.3 Operation of Channels 0 and 1 when Bit ICE is Set to 1 in 8TCSR1 Register.... 299

Table 9.4 Operation of Channels 2 and 3 when Bit ICE is Set to 1 in 8TCSR3 Register.... 299

Table 9.5 Types of 8-Bit Timer Interrupt Sources and Priority Order................................. 311

Table 9.6 8-Bit Timer Interrupt Sources.............................................................................. 311

Table 9.7 Timer Output Priority Order ................................................................................ 320

Table 9.8 Internal Clock Switchover and 8TCNT Operation .............................................. 321

Table 10.1 TPC Pins............................................................................................................... 325

Table 10.2 TPC Registers....................................................................................................... 326

Table 10.3 TPC Operating Conditions ................................................................................... 339

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Table 11.1 WDT Pin .............................................................................................................. 350

Table 11.2 WDT Registers..................................................................................................... 351

Table 11.3 Read Addresses of TCNT, TCSR, and RSTCSR................................................. 356

Table 12.1 SCI Pins................................................................................................................ 364

Table 12.2 SCI Registers........................................................................................................ 365

Table 12.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode...................... 381

Table 12.4 Examples of Bit Rates and BRR Settings in Synchronous Mode........................ 384

Table 12.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode)................. 386

Table 12.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode).............. 387

Table 12.7 Maximum Bit Rates with External Clock Input (Synchronous Mode)................ 388

Table 12.8 SMR Settings and Serial Communication Formats.............................................. 390

Table 12.9 SMR and SCR Settings and SCI Clock Source Selection.................................... 390

Table 12.10 Serial Communication Formats (Asynchronous Mode)....................................... 392

Table 12.11 Receive Error Conditions..................................................................................... 399

Table 12.12 SCI Interrupt Sources........................................................................................... 415

Table 12.13 SSR Status Flags and Transfer of Receive Data.................................................. 416

Table 13.1 Smart Card Interface Pins .................................................................................... 422

Table 13.2 Smart Card Interface Registers ............................................................................ 423

Table 13.3 Smart Card Interface Register Settings................................................................ 432

Table 13.4 n-Values of CKS1 and CKS0 Settings................................................................. 434

Table 13.5 Bit Rates (bits/s) for Various BRR Settings (When n = 0) .................................. 434

Table 13.6 BRR Settings for Typical Bit Rates (bits/s) (When n = 0)................................... 435

Table 13.7 Maximum Bit Rates for Various Frequencies (Smart Card Interface Mode) ...... 435

Table 13.8 Smart Card Interface Mode Operating States and Interrupt Sources ................... 441

Table 14.1 A/D Converter Pins.............................................................................................. 449

Table 14.2 A/D Converter Registers...................................................................................... 450

Table 14.3 Analog Input Channels and A/D Data Registers (ADDRA to ADDRD) ............ 451

Table 14.4 A/D Conversion Time (Single Mode).................................................................. 461

Table 14.5 Analog Input Pin Ratings ..................................................................................... 463

Table 15.1 D/A Converter Pins.............................................................................................. 469

Table 15.2 D/A Converter Registers...................................................................................... 469

Table 16.1 H8/3062 Series On-Chip RAM Specifications .................................................... 475

Table 16.2 System Control Register....................................................................................... 476

Table 17.1 Operating Modes and ROM ................................................................................. 479

Table 17.2 Flash Memory Pins............................................................................................... 482

Table 17.3 Flash Memory Registers....................................................................................... 482

Table 17.4 Flash Memory Erase Blocks ................................................................................ 487

Table 17.5 RAM Area Setting................................................................................................ 488

Table 17.6 On-Board Programming Mode Settings............................................................... 490

Table 17.7 System Clock Frequencies for which Automatic Adjustment of MCU Bit Rate

is Possible............................................................................................................. 495

Table 17.8 Hardware Protection............................................................................................. 506

Table 17.9 Software Protection.............................................................................................. 508

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Table 17.10 H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version Socket Adapter

Product Codes ...................................................................................................... 513

Table 18.1 Operating Modes and ROM ................................................................................. 523

Table 18.2 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version....... 524

Table 18.3 Flash Memory Pins............................................................................................... 527

Table 18.4 Flash Memory Registers....................................................................................... 527

Table 18.5 Flash Memory Erase Blocks ................................................................................ 533

Table 18.6 Flash Memory Area Divisions.............................................................................. 534

Table 18.7 On-Board Programming Mode Settings............................................................... 541

Table 18.8 System Clock Frequencies for which Automatic Adjustment of

H8/3064F-ZTAT B-mask version Bit Rate is Possible........................................ 544

Table 18.9 Hardware Protection............................................................................................. 558

Table 18.10 Software Protection.............................................................................................. 559

Table 18.11 H8/3064F-ZTAT B-Mask Version Socket Adapter Product Codes .................... 565

Table 19.1 Operating Modes and ROM ................................................................................. 575

Table 19.2 Differences from H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version....... 576

Table 19.3 Flash Memory Pins............................................................................................... 579

Table 19.4 Flash Memory Registers....................................................................................... 579

Table 19.5 Flash Memory Erase Blocks................................................................................. 585

Table 19.6 RAM Area Setting................................................................................................ 586

Table 19.7 On-Board Programming Mode Settings............................................................... 593

Table 19.8 System Clock Frequencies for which Automatic Adjustment of

H8/3062F-ZTAT B-Mask Version Bit Rate is Possible ...................................... 596

Table 19.9 Hardware Protection............................................................................................. 610

Table 19.10 Software Protection.............................................................................................. 611

Table 19.11 H8/3062F-ZTAT B-Mask Version Socket Adapter Product Codes .................... 616

Table 20.1 (1) Damping Resistance Value .................................................................................. 628

Table 20.1 (2) External Capacitance Values................................................................................ 628

Table 20.2 Crystal Resonator Parameters .............................................................................. 629

Table 20.3 (1) Clock Timing for On-Chip Flash Memory Versions ........................................... 631

Table 20.3 (2) Clock Timing for On-Chip Mask ROM Versions................................................ 631

Table 20.4 Frequency Division Register................................................................................ 633

Table 20.5 Comparison of H8/3062 Series Operating Frequency Ranges............................. 634

Table 21.1 Power-Down State and Module Standby Function.............................................. 636

Table 21.2 Control Register.................................................................................................... 637

Table 21.3 Clock Frequency and Waiting Time for Clock to Settle...................................... 644

Table 21.4 φ Pin State in Various Operating States ............................................................... 649

Table 22.1 Electrical Characteristics of H8/3062 Series Products......................................... 651

Table 22.2 Absolute Maximum Ratings................................................................................. 652

Table 22.3 DC Characteristics (1).......................................................................................... 653

Table 22.3 DC Characteristics (2).......................................................................................... 656

Table 22.3 DC Characteristics (3).......................................................................................... 659

Table 22.4 Permissible Output Currents ................................................................................ 662

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Table 22.5 Clock Timing........................................................................................................ 664

Table 22.6 Control Signal Timing.......................................................................................... 665

Table 22.7 Bus Timing........................................................................................................... 666

Table 22.8 Timing of On-Chip Supporting Modules ............................................................. 668

Table 22.9 A/D Conversion Characteristics........................................................................... 670

Table 22.10 D/A Conversion Characteristics........................................................................... 672

Table 22.11 Absolute Maximum Ratings................................................................................. 673

Table 22.12 DC Characteristics (1).......................................................................................... 674

Table 22.12 DC Characteristics (2).......................................................................................... 677

Table 22.13 Permissible Output Currents ................................................................................ 680

Table 22.14 Clock Timing........................................................................................................ 682

Table 22.15 Control Signal Timing.......................................................................................... 683

Table 22.16 Bus Timing........................................................................................................... 684

Table 22.17 Timing of On-Chip Supporting Modules............................................................. 686

Table 22.18 A/D Conversion Characteristics........................................................................... 688

Table 22.19 D/A Conversion Characteristics........................................................................... 690

Table 22.20 Flash Memory Characteristics (1)........................................................................ 691

Table 22.20 Flash Memory Characteristics (2)........................................................................ 693

Table 22.21 Absolute Maximum Ratings................................................................................. 695

Table 22.22 DC Characteristics................................................................................................ 696

Table 22.23 Permissible Output Currents ................................................................................ 699

Table 22.24 Clock Timing........................................................................................................ 701

Table 22.25 Control Signal Timing.......................................................................................... 702

Table 22.26 Bus Timing........................................................................................................... 703

Table 22.27 Timing of On-Chip Supporting Modules............................................................. 705

Table 22.28 A/D Conversion Characteristics........................................................................... 707

Table 22.29 D/A Conversion Characteristics........................................................................... 708

Table 22.30 Flash Memory Characteristics.............................................................................. 709

Table 22.31 Absolute Maximum Ratings................................................................................. 711

Table 22.32 DC Characteristics ............................................................................................... 712

Table 22.33 Permissible Output Currents ................................................................................ 714

Table 22.34 Clock Timing........................................................................................................ 716

Table 22.35 Control Signal Timing.......................................................................................... 717

Table 22.36 Bus Timing........................................................................................................... 718

Table 22.37 Timing of On-Chip Supporting Modules............................................................. 720

Table 22.38 A/D Conversion Characteristics........................................................................... 722

Table 22.39 D/A Conversion Characteristics........................................................................... 723

Table 22.40 Absolute Maximum Ratings................................................................................. 724

Table 22.41 DC Characteristics................................................................................................ 725

Table 22.42 Permissible Output Currents ................................................................................ 728

Table 22.43 Clock Timing........................................................................................................ 730

Table 22.44 Control Signal Timing.......................................................................................... 731

Table 22.45 Bus Timing........................................................................................................... 732

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Table 22.46 Timing of On-Chip Supporting Modules............................................................. 734

Table 22.47 A/D Conversion Characteristics........................................................................... 736

Table 22.48 D/A Conversion Characteristics........................................................................... 737

Table 22.49 Flash Memory Characteristics.............................................................................. 738

Table 22.50 Absolute Maximum Ratings................................................................................. 740

Table 22.51 DC Characteristics ............................................................................................... 741

Table 22.52 Permissible Output Currents ................................................................................ 743

Table 22.53 Clock Timing........................................................................................................ 745

Table 22.54 Control Signal Timing.......................................................................................... 746

Table 22.55 Bus Timing........................................................................................................... 747

Table 22.56 Timing of On-Chip Supporting Modules............................................................. 749

Table 22.57 A/D Conversion Characteristics........................................................................... 751

Table 22.58 D/A Conversion Characteristics........................................................................... 752

Table A.1 Instruction Set ...................................................................................................... 765

Table A.2 Operation Code Map (1) ...................................................................................... 778

Table A.2 Operation Code Map (2) ...................................................................................... 779

Table A.2 Operation Code Map (3) ...................................................................................... 780

Table A.3 Number of States per Cycle.................................................................................. 782

Table A.4 Number of Cycles per Instruction ........................................................................ 783

Table B.1 Comparison of H8/3062 Series Internal I/O Register Specifications .................. 790

Table D.1 Port States............................................................................................................. 926

Table F.1 H8/3062 Series ..................................................................................................... 934

Table H.1 Pin Arrangement of Each Product (FP-100B, TFP-100B)................................... 942

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Section 1 Overview

1.1 Overview

The H8/3062 Series is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Hitachi architecture.

The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series.

The on-chip system supporting functions include ROM, RAM, a 16-bit timer, an 8-bit timer, a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, and other facilities.

The 11 members of the H8/3062 Series are the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 (mask ROM version), H8/3061 (mask ROM version), H8/3060 (mask ROM version), H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version.

Seven MCU operating modes offer a choice of bus width and address space size. The modes (modes 1 to 7) include two single-chip modes and five expanded modes.

In addition to its mask ROM versions, the H8/3062 Series has F-ZTAT™* versions with on-chip flash memory that allows programs to be freely rewritten by the user. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions.

Table 1.1 summarizes the features of the H8/3062 Series.

Note: * F-ZTATTM (Flexible ZTAT) is a trademark of Hitachi, Ltd.

Page 50

Table 1.1 Features

Feature Description

CPU Upward-compatible with the H8/300 CPU at the object-code level

General-register machine

• Sixteen 16-bit general registers (also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight 32-bit registers)

High-speed operation

H8/3062F-ZTAT H8/3062F-ZTAT R-Mask version H8/3062 (mask ROM version) H8/3061 (mask ROM version) H8/3060 (mask ROM version)

H8/3064F-ZTAT B-mask version H8/3062F-ZTAT B-mask version H8/3064 mask ROM B-mask version H8/3062 mask ROM B-mask version H8/3061 mask ROM B-mask version H8/3060 mask ROM B-mask version

Maximum clock rate

20 MHz 100 ns 700 ns

25 MHz 80 ns 560 ns

Add/ subtract

Multiply/ divide

16-Mbyte address space Instruction features

• 8/16/32-bit data transfer, arithmetic, and logic instructions

• Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)

• Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)

• Bit accumulator function

• Bit manipulation instructions with register-indirect specification of bit positions

Page 51

Feature Description

Memory ROM RAM

H8/3062F-ZTAT

128 kbytes 4 kbytes H8/3062F-ZTAT R-mask version H8/3062F-ZTAT B-mask version H8/3062 (mask ROM version) H8/3062 mask ROM B-mask version

H8/3061 (mask ROM version)

96 kbytes 4 kbytes H8/3061 mask ROM B-mask version

H8/3060 (mask ROM version)

64 kbytes 2 kbytes H8/3060 mask ROM B-mask version

H8/3064F-ZTAT B-mask version

256 kbytes 8 kbytes H8/3064 mask ROM B-mask version

Interrupt controller

Bus controller

16-bit timer, 3 channels

• Seven external interrupt pins: NMI, IRQ

to IRQ

• 27 internal interrupts

• Three selectable interrupt priority levels

• Address space can be partitioned into eight areas, with independent bus

specifications in each area

• Chip select output available for areas 0 to 7

• 8-bit access or 16-bit access selectable for each area

• Two-state or three-state access selectable for each area

• Selection of two wait modes

• Number of program wait states selectable for each area

• Bus arbitration function

• Two address update modes (not available in the H8/3062F-ZTAT)

• Three 16-bit timer channels, capable of processing up to six pulse outputs or

six pulse inputs

• 16-bit timer counter (channels 0 to 2)

• Two multiplexed output compare/input capture pins (channels 0 to 2)

• Operation can be synchronized (channels 0 to 2)

• PWM mode available (channels 0 to 2)

• Phase counting mode available (channel 2)

Page 52

Feature Description

8-bit timer, 4 channels

• 8-bit up-counter (external event count capability)

• Two time constant registers

• Two channels can be connected

Programmable timing pattern controller (TPC)

Watchdog timer (WDT), 1 channel

Serial communication interface (SCI), 2 channels

A/D converter

D/A converter

• Maximum 16-bit pulse output, using 16-bit timer as time base

• Up to four 4-bit pulse output groups (or one 16-bit group, or two 8-bit groups)

• Non-overlap mode available

• Internal reset signal can be generated by overflow

• Reset signal can be output externally (not available in on-chip flash memory

versions)

• Usable as an interval timer

• Selection of asynchronous or synchronous mode

• Full duplex: can transmit and receive simultaneously

• On-chip baud-rate generator

• Smart card interface extended functions added

• Resolution: 10 bits

• Eight channels, with selection of single or scan mode

• Variable analog conversion voltage range

• Sample-and-hold function

• A/D conversion can be started by an external trigger or 8-bit timer compare-

match

• Resolution: 8 bits

• Two channels

• D/A outputs can be sustained in software standby mode

I/O ports

• 70 input/output pins

• 9 input-only pins

Page 53

Feature Description

Operating modes Seven MCU operating modes

Address

Mode

Space

Mode 1 1 Mbyte A Mode 2 1 Mbyte A19 to A Mode 3 16 Mbytes A23 to A Mode 4 16 Mbytes A23 to A Mode 5 16 Mbytes A23 to A Mode 6 64 kbytes — — — Mode 7 1 Mbyte — — —

• On-chip ROM is disabled in modes 1 to 4

• In the versions with on-chip flash memory, an on-board programming mode is

supported that allows flash memory to be programmed in modes 5 and 7.

Address Pins

to A

Initial Bus Width

8 bits 16 bits 16 bits 16 bits 8 bits 16 bits 16 bits 16 bits 8 bits 16 bits

Max. Bus Width

Power-down state

Other features

• Sleep mode

• Software standby mode

• Hardware standby mode

• Module standby function

• Programmable system clock frequency division

• On-chip clock pulse generator

Page 54

Feature Description

Product lineup

Product Type Model

H8/3062F-ZTAT 5 V operation HD64F3062F 100-pin QFP (FP-100B)

H8/3062F-ZTAT 5 V operation HD64F3062RF 100-pin QFP (FP-100B) R-mask version

H8/3062 mask 5 V operation HD6433062F 100-pin QFP (FP-100B) ROM version

H8/3061 mask 5 V operation HD6433061F 100-pin QFP (FP-100B) ROM version

H8/3060 mask 5 V operation HD6433060F 100-pin QFP (FP-100B) ROM version

H8/3064F-ZTAT 5 V operation HD64F3064BF 100-pin QFP (FP-100B) B-mask version

H8/3064 mask ROM 5 V operation HD6433064BF 100-pin QFP (FP-100B) B-mask version

H8/3062F-ZTAT 5 V operation HD64F3062BF 100-pin QFP (FP-100B) B-mask version

H8/3062 mask ROM 5 V operation HD6433062BF 100-pin QFP (FP-100B) B-mask version

H8/3061 mask ROM 5 V operation HD6433061BF 100-pin QFP (FP-100B) B-mask version

H8/3060 mask ROM 5 V operation HD6433060BF 100-pin QFP (FP-100B) B-mask version

Package (Hitachi Package Code)

HD64F3062TE 100-pin TQFP (TFP-100B) HD64F3062FP 100-pin QFP (FP-100A)

HD64F3062RTE 100-pin TQFP (TFP-100B) HD64F3062RFP 100-pin QFP (FP-100A)

3 V operation HD64F3062RVF 100-pin QFP (FP-100B)

HD64F3062RVTE 100-pin TQFP (TFP-100B) HD64F3062RVFP 100-pin QFP (FP-100A)

HD6433062TE 100-pin TQFP (TFP-100B) HD6433062FP 100-pin QFP (FP-100A)

3 V operation HD6433062VF 100-pin QFP (FP-100B)

HD6433062VTE 100-pin TQFP (TFP-100B) HD6433062VFP 100-pin QFP (FP-100A)

HD6433061TE 100-pin TQFP (TFP-100B) HD6433061FP 100-pin QFP (FP-100A)

3 V operation HD6433061VF 100-pin QFP (FP-100B)

HD6433061VTE 100-pin TQFP (TFP-100B) HD6433061VFP 100-pin QFP (FP-100A)

HD6433060TE 100-pin TQFP (TFP-100B) HD6433060FP 100-pin QFP (FP-100A)

3 V operation HD6433060VF 100-pin QFP (FP-100B)

HD6433060VTE 100-pin TQFP (TFP-100B) HD6433060VFP 100-pin QFP (FP-100A)

HD64F3064BTE 100-pin TQFP (TFP-100B) HD64F3064BFP 100-pin QFP (FP-100A)

HD6433064BTE 100-pin TQFP (TFP-100B) HD6433064BFP 100-pin QFP (FP-100A)

HD64F3062BTE 100-pin TQFP (TFP-100B) HD64F3062BFP 100-pin QFP (FP-100A)

HD6433062BTE 100-pin TQFP (TFP-100B) HD6433062BFP 100-pin QFP (FP-100A)

HD6433061BTE 100-pin TQFP (TFP-100B) HD6433061BFP 100-pin QFP (FP-100A)

HD6433060BTE 100-pin TQFP (TFP-100B) HD6433060BFP 100-pin QFP (FP-100A)

Page 55

1.2 Block Diagram

Figure 1.1 shows an internal block diagram.

ADTRG/CS

RESO/FWE

HWR/P6

BACK/P6

BREQ/P6

WAIT/P6

/IRQ3/P83

/IRQ2/P82

/IRQ1/P81

MD MD MD

EXTAL

XTAL STBY

RES

NMI

φ/P6

LWR/P66

RD/P6 AS/P6

CS0/P84

IRQ

/P80

CL*2CCCCSSSSSSSSSS

VVVVVVVVV

1514131211109 7654321

P3 /D

8 0

P3 /D

P4 /D

7654321 7654321

P4 /D

0 0

P4 /D

Port 3 Port 4

Address bus

2 1 0

Data bus (upper)

Data bus (lower)

H8/300H CPU

5 4 3

Port 6

2 1 0

generator

Clock pulse

Interrupt controller

ROM (mask ROM or flash memory)

Bus controller

RAM

Watchdog timer

(WDT)

Port 8

16-bit timer unit

8-bit timer unit

Programmable

timing pattern

controller (TPC)

Serial communication

interface

(SCI) 2 channels

A/D converter

D/A converter

P5 /A P5 /A P5 /A

Port 5Port 9

P5 /A

P2 /A P2 /A P2 /A P2 /A P2 /A

Port 2

P2 /A P2 /A P2 /A

P1 /A P1 /A P1 /A P1 /A P1 /A

Port 1

P1 /A P1 /A P1 /A

P9 /SCK /IRQ P9 /SCK /IRQ P9 /RxD P9 /RxD P9 /TxD P9 /TxD

/PB TP

/PA

/TP

/TIOCB

/TIOCA

6 2

Port A

/PA

/TP

/TIOCB

/TIOCA

/PA

/TP

TCLKD/TIOCB

TCLKC/TIOCA

/PA

TCLKB/TP

TCLKA/TP

REF

Port B

/PB

/PB TP

/PB

/TP

/TMO

/TMIO

/TMO

/TMIO

/P7 /AN

Port 7

/P7

/AN

/P7

Notes: *1 Functions as RESO in the on-chip mask ROM versions, and as FWE in the on-chip flash memory versions.

*2 The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version,

H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version have a V

pin, and require the connection of an external capacitor.

Figure 1.1 Block Diagram

Page 56

1.3 Pin Description

1.3.1 Pin Arrangement

The pin arrangement of the H8/3062 Series is shown in figures 1.2 to 1.5. Differences in the H8/3062 Series pin arrangements are shown in table 1.2. The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version have a VCL pin. See section 1.5, Notes on H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version. Except for the differences shown in table 1.2, the pin arrangements are the same.

Table 1.2 Comparison of H8/3062 Series Pin Arrangements

Package Pin

Number

H8/3062F-ZTAT

R-Mask Version

FP-100B 1 V

H8/3062F-ZTAT,

(TFP-100B)

10 FWE RESO RESO RESO FWE FWE

FP-100A 3 V

12 FWE RESO RESO RESO FWE FWE

Package Pin

Number

FP-100B 1 V

(TFP-100B)

10 RESO RESO RESO RESO

FP-100A 3 V

12 RESO RESO RESO RESO

H8/3064

Mask ROM

B-Mask

Version

H8/3062

Mask ROM

Version

H8/3062

Mask ROM

B-Mask

Version

H8/3061

Mask ROM

Version

H8/3061

Mask ROM

B-Mask

Version

H8/3060

Mask ROM

Version

H8/3060

Mask ROM

B-Mask

Version

H8/3064

F-ZTAT

B-Mask Version

H8/3062

F-ZTAT

B-Mask Version

Page 57

P7 /AN

P7 /AN /DA

/P8 IRQ

/P8 /IRQCS

CS2/IRQ2/P8

ADTRG/CS1/IRQ3/P8

CS0/P8

TCLKA/TP0/PA

TCLKB/TP1/PA TCLKC/TIOCA0/TP2/PA TCLKD/TIOCB0/TP3/PA

A23/TIOCA1/TP4/PA A22/TIOCB1/TP5/PA A21/TIOCA2/TP6/PA A20/TIOCB2/TP7/PA

REF

210

654

MDMDMD

P6 /LWR

P6 /HWR

P6 /RD

P6 /ASVXTAL

75747372717069686766656463626160595857565554535251

EXTALVNMI

RES

STBY

/φ

210

P6 /BACK

P6 /BREQ

P6 /WAITVP5 /A

77 78

87 88

100

12345678910111213141516171819202122232425

/PB

/TP

/TMO

/ TMIO

/TMO

/PB

/TP

/ TMIO

/PB

/PB TP

/PB

Top view

(FP-100B, TFP-100B)

012345012

/PB

010101012

FWE

/RESO

TxD /P9

RxD /P9

IRQ /SCK /P9

D /P4

IRQ /SCK /P9

1918171615 32107

P5 /A

3 3

D /P4

P5 /A

P2 /A

456 456

D /P4

14 6

P2 /A

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

D /P4

A /P2

A /P1

D /P3

D /P4

5 4 3 2 1 0

7 6 5 4 3 2 1 0

7 6

5 4 3 2 1 0 7

Note: * Functions as RESO in the on-chip mask ROM versions, and as FWE in the on-chip flash memory

versions.

Figure 1.2 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

and H8/3060 Mask ROM Version

(FP-100B or TFP-100B Package, Top View)

Page 58

/AN

REF

/LWR

AVCCMD2MD1MD0P6

/HWR

/RD

/AS

XTAL

EXTAL

VSSNMI

RES

/φ

STBY

/BACK

/BREQ

/WAIT

/A P5

/A P2

P71/AN P72/AN P73/AN P74/AN

P75/AN P76/AN6/DA P77/AN7/DA

P80/IRQ P81/IRQ1/CS P82/IRQ2/CS

P83/IRQ3/CS1/ADTRG

/TP2/TIOCA0/TCLKC

/TP3/TIOCB0/TCLKD

PA PA5/TP5/TIOCB1/A

PA0/TP0/TCLKA PA

/TP1/TCLKB

/TP4/TIOCA1/A

/CS

8079787776

92 93

95 96 97 98 99

100

12345678910111213141516171819202122232425

A /TIOCA /TP /PA

A /TIOCB /TP /PA

75747372717069686766656463626160595857565554535251

Top view (FP-100A)

210

CS /TMO /TP /PB

CS /TMIO /TP /PB

CS /TMO /TP /PB

TP /PB

RESO/FWE

4125136

CS /TMIO /TP /PB

TxD /P9

RxD /P9

D /P4

RxD /P9

404

515

IRQ /SCK /P9

D /P4

2627282930

6770819

D /P4

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

D /P3

A A A A

A /P1

D /P3

Note: * Functions as RESO in the on-chip mask ROM versions, and as FWE in the on-chip flash memory

versions.

/P2

/P2 /P2 /P2

3 11

210 19 0

7 6 5 4 3 2

1 0

7 6 5 4 3 2

Figure 1.3 Pin Arrangement of H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version,

H8/3062 Mask ROM Version, H8/3061 Mask ROM Version,

and H8/3060 Mask ROM Version

(FP-100A Package, Top View)

Page 59

P7 /AN

P7 /AN /DA

/P8 IRQ

/P8 /IRQCS

CS2/IRQ2/P8

ADTRG/CS1/IRQ3/P8

CS0/P8

TCLKA/TP0/PA

TCLKB/TP1/PA TCLKC/TIOCA0/TP2/PA TCLKD/TIOCB0/TP3/PA

A23/TIOCA1/TP4/PA A22/TIOCB1/TP5/PA A21/TIOCA2/TP6/PA A20/TIOCB2/TP7/PA

REF

210

654

MDMDMD

P6 /LWR

P6 /HWR

P6 /RD

P6 /ASVXTAL

75747372717069686766656463626160595857565554535251

EXTALVNMI

RES

STBY

/φ

210

P6 /BACK

P6 /BREQ

P6 /WAITVP5 /A

77 78

87 88

100

12345678910111213141516171819202122232425

/PB

/TP

/TMO

/ TMIO

/TMO

/PB

/TP

/ TMIO

/PB

Top view

(FP-100B, TFP-100B)

012345012

/PB

FWE

010101012

TxD /P9

RxD /P9

IRQ /SCK /P9

D /P4

IRQ /SCK /P9

1918171615 32107

P5 /A

3 3

D /P4

P5 /A

P2 /A

456 456

D /P4

14 6

P2 /A

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

D /P4

0.1 µF

P25/A P24/A P23/A P22/A P21/A P2

0/A8

P17/A P16/A P15/A P14/A P13/A P12/A P11/A P1

0/A0

D15/P37 D

/P36

D13/P35 D12/P3 D11/P33 D10/P32 D9/P31 D8/P3 D7/P47

13 12 11 10 9

7 6 5 4 3 2 1

Note: * An external capacitor must be connected to the VCL pin.

Figure 1.4 Pin Arrangement of H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT

B-Mask Version, H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask

Version, H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version

(FP-100B or TFP-100B Package, Top View)

Page 60

/AN

REF

/LWR

AVCCMD2MD1MD0P6

/HWR

/RD

/AS

XTAL

EXTAL

VSSNMI

RES

/φ

STBY

/BACK

/BREQ

/WAIT

/A P5

/A P2

P71/AN P72/AN P73/AN P74/AN

P75/AN P76/AN6/DA P77/AN7/DA

P80/IRQ P81/IRQ1/CS P82/IRQ2/CS

P83/IRQ3/CS1/ADTRG

/TP2/TIOCA0/TCLKC

/TP3/TIOCB0/TCLKD

PA PA5/TP5/TIOCB1/A

PA0/TP0/TCLKA PA

/TP1/TCLKB

/TP4/TIOCA1/A

8079787776

92 93

/CS

95 96 97 98 99

100

75747372717069686766656463626160595857565554535251

Top view (FP-100A)

12345678910111213141516171819202122232425

A /TIOCA /TP /PA

A /TIOCB /TP /PA

CL*

210

CS /TMO /TP /PB

CS /TMIO /TP /PB

CS /TMO /TP /PB

CS /TMIO /TP /PB

4125136

TP /PB

FWE

TP /PB

TxD /P9

Note: * An external capacitor must be connected to the VCL pin.

RxD /P9

404

515

IRQ /SCK /P9

D /P4

2627282930

6770819

D /P4

D /P3

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31

D /P3

0.1 µF

P23/A P22/A P21/A P20/A

P17/A P16/A6 P1

5/A5

P14/A P13/A P12/A P11/A P10/A

D /P3

11 10 9 8

4 3 2 1 0

7 6 5 4 3

Figure 1.5 Pin Arrangement of H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT

B-Mask Version, H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask

Version, H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version

(FP-100A Package, Top View)

Page 61

1.3.2 Pin Functions

Table 1.3 summarizes the pin functions. The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version have a VCL pin, and require the connection of an external capacitor.

Table 1.3 Pin Functions

Pin No.

FP-100B

Type Symbol

Power V

Internal step-down

Clock XTAL 67 69 Input For connection to a crystal resonator.

EXTAL 66 68 Input For connection to a crystal resonator or input

φ 61 63 Output System clock: Supplies the system clock to

TFP-100B FP-100A I/O Name and Function

, 35,683

, 37,70Input Power: For connection to the power supply.

Connect all V

pins to the system power

supply.

11, 22, 44, 57, 65, 92

13, 24, 46, 59, 67, 94

Input Ground: For connection to ground (0 V).

Connect all V

pins to the 0-V system power

supply.

Output Connect an external capacitor between this

pin and GND (0 V).

0.1 µF

For examples of crystal resonator and external clock input, see section 20, Clock Pulse Generator.

of an external clock signal. For examples of crystal resonator and external clock input, see section 20, Clock Pulse Generator.

external devices.

Do not connect to V

Page 62

Type Symbol

Operating mode

MD2 to MD

control

Pin No.

FP-100B TFP-100B FP-100A I/O Name and Function

75 to 73 77 to 75 Input Mode 2 to mode 0: For setting the operating

mode, as follows. Inputs at these pins must not be changed during operation.

MD2MD1MD0Operating Mode 0 0 0 Setting prohibited 0 0 1 Mode 1 0 1 0 Mode 2 0 1 1 Mode 3 1 0 0 Mode 4 1 0 1 Mode 5 1 1 0 Mode 6 1 1 1 Mode 7

System control

RES 63 65 Input Reset input: When driven low, this pin resets

the chip. This pin must be driven low at powerup.

RESO 10 12 Output Reset output (On-chip mask ROM

versions): Outputs the reset signal generated

by the watchdog timer to external devices.

FWE 10 12 Input Write enable signal (On-chip flash memory

versions): Flash memory programming control signal

STBY 62 64 Input Standby: When driven low, this pin forces

a transition to hardware standby mode.

BREQ 59 61 Input Bus request: Used by an external bus master

to request the bus right.

BACK 60 62 Output Bus request acknowledge: Indicates that the

bus has been granted to an external bus master.

Interrupts NMI 64 66 Input Nonmaskable interrupt: Requests a

nonmaskable interrupt.

IRQ

Address bus

17, 16,

IRQ

90 to 87

A23 to A097 to 100,

56 to 45, 43 to 36

19, 18, 92 to 89

99, 100, 1, 2, 58 to 47,

Input Interrupt request 5 to 0: Maskable interrupt

request pins

Output Address bus: Output address signals.

45 to 38

Page 63

Pin No.

FP-100B

Type Symbol

TFP-100B FP-100A I/O Name and Function

Data bus D15 to D034 to 23,

21 to 18

Bus control

CS CS

7 0

2 to 5, 88 to 91

AS 69 71 Output Address strobe: Goes low to indicate valid

RD 70 72 Output Read: Goes low to indicate reading from the

HWR 71 73 Output High write: Goes low to indicate writing to the

LWR 72 74 Output Low write: Goes low to indicate writing to the

WAIT 58 60 Input Wait: Requests insertion of wait states in bus

16-bit timer

8-bit timer TMO0,

TCLKD to TCLKA

TIOCA2 to TIOCA

TIOCB2 to TIOCB

TMO

TMIO1, TMIO

TCLKD to

96 to 93 98 to95 Input Clock input D to A: External clock inputs

99, 97, 95 1, 99, 97 Input/

100, 98,962, 100,98Input/

2, 4 4, 6 Output Compare match output: Compare match

3, 5 5, 7 Input/

96 to 93 98 to 95 Input Counter external clock input: These pins

TCLKA

Programmable

TP TP

15 0

9 to 2,

100 to 93 timing pattern controller (TPC)

36 to 25, 23 to 20

4 to 7, 90 to 93

11 to 4, 2, 1, 100 to 95

Input/

Data bus: Bidirectional data bus

output Output Chip select: Select signals for areas 7 to 0.

address output on the address bus.

external address space.

external address space; indicates valid data on the upper data bus (D

to D8).

external address space; indicates valid data on the lower data bus (D

to D0).

cycles during access to the external address space.

Input capture/output compare A2 to A0:

output

GRA2 to GRA0 output compare or input capture, or PWM output

Input capture/output compare B2 to B0:

output

GRB2 to GRB0 output compare or input capture

output pins

Input capture input/compare match output:

output

Input capture input or compare match output pins

input an external clock to the counters.

Output TPC output 15 to 0: Pulse output

Page 64

Pin No.

FP-100B

Type Symbol

Serial communication interface (SCI)

TxD1, TxD

RxD RxD

SCK1, SCK

A/D converter

AN7 to AN

TFP-100B FP-100A I/O Name and Function

13, 12 15, 14 Output Transmit data (channels 0, 1): SCI data

15, 14 17, 16 Input Receive data (channels 0, 1): SCI data input

1 0

17, 16 19, 18 Input/

output

85 to 78 87 to 80 Input Analog 7 to 0: Analog input pins

ADTRG 90 92 Input A/D conversion external trigger input:

D/A

DA1, DA085, 84 87, 86 Output Analog output: Analog output from the

converter Analog

76 78 Input Power supply pin for the A/D and D/A power supply

REF

86 88 Input Ground pin for the A/D and D/A converters.

77 79 Input Reference voltage input pin for the A/D and

I/O ports P17 to P1043 to 36 45 to 38 Input/

output

P27 to P2052 to 45 54 to 47 Input/

output

P37 to P3034 to 27 36 to 29 Input/

output

P47 to P4026 to 23,

21 to 18

28 to 25, 23 to 20

Input/ output

P53 to P5056 to 53 58 to 55 Input/

output

Serial clock (channels 0, 1): SCI clock input/output

External trigger input for starting A/D conversion

D/A converter

converters. Connect to the system power supply when not using the A/D and D/A converters.

Connect to system ground (0 V).

D/A converters. Connect to the system power supply when not using the A/D and D/A converters.

Port 1: Eight input/output pins. The direction of each pin can be selected in the port 1 data direction register (P1DDR).

Port 2: Eight input/output pins. The direction of each pin can be selected in the port 2 data direction register (P2DDR).

Port 3: Eight input/output pins. The direction of each pin can be selected in the port 3 data direction register (P3DDR).

Port 4: Eight input/output pins. The direction of each pin can be selected in the port 4 data direction register (P4DDR).

Port 5: Four input/output pins. The direction of each pin can be selected in the port 5 data direction register (P5DDR).

Page 65

Pin No.

FP-100B

Type Symbol

I/O ports P67 to P6061,

TFP-100B FP-100A I/O Name and Function

72 to 69, 60 to 58

63, 74 to 71, 62 to 60

Input/ output

Port 6: Eight input/output pins. The direction of each pin can be selected in the port 6 data

direction register (P6DDR). P77 to P7085 to 78 87 to 80 Input Port 7: Eight input pins P84 to P8091 to 87 93 to 89 Input/

output

Port 8: Five input/output pins. The direction of

each pin can be selected in the port 8 data

direction register (P8DDR). P95 to P9017 to 12 19 to 14 Input/

output

Port 9: Six input/output pins. The direction of

each pin can be selected in the port 9 data

direction register (P9DDR). PA7 to

PB7 to PB

100 to 93 2, 1,

100 to

Input/ output

9 to 2 11 to 4 Input/

output

Port A: Eight input/output pins. The direction

of each pin can be selected in the port A data

direction register (PADDR).

Port B: Eight input/output pins. The direction

of each pin can be selected in the port B data

direction register (PBDDR).

Notes: *1 In the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version,

H8/3061 mask ROM version, and H8/3060 mask ROM version

*2 In the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064

mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version.

Page 66

1.3.3 Pin Assignments in Each Mode

Table 1.4 lists the pin assignments in each mode.

Table 1.4 Pin Assignments in Each Mode (FP-100B or TFP-100B, FP-100A)

Pin No. Pin Name

FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

13v 24PB

35PB

46PB

57PB

68PB 79PB 810PB 911PB 10 12 RESO/

11 13 V

)

v PB0/TP8/

TMO0/CS

PB1/TP9/ TMIO1/CS

PB2/TP10/ TMO2/CS

PB3/TP11/ TMIO3/CS

RESO/ FWE

CC (vCL

/TP8/

TMO0/CS

/TP9/

TMIO1/CS

/TP10/

TMO2/CS

/TP11/

TMIO3/CS

/TP12PB4/TP12PB4/TP12PB4/TP12PB4/TP12PB4/TP12PB4/TP

/TP13PB5/TP13PB5/TP13PB5/TP13PB5/TP13PB5/TP13PB5/TP

/TP14PB6/TP14PB6/TP14PB6/TP14PB6/TP14PB6/TP14PB6/TP

/TP15PB7/TP15PB7/TP15PB7/TP15PB7/TP15PB7/TP15PB7/TP

FWE

12 14 P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD 13 15 P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD1P91/TxD 14 16 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD 15 17 P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD1P93/RxD 16 18 P94 /SCK0/

IRQ

17 19 P95 /SCK1/

IRQ

18 20 P40/D 19 21 P41/D 20 22 P42/D 21 23 P43/D 22 24 V

23 25 P44/D 24 26 P45/D

P94 /SCK0/

IRQ

P95 /SCK1/

IRQ

P40/D P41/D P42/D P43/D V P44/D P45/D

CC (vCL

)

CC (vCL

PB0/TP8/ TMO0/CS

PB1/TP9/ TMIO1/CS

PB2/TP10/ TMO2/CS

PB3/TP11/ TMIO3/CS

RESO/

FWE V

P94 /SCK0/

IRQ

P95 /SCK1/

IRQ

P40/D

P41/D

P42/D

P43/D

P44/D

P45/D

CC (vCL

PB0/TP8/ TMO0/CS

PB1/TP9/ TMIO1/CS

PB2/TP10/ TMO2/CS

PB3/TP11/ TMIO3/CS

RESO/ FWE

P94 /SCK0/

IRQ

P95 /SCK1/

IRQ

P40/D P41/D P42/D P43/D V

P44/D P45/D

)

v PB0/TP8/

TMO0/CS

PB1/TP9/ TMIO1/CS

PB2/TP10/ TMO2/CS

PB3/TP11/ TMIO3/CS

RESO/

FWE V

P94 /SCK0/

IRQ

P95 /SCK1/

IRQ

P40/D

P41/D

P42/D

P43/D

P44/D

P45/D

CC (vCL

)

CC (vCL

PB0/TP8/ TMO

PB1/TP9/ TMIO

PB2/TP10/ TMO

PB3/TP11/ TMIO

RESO/ FWE

P94 /SCK0/

IRQ

P95 /SCK1/

IRQ

P4 P4 P4 P4 V

P4 P4

)

CC (vCL

PB0/TP8/ TMO

PB1/TP9/ TMIO

PB2/TP10/ TMO

PB3/TP11/ TMIO

RESO/ FWE

P94 /SCK0/

IRQ

P95 /SCK1/

IRQ

P4 P4 P4 P4 V

P4 P4

)

Page 67

Pin No. Pin Name

FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

25 27 P46/D 26 28 P47/D 27 29 D 28 30 D 29 31 D 30 32 D 31 33 D 32 34 D 33 35 D 34 36 D 35 37 V 36 38 A 37 39 A 38 40 A 39 41 A 40 42 A 41 43 A 42 44 A 43 45 A 44 46 V 45 47 A 46 48 A 47 49 A 48 50 A 49 51 A 50 52 A 51 53 A 52 54 A 53 55 A 54 56 A 55 57 A 56 58 A 57 59 V

58 60 P60/WAIT P60/WAIT P60/WAIT P60/WAIT P60/WAIT P6

P46/D P47/D D

P10/A P11/A P12/A P13/A P14/A P15/A P16/A P17/A V

P20/A P21/A P22/A P23/A P24/A P25/A P26/A P27/A P50/A P51/A P52/A P53/A V

P4 P4 P3 P3 P3 P3 P3 P3 P3 P3 V P1 P1 P1 P1 P1 P1 P1 P1 V P2 P2 P2 P2 P2 P2 P2 P2 P5 P5 P5 P5 V P6

Page 68

Pin No. Pin Name

FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

59 61 P61/BREQ P61/BREQ P61/BREQ P61/BREQ P61/BREQ P6 60 62 P62/BACK P62/BACK P62/BACK P62/BACK P62/BACK P6

P6 P6

61 63 φφφφP67/φ P67/φ P67/φ 62 64 STBY STBY STBY STBY STBY STBY STBY 63 65 RES RES RES RES RES RES RES 64 66 NMI NMI NMI NMI NMI NMI NMI 65 67 V

66 68 EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL EXTAL 67 69 XTAL XTAL XTAL XTAL XTAL XTAL XTAL 68 70 V

69 71 AS AS AS AS AS P6 70 72 RD RD RD RD RD P6 71 73 HWR HWR HWR HWR HWR P6 72 74 LWR LWR LWR LWR LWR P6 73 75 MD 74 76 MD 75 77 MD 76 78 AV 77 79 V

REF

78 80 P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0P70/AN0P70/AN 79 81 P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1P71/AN1P71/AN 80 82 P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2P72/AN2P72/AN 81 83 P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3P73/AN3P73/AN 82 84 P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4P74/AN4P74/AN 83 85 P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5P75/AN5P75/AN

MD MD MD AV V

REF

MD MD MD AV V

REF

MD MD MD AV V

REF

MD MD MD AV V

REF

MD MD MD AV V

REF

P6 P6 P6 P6 MD MD MD AV V

REF

84 86 P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA0P76/AN6/DA 85 87 P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA1P77/AN7/DA 86 88 AV

87 89 P80/IRQ0P80/IRQ0P80/IRQ0P80/IRQ0P80/IRQ0P80/IRQ0P80/IRQ 88 90 P81/IRQ1/

89 91 P82/IRQ2/

P81/IRQ1/

P82/IRQ2/

P81/IRQ1/

P82/IRQ2/

P81/IRQ1/

P82/IRQ2/

P81/IRQ1/

P82/IRQ2/

P81/IRQ1P81/IRQ

P82/IRQ2P82/IRQ

Page 69

Pin No. Pin Name

FP-100B TFP-100B FP-100A Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7

90 92 P83/IRQ3/

CS1/ ADTRG

91 93 P84/CS0P84/CS0P84/CS0P84/CS0P84/CS0P8 92 94 V

93 95 PA0/TP0/

TCLKA

94 96 PA1/TP1/

TCLKB

95 97 PA2/TP2/

TIOCA0/ TCLKC

96 98 PA3/TP3/

TIOCB0/ TCLKD

97 99 PA4/TP4/

TIOCA

98 100 PA5/TP5/

TIOCB

99 1 PA6/TP6/

TIOCA

100 2 PA7/TP7/

TIOCB

P83/IRQ3/

CS1/ ADTRG

PA0/TP0/ TCLKA

PA1/TP1/ TCLKB

PA2/TP2/ TIOCA0/ TCLKC

PA3/TP3/ TIOCB0/ TCLKD

PA4/TP4/ TIOCA

PA5/TP5/ TIOCB

PA6/TP6/ TIOCA

PA7/TP7/ TIOCB

P83/IRQ3/

CS1/ ADTRG

PA0/TP0/ TCLKA

PA1/TP

/TCLKB PA2/TP2/

TIOCA0/ TCLKC

PA3/TP3/ TIOCB0/ TCLKD

PA4/TP4/ TIOCA1/A

PA5/TP5/ TIOCB1/A

PA6/TP6/ TIOCA2/A

P83/IRQ3/

CS1/ ADTRG

PA0/TP0/ TCLKA

PA1/TP1/ TCLKB

PA2/TP2/ TIOCA0/ TCLKC

PA3/TP3/ TIOCB0/ TCLKD

PA4/TP4/ TIOCA1/A

PA5/TP5/ TIOCB1/A

PA6/TP6/ TIOCA2/A

P83/IRQ3/

CS1/ ADTRG

PA0/TP0/ TCLKA

PA1/TP1/ TCLKB

PA2/TP2/ TIOCA0/ TCLKC

PA3/TP3/ TIOCB0/ TCLKD

PA4/TP4/ TIOCA1/A

PA5/TP5/ TIOCB1/A

PA6/TP6/ TIOCA2/A

PA7/TP7/ TIOCB2/A

P83/IRQ3/

ADTRG

PA0/TP0/ TCLKA

PA1/TP1/ TCLKB

PA2/TP2/ TIOCA0/ TCLKC

PA3/TP3/ TIOCB0/ TCLKD

PA4/TP4/ TIOCA

PA5/TP5/ TIOCB

PA6/TP6/ TIOCA

PA7/TP7/ TIOCB

P83/IRQ3/

ADTRG

P8 V

PA0/TP0/ TCLKA

PA1/TP1/ TCLKB

PA2/TP2/ TIOCA0/ TCLKC

PA3/TP3/ TIOCB0/ TCLKD

PA4/TP4/ TIOCA

PA5/TP5/ TIOCB

PA6/TP6/ TIOCA

PA7/TP7/ TIOCB

Notes: *1 In modes 1, 3, and 5 the P40 to P47 functions of pins P40/D0 to P47/D7 are selected after

a reset, but they can be changed by software.

*2 In modes 2 and 4 the D

to D7 functions of pins P40/D0 to P47/D7 are selected after a

reset, but they can be changed by software.

*3 Functions as RESO in the on-chip mask ROM versions, and as FWE in the on-chip

flash memory versions. Functions as the programming control signal in modes 5 and 7.

*4 Functions as V

in the H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062

mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. In the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version, this pin functions as V

Page 70

1.4 Notes on H8/3062F-ZTAT R-Mask Version

There are two models with on-chip flash memory in the H8/3062 Series: the H8/3062F-ZTAT and the H8/3062F-ZTAT R-mask version. Points to be noted when using the H8/3062F-ZTAT R-mask version are given below.

1.4.1 Pin Arrangement

The H8/3062F-ZTAT R-mask version has the same pin arrangement as the H8/3062F-ZTAT and the H8/3062 mask ROM version, H8/3061 mask ROM version, and H8/3060 mask ROM version. Except for the VCL pin, it also has the same pin arrangement as the H8/3062F-ZTAT B-mask version, H8/3064F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version.

Page 71

1.4.2 Product Type Names and Markings

Table 1.5 shows the product type names and differences in sample markings for the H8/3062FZTAT and the H8/3062F-ZTAT R-mask version.

Table 1.5 Differences in H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version

Markings

H8/3062F-ZTAT H8/3062F-ZTAT R-Mask Version

TFP-100 Product type name HD64F3062TE HD64F3062RTE

Sample markings

FP-100B Product type name HD64F3062F HD64F3062RF

Sample markings

H8/3062

HD 64F3062TE20

JAPAN

H8/3062

HD 64F3062F20

JAPAN

H8/3062 R

HD 64F3062TE20

JAPAN

“R” is printed above the type name.

H8/3062 R

HD 64F3062F20

JAPAN

“R” is printed above the type name.

FP-100A Product type name HD64F3062FP HD64F3062RFP

Sample markings

H8/3062

HD 64F3062FP20

JAPAN

H8/3062 R

HD 64F3062FP20

JAPAN

“R” is printed above the type name.

1.4.3 Differences between H8/3062F-ZTAT and H8/3062F-ZTAT R-Mask Version

Table 1.6 shows the differences between the H8/3062F-ZTAT, the H8/3062F-ZTAT R-mask version, and the on-chip mask ROM versions.

Page 72

Table 1.6 Differences between H8/3062F-ZTAT, H8/3062F-ZTAT R-Mask Version, and

On-Chip Mask ROM Versions

On-Chip Flash Memory Versions On-Chip Mask ROM Versions

Item HD64F3062 HD64F3062R HD6433062 HD6433061 HD6433060

ROM 128 kbytes flash memory 128 kbytes

mask ROM

Address output functions

ADRCR register (H'FEE01E)

Compatible with previous H8/300H Series

—

Corresponding address consists of reserved bits

Choice of address update mode 1 (compatible with previous H8/300H Series) or address update mode 2

See the section on the bus controller for details.

—

See the section on the bus controller for the bit function.

96 kbytes mask ROM

—

64 kbytes mask ROM

—

ADRCTL

The address output functions and ADRCR register specification of the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version are the same as for the H8/3062F-ZTAT R-mask version.

1.5 Notes on H8/3064F-ZTAT B-Mask Version, H8/3062F-ZTAT B-Mask Version, H8/3064 Mask ROM B-Mask Version, H8/3062 Mask ROM B-Mask Version, H8/3061 Mask ROM B-Mask Version, and H8/3060 Mask ROM B-Mask Version

The H8/3062 Series includes one model with 128-kbyte on-chip flash memory, the H8/3062FZTAT B-mask version developed on the basis of the H8/3062F-ZTAT R-mask version, and one model with 256-kbyte large-capacity on-chip flash memory, the H8/3064F-ZTAT B-mask version.

The H8/3062F-ZTAT B-mask version and H8/3064F-ZTAT B-mask version have the following features:

1. Low power consumption

2. Functional compatibility with the H8/3062F-ZTAT R-mask version

3. Pin arrangement compatibility (except for the VCL pin)

Points to be noted when using the H8/3062F-ZTAT B-mask version or H8/3064F-ZTAT B-mask version are given below.

Page 73

1.5.1 Pin Arrangement

Except for the VCL pin, the H8/3062F-ZTAT and the H8/3062F-ZTAT R-mask version have the same pin arrangement as the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version.

1.5.2 Product Type Names and Markings

Table 1.7 shows the product type names and differences in sample markings for the H8/3062FZTAT R-mask version, H8/3062F-ZTAT B-mask version, and H8/3064F-ZTAT B-mask version.

Table 1.7 Differences in H8/3062F-ZTAT R-Mask Version, H8/3062F-ZTAT B-Mask

Version, and H8/3064F-ZTAT B-Mask Version Markings

TFP-100 Product

type name Sample

markings

FP-100B Product

type name Sample

markings

FP-100A Product

type name Sample

markings

H8/3062F-ZTAT R-Mask Version

H8/3062F-ZTAT B-Mask Version

H8/3064F-ZTAT B-Mask Version

HD64F3062RTE HD64F3062BTE HD64F3064BTE

H8/3062 R

HD 64F3062TE20

JAPAN

H8/3062 B

HD 64F3062TE25

JAPAN

“B” is printed above the type name.

H8/3064 B

HD 64F3064TE25

JAPAN

“B” is printed above the type name.

HD64F3062RF HD64F3062BF HD64F3064BF

H8/3062 R

HD 64F3062F20

JAPAN

H8/3062 B

HD 64F3062F25

JAPAN

“B” is printed above the type name.

H8/3064 B

HD 64F3064F25

JAPAN

“B” is printed above the type name.

HD64F3062RFP HD64F3062BFP HD64F3064BFP

H8/3062 R

HD 64F3062FP20

JAPAN

H8/3062 B

HD 64F3062FP25

JAPAN

H8/3064 B

HD 64F3064FP25

JAPAN

“B” is printed above the type name.

Page 74

1.5.3 VCL Pin

The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, and on-chip mask ROM B-mask versions have a VCL (internal step-down) pin, to which a 0.1 µF internal voltage stabilization capacitor must be connected.

The method of connecting the external capacitor is shown in figure 1.6.

Do not connect the V

power supply to the V

pin (Connect the VCC power supply to other V

pins as usual). Note that the VCL output pin occupies the same location as a VCC pin in the H8/3062F-ZTAT R-mask version and on-chip mask ROM versions.

VCC power

supply External capacitor

0.1 µF

H8/3062F-ZTAT, H8/3062F-ZTAT B-mask version, H8/3064F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version,

H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version

H8/3061 mask ROM B-mask version, H8/3060 mask ROM B-mask version (5 V model)

Do not connect the VCC power supply to the V

pin (Connect the VCC power supply to

other V

pins as usual).

Place the capacitor close to the pin.

These versions have a V pin in the same pin position as a V the H8/3062F-ZTAT B-mask version and H8/3064F-ZTAT B-mask version.

Figure 1.6 H8/3062F-ZTAT B-Mask Version, H8/3064F-ZTAT B-Mask Version, and

On-Chip Mask ROM B-Mask Versions

power supply

pin in

Page 75

1.5.4 Notes on Changeover to On-Chip Mask ROM Versions and On-Chip Mask ROM B-Mask Versions

(1) Care is required when changing from the H8/3062F-ZTAT B-mask version with on-chip flash

memory to a model with on-chip mask ROM. An external capacitor must be connected to the VCL pin of the H8/3062F-ZTAT B-mask

version (5 V model). This VCL pin occupies the same location as a VCC pin in the on-chip mask ROM versions. Changeover to a mask ROM version must therefore be taken into account when undertaking pattern design, etc., in the board design stage.

(2) When changing from the H8/3062F-ZTAT B-mask version with on-chip flash memory to the

on-chip mask ROM B-mask version, note (1) above does not need to be considered because the VCL pin is assigned to the same location in both versions. It does not need to be considered either when changing from the H8/3064F-ZTAT B-mask version to the on-chip mask ROM B-mask version.

power

H8/3062 Series chip

supply

← Land pattern for on-chip mask ROM versions

(0 Ω resistance mounted)

← Land pattern for H8/3062F-ZTAT B-mask version

(0.1 µF capacitor mounted)

Figure 1.7 Example of Board Pattern Providing for External Capacitor

Page 76

1.6 Setting Oscillation Settling Wait Time

When software standby mode is used, after exiting software standby mode a wait period must be provided to allow the clock to stabilize. Select the length of time for which the CPU and peripheral functions are to wait by setting bits STS2 to STS0 in the system control register (SYSCR) and bits DIV1 and DIV0 in the division ratio control register (DIVCR) according to the operating frequency of the chip.

For the H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, and on-chip mask ROM B-mask versions ensure that the oscillation settling wait time is at least 0.1 ms when operating on an external clock.

For setting details, see section 21.4.3, Selection of Waiting Time for Exit from Software Standby Mode.

1.7 Caution on Crystal Resonator Connection

The H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, and on-chip mask ROM B-mask versions support an operating frequency of up to 25 MHz. If a crystal resonator with a frequency higher than 20 MHz is connected, attention must be paid to circuit constants such as external load capacitance values. For details see section 20.2.1, Connecting a Crystal Resonator.

Page 77

Section 2 CPU

2.1 Overview

The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.

2.1.1 Features

The H8/300H CPU has the following features.

• Upward compatibility with H8/300 CPU

Can execute H8/300 Series object programs.

• General-register architecture

Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers)

• 64 basic instructions

 8/16/32-bit arithmetic and logic instructions  Multiply and divide instructions  Powerful bit-manipulation instructions

• Eight addressing modes

 Register direct [Rn]  Register indirect [@ERn]  Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)]  Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]  Absolute address [@aa:8, @aa:16, or @aa:24]  Immediate [#xx:8, #xx:16, or #xx:32]  Program-counter relative [@(d:8, PC) or @(d:16, PC)]  Memory indirect [@@aa:8]

• 16-Mbyte linear address space

• High-speed operation

 All frequently-used instructions execute in two to four states  Maximum clock frequency:

20 MHz (H8/3062F-ZTAT, H8/3062F-ZTAT R-mask version, H8/3062 mask ROM version, H8/3061 mask ROM version, H8/3060 mask ROM version)

25 MHz (H8/3064F-ZTAT B-mask version, H8/3062F-ZTAT B-mask version, H8/3064 mask ROM B-mask version, H8/3062 mask ROM B-mask version, H8/3061 mask ROM B-mask version, and H8/3060 mask ROM B-mask version)

Page 78

 8/16/32-bit register-register add/subtract: 100 ns@20 MHz (80 ns@25 MHz)  8 × 8-bit register-register multiply: 700 ns@20 MHz (560 ns@25 MHz)  16 ÷ 8-bit register-register divide: 700 ns@20 MHz (560 ns@25 MHz)  16 × 16-bit register-register multiply: 1.1 µs@20 MHz (0.88 µs@25 MHz)  32 ÷ 16-bit register-register divide: 1.1 µs@20 MHz (0.88 µs@25 MHz)

• Two CPU operating modes  Normal mode  Advanced mode

• Low-power mode

Transition to power-down state by SLEEP instruction

2.1.2 Differences from H8/300 CPU

In comparison to the H8/300 CPU, the H8/300H has the following enhancements.

• More general registers Eight 16-bit registers have been added.

• Expanded address space  Advanced mode supports a maximum 16-Mbyte address space.  Normal mode supports the same 64-kbyte address space as the H8/300 CPU.

• Enhanced addressing

The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.

• Enhanced instructions  Data transfer, arithmetic, and logic instructions can operate on 32-bit data.  Signed multiply/divide instructions and other instructions have been added.

Page 79

2.2 CPU Operating Modes

The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes.

Normal mode

CPU operating modes

Advanced mode

Maximum 64 kbytes, program and data areas combined.

Maximum 16 Mbytes, program and data areas combined.

Figure 2.1 CPU Operating Modes

2.3 Address Space

Figure 2.2 shows a simple memory map for the H8/3062 Series. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further details see section 3.6, Memory Map in Each Operating Mode.

The 1-Mbyte operating modes use 20-bit addressing. The upper 4 bits of effective addresses are ignored.

H'0000

H'FFFF

H'00000

H'000000

H'FFFFF

a. 1-Mbyte mode b. 16-Mbyte mode

Figure 2.2 Memory Map

H'FFFFFF

Advanced modeNormal mode

Page 80

2.4 Register Configuration

2.4.1 Overview

The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers.

General Registers (ERn)

0707015 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7

Control Registers (CR)

E0 E1 E2 E3 E4 E5 E6 E7

23 0

(SP)

R0H R1H R2H R3H R4H R5H R6H R7H

R0L R1L R2L R3L R4L R5L R6L R7L

Legend:

Stack pointer

SP :

Program counter

PC :

Condition code register

CCR :

Interrupt mask bit

User bit or interrupt mask bit

UI :

Half-carry flag

User bit

Negative flag

Zero flag

Overflow flag

Carry flag

Figure 2.3 CPU Registers

6543210

IUIHUNZVC

CCR

Page 81

2.4.2 General Registers

The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7).

The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers.

The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers.

Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected independently.

• Address registers

• 32-bit registers • 16-bit registers • 8-bit registers E registers

(extended registers)

E0 to E7

ER registers

ER0 to ER7

R registers

R0 to R7

RH registers

R0H to R7H

RL registers

R0L to R7L

Figure 2.4 Usage of General Registers

General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack.

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Free area

SP (ER7)

Stack area

Figure 2.5 Stack

2.4.3 Control Registers

The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR).

Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0.

Condition Code Register (CCR): This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.

Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence.

Bit 6—User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see section 5, Interrupt Controller.

Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise.

Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions.

Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit.

Bit 2—Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.

Page 83

Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times.

Bit 0—Carry Flag (C): Set to 1 when a carry is generated by execution of an operation, and cleared to 0 otherwise. Used by:

• Add instructions, to indicate a carry

• Subtract instructions, to indicate a borrow

• Shift and rotate instructions

The carry flag is also used as a bit accumulator by bit manipulation instructions.

Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional branch (Bcc) instructions.

For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and UI bits, see section 5, Interrupt Controller.

2.4.4 Initial CPU Register Values

In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the initial value of the stack pointer (ER7) is also undefined. The stack pointer (ER7) must therefore be initialized by an MOV.L instruction executed immediately after a reset.

Page 84

2.5 Data Formats

The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

2.5.1 General Register Data Formats

Figures 2.6 and 2.7 show the data formats in general registers.

Data Type Data Format

1-bit data

4-bit BCD data

Byte data

Legend: RnH : General register RH

RnL : General register RL

General Register

RnH

RnL

RnH

RnL

RnH

RnL

70 7

6543210

Don’t care

Lower digitUpper digit

Don’t care

MSB LSB

Don’t care

70 76543210

Don’t care

MSB LSB

Lower digitUpper digit

Figure 2.6 General Register Data Formats

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General RegisterData Type Data Format

15 0

Word data

Longword data

Legend: ERn :

General register

En :

General register E

Rn :

General register R

MSB :

Most significant bit

LSB :

Least significant bit

ERn

15 0

MSB LSB

31 16

MSB

MSB LSB

15 0

LSB

Figure 2.7 General Register Data Formats

2.5.2 Memory Data Formats

Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.

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1-bit data

AddressData Type Data Format

70 76543210Address L

Byte data

Word data

Longword data

Address L

Address 2M Address 2M + 1

Address 2N Address 2N + 1

MSB LSB

MSB

LSB

MSB

Address 2N + 2 Address 2N + 3

LSB

Figure 2.8 Memory Data Formats

When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size.

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2.6 Instruction Set

2.6.1 Instruction Set Overview

The H8/300H CPU has 64 types of instructions, which are classified in table 2.1.

Table 2.1 Instruction Classification

Function Instruction Types

Data transfer MOV, PUSH

Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS,

MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU Logic operations AND, OR, XOR, NOT 4 Shift operations SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR 8 Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR,

BIXOR, BLD, BILD, BST, BIST

Branch Bcc

, JMP, BSR, JSR, RTS 5 System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP 9 Block data transfer EEPMOV 1

Notes: *1 POP.W Rn is identical to MOV.W @SP+, Rn.

PUSH.W Rn is identical to MOV.W Rn, @–SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @–SP.

Not available in the H8/3062 Series.

*3 Bcc is a generic branching instruction.

, POP

, MOVTPE

, MOVFPE

5 18

Total 64 types

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2.6.2 Instructions and Addressing Modes

Table 2.2 indicates the instructions available in the H8/300H CPU.

Table 2.2 Instructions and Addressing Modes

Addressing Modes

(d:24,

(d:16,

Function Instruction #xx Rn @ERn

Data MOV BWL BWL BWL BWL BWL BWL B BWL BWL ———— transfer

Arithmetic ADD, CMP BWL BWL — ——— ——————— operations

Logic operations

Shift instructions — BWL ———— ——————— Bit manipulation — BB—— — B —————— Branch Bcc, BSR ——— ——— ———————

System TRAPA —————— —————— control

Block data transfer —————— ——————BW

POP, PUSH —————— ——————WL MOVFPE, ——— ——— ———————

MOVTPE

SUB WL BWL ———— ——————— ADDX, SUBX B B ———— ——————— ADDS, SUBS — L ———— ——————— INC, DEC — BWL — ——— ——————— DAA, DAS — B ———— ——————— MULXU, — BW — ——— ———————

MULXS, DIVXU, DIVXS

NEG — BWL ———— ——————— EXTU, EXTS — WL ———— ——————— AND, OR, XOR — BWL — ——— ———————

NOT — BWL ———— ———————

JMP, JSR —— ——— ——— —— RTS —————— —— —— —

RTE —————— —————— SLEEP —————— —————— LDC B B W W W W — WW——— STC — BWWWW — WW———— ANDC, ORC,

XORC NOP —————— ——————

B ————— ———————

ERn)

@ERn+/

ERn)

@–ERn@aa:8@aa:16@aa:24

@ (d:8, PC)

(d:16, PC)@@aa:8 —

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2.6.3 Tables of Instructions Classified by Function

Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next.

Operation Notation

Rd General register (destination)* Rs General register (source)* Rn General register* ERn General register (32-bit register or address register)* (EAd) Destination operand (EAs) Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction

× Multiplication ÷ Division ∧ AND logical ∨ OR logical ⊕ Exclusive OR logical → Move

¬ NOT (logical complement) :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length

Note: *General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to

R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7).

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Table 2.3 Data Transfer Instructions

Instruction Size* Function

MOV B/W/L (EAs) → Rd, Rs → (EAd)

Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.

MOVFPE B (EAs) → Rd

Cannot be used in the H8/3062 Series.

MOVTPE B Rs → (EAs)

Cannot be used in the H8/3062 Series.

POP W/L @SP+ → Rn

Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn.

PUSH W/L Rn → @–SP

Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @–SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @–SP.

Note: *Size refers to the operand size.

B : Byte W: Word L : Longword

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Table 2.4 Arithmetic Operation Instructions

Instruction Size* Function

ADD,SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd

Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.)

ADDX, SUBX

INC, DEC

ADDS, SUBS

DAA, DAS

MULXU B/W Rd × Rs → Rd

MULXS B/W Rd × Rs → Rd

B Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd

Performs addition or subtraction with carry or borrow on data in two general registers, or on immediate data and data in a general register.

B/W/L Rd ± 1 → Rd, Rd ± 2 → Rd

Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.)

L Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd

Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.

B Rd decimal adjust → Rd

Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data.

Performs unsigned multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

Performs signed multiplication on data in two general registers: either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.

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Instruction Size* Function

DIVXU B/W Rd ÷ Rs → Rd

Performs unsigned division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder

DIVXS B/W Rd ÷ Rs → Rd

Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder, or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder

CMP B/W/L Rd – Rs, Rd – #IMM

Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result.

NEG B/W/L 0 – Rd → Rd

Takes the two’s complement (arithmetic complement) of data in a general register.

EXTS W/L Rd (sign extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit.

EXTU W/L Rd (zero extension) → Rd

Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros.

Note: *Size refers to the operand size.

B : Byte W: Word L : Longword

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Table 2.5 Logic Operation Instructions

Instruction Size* Function

AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd

Performs a logical AND operation on a general register and another general register or immediate data.

OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd

Performs a logical OR operation on a general register and another general register or immediate data.

XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd

Performs a logical exclusive OR operation on a general register and another general register or immediate data.

NOT B/W/L ¬ Rd → Rd

Takes the one’s complement (logical complement) of general register contents.

Note: *Size refers to the operand size.

B : Byte W: Word L : Longword

Table 2.6 Shift Instructions

Instruction Size* Function

SHAL, SHAR

SHLL, SHLR

ROTL, ROTR

ROTXL, ROTXR

Note: *Size refers to the operand size.

B/W/L Rd (shift) → Rd

Performs an arithmetic shift on general register contents.

B/W/L Rd (shift) → Rd

Performs a logical shift on general register contents.

B/W/L Rd (rotate) → Rd

Rotates general register contents.

B/W/L Rd (rotate) → Rd

Rotates general register contents, including the carry bit.

B : Byte W: Word L : Longword

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Table 2.7 Bit Manipulation Instructions

Instruction Size* Function

BSET B 1 → (<bit-No.> of <EAd>)

Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.

BCLR B 0 → (<bit-No.> of <EAd>)

Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.

BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)

Inverts a specified bit in a general register or memory operand. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.

BTST B ¬ (<bit-No.> of <EAd>) → Z

Tests a specified bit in a general register or memory operand and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower 3 bits of a general register.

BAND B C ∧ (<bit-No.> of <EAd>) → C

ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag.