HITACHI HD61830, HD61830B User Manual

HD61830

HD61830/HD61830B

LCDC (LCD Timing Controller)

ADE-207-275(Z) '99.9 Rev. 0.0

Description

The HD61830/HD61830B is a dot matrix liquid crystal graphic display controller LSI that stores the display data sent from an 8-bit microcontroller in the external RAM to generate dot matrix liquid crystal driving signals.

It has a graphic mode in which 1-bit data in the external RAM corresponds to the on/off state of 1 dot on liquid crystal display and a character mode in which characters are displayed by storing character codes in the external RAM and developing them into the dot patterns with the internal character generator ROM. Both modes can be provided for various applications.

The HD61830/HD61830B is produced by the CMOS process. Thus, combined with a CMOS microcontroller it can complete a liquid crystal display device with lower power dissipation.

Features

•Dot matrix liquid crystal graphic display controller

•Display control capacity

Graphic mode: 512k dots (216 bytes)

Character mode: 4096 characters (212 characters)

•Internal character generator ROM: 7360 bits

160 types of 5 7 dot characters

32 types of 5 11 dot characters Total 192 characters

Can be extended to 256 characters (4 kbytes max.) with external ROM

1

HD61830/HD61830B

•Interfaces to 8-bit MPU

•Display duty cycle (can be selected by a program) Static to 1/128 duty cycle

•Various instruction functions

Scroll, cursor on/off/blink, character blink, bit manipulation

•Display method: Selectable A or B types

•Internal oscillator (with external resistor and capacitor) HD61830

•Operating frequency

1.1 MHz HD61830

2.4 MHz HD61830B

•Low power dissipation

•Power supply: Single +5 V ±10%

•CMOS process

2

HD61830/HD61830B

Differences between Products

HD61830 and HD61830B

	HD61830	HD61830B
Oscillator	Internal or external	External only
Operating frequency	1.1 MHz	2.4 MHz
Pin arrangement	Pin 6: C	Pin 6: CE
and signal name	Pin 7: R	Pin 7: OE
	Pin 9: CPO	Pin 9: NC
Package marking	A	B
to see figure

Package Marking
	3D13	Lot No.
A	HD61830A00
	JAPAN

	3D13	Lot No.
B	HD61830B00
	JAPAN

Ordering Information

Type No.

Package

HD61830A00H

60-pin plastic QFP (FP-60)

HD61830B00H

3

HD61830/HD61830B

Pin Arrangement

												MB		MA0		MA1		MA2		MA3			MA4		MA5		MA6		MA7		MA8		MA9
											5		4		3		2		1		60			59		58		57		56		55		54
									6																									53
	(CE)			C
																																		52
	(OE)			R					7
				CR																														51
									8
(NC) CPO																																		50
									9
	FLM																																	49
									10
		CL1																																48
									11
																																		47
SYNC									12
																																		46
			WE						13												FP-60
																																		45
		RES							14											(Top view)
																																		44
				CS					15
					E																													43
									16
		R/W																																42
									17
				RS																														41
									18
			MA																															40
									19
	GND																																	39
									20
		DB7																																38
									21
		DB6																																37
									22
		DB5								24	25		26		27		28		29		30			31		32		33		34		35		36
									23
										DB4		DB3		DB2		DB1		DB0		V			MD7		MD6		MD5		MD4		MD3		MD2
																				CC

( ) is for HD61830B

MA10

MA11

MA12

MA13

MA14

MA15

D2

D1

CL2

RD0

RD1

RD2

RD3

RD4

RD5

RD6

RD7

MD0

MD1

4

HD61830/HD61830B

Terminal Functions

Symbol

Pin Number

I/O

Function

DB0–DB7

28–21

I/O

Data bus: Three-state I/O common terminal

Data is transferred to MPU through DB0 to DB7.

CS

15

I

Chip select: Selected state with CS = 0

R/W

17

I

Read/Write:R/W = 1: MPU ← HD61830

R/W = 0: MPU → HD61830

RS

18

I

Register select:RS = 1: Instruction register

RS = 0: Data register

E

16

I

Enable: Data is written at the fall of E

Data can be read while E is 1

CR

8

I

CR oscillator (HD61830), External clock input (HD61830B)

C

6

—

CR oscillator to capacitor (HD61830 only)

R

7

—

CR oscillator to resistor (HD61830 only)

CPO

9

O

Clock signal for HD61830 in slave mode (HD61830 only)

CE

6

O

Chip enable (HD61830B only)

CE = 0: Chip enables make external RAM in active

OE

7

O

Output enable (HD61830B only)

OE = 1: Output enable informs external RAM that HD61830B requires

data bus

NC

9

Open

Unused terminal. Don’t connect any wires to this terminal

(HD61830B only)

MA0–MA15

4–1, 60–49

O

External RAM address output

In character mode, the line code for external CG is output through

MA12 to MA15 (0: Character 1st line, F: Character 16th line)

MD0–MD7

37–30

I/O

Display data bus: Three-state I/O common terminal

RD0–RD7

45–38

I

ROM data input: Dot data from external character generator is input

WE

13

O

Write enable: Write signal for external RAM

CL2

46

O

Display data shift clock for LCD drivers

CL1

11

O

Display data latch signal for LCD drivers

FLM

10

O

Frame signal for display synchronization

MA

19

O

Signal for converting liquid crystal driving signal into AC, A type

MB

5

O

Signal for converting liquid crystal driving signal into AC, B type

D1

47

O

Display data serial output

D1: For upper half of screen

D2

48

D2: For lower half of screen

SYNC

12

I/O

Synchronous signal for parallel operation

Three-state I/O common terminal (with pull-up MOS)

Master: Synchronous signal is output

Slave: Synchronous signal is input

RES

14

I

Reset: Reset = 0 results in display off, slave mode and Hp = 6

5

6

			SYNC CL1 MA MB FLM				(CE)
							(OE)	WE
					Refesh address	16
					counter (1)
			Dot counter		(RAC1)	16	Multiplexer
E	circuit			8	Refesh address
		Data	(DC)					RAM
					counter (2)
	8	input			(RAC2)			*
DB0–DB7		register			Cursor address 16
CS		(DIR)	Dot registers		counter
			(DR)		(CAC)			MD0–MD7
	interface
RES		Data			counter			ROM
RS			8					Extended
R/W					Line address	4		external
	I/O	output	6	8			Character
							generator
		register					ROM
		(DOR)			Cursor		(CGROM)
			Mode		signal
					generator			RD0–RD7
			control
	4		register	Control			Multiplexer
		Instruction	(MCR)	signal
		register	Control
	Busy	(IR)	signal
	flag						Parallel/serial	D1
	(BF)						converter
		Oscillator		Oscillator
		circuit
				circuit			Parallel/serial
								D2
							converter
		Cf

		(CL2)	(CR)	* When extended external ROM is used, MA0–MA11
CL2	Rf	CPO
				are applied to RAM, MA12 –MA15 are applied to
				extended external ROM.
				( ) is for HD61830B

Diagram Block	HD61830/HD61830B

HD61830/HD61830B

Block Functions

Registers

The HD61830/HD61830B has the five types of registers: instruction register (IR), data input register (DIR), data output register (DOR), dot registers (DR), and mode control register (MCR).

The IR is a 4-bit register that stores the instruction codes for specifying MCR, DR, a start address register, a cursor address register, and so on. The lower order 4 bits DB0 to DB3 of data buses are written in it.

The DIR is an 8-bit register used to temporarily store the data written into the external RAM, DR, MCR, and so on.

The DOR is an 8-bit register used to temporarily store the data read from the external RAM. Cursor address information is written into the cursor address counter (CAC) through the DIR. When the memory read instruction is set in the IR (latched at the falling edge of E signal), the data of external RAM is read to DOR by an internal operation. The data is transferred to the MPU by reading the DOR with the next instruction (the contents of DOR are output to the data bus when E is at the high level).

The DR are registers used to store dot information such as character pitches and the number of vertical dots, and so on. The information sent from the MPU is written into the DR via the DIR.

The MCR is a 6-bit register used to store the data which specifies states of display such as display on/off and cursor on/off/blink. The information sent from the MPU is written in it via the DIR.

Busy Flag (BF)

The busy flag = 1 indicates the HD61830 is performing an internal operation. Instructions cannot be accepted. As shown in Control Instruction, read busy flag, the busy flag is output on DB7 under the conditions of RS = 1, R/W = 1, and E = 1. Make sure the busy flag is 0 before writing the next instruction.

Dot Counters (DC)

The dot counters are counters that generate liquid crystal display timing according to the contents of DR.

7

HD61830/HD61830B

Refresh Address Counters (RAC1/RAC2)

The refresh address counters, RAC1 and RAC2, control the addresses of external RAM, character generator ROM (CGROM), and extended external ROM. The RAC1 is used for the upper half of the screen and the RAC2 for the lower half. In the graphic mode, 16-bit data is output and used as the address signal of external RAM. In the character mode, the high order 4 bits (MA12–MA15) are ignored. The 4 bits of line address counter are output instead and used as the address of extended ROM.

Character Generator ROM

The character generator ROM has 7360 bits in total and stores 192 types of character data. A character code (8 bits) from the external RAM and a line code (4 bits) from the line address counter are applied to its address signals, and it outputs 5-bit dot data.

The character font is 5 × 7 (160 characters) or 5 × 11 (32 characters). The use of extended ROM allows 8 × 16 (256 characters max.) to be used.

Cursor Address Counter

The cursor address counter is a 16-bit counter that can be preset by instruction. It holds an address when the data of external RAM is read or written (when display dot data or a character code is read or written). The value of the cursor address counter is automatically increased by 1 after the display data is read or written and after the set/clear bit instruction is executed.

Cursor Signal Generator

The cursor can be displayed by instruction in character mode. The cursor is automatically generated on the display specified by the cursor address and cursor position.

Parallel/Serial Conversion

The parallel data sent from the external RAM, character generator ROM, or extended ROM is converted into serial data by two parallel/serial conversion circuits and transferred to the liquid crystal driver circuits for upper screen and lower screen simultaneously.

8

HD61830/HD61830B

Display Control Instructions

Display is controlled by writing data into the instruction register and 13 data registers. The RS signal distinguishes the instruction register from the data registers. 8-bit data is written into the instruction register with RS = 1, and the data register code is specified. After that, the 8-bit data is written in the data register and the specified instruction is executed with RS = 0.

During the execution of the instruction, no new instruction can be accepted. Since the busy flag is set during this, read the busy flag and make sure it is 0 before writing the next instruction.

1. Mode Control: (Execution time: 4 s) Code H'00 (hexadecimal) written into the instruction register specifies the mode control register.

Register	R/W	RS	DB7	DB6	DB5	DB4	DB3	DB2	DB1	DB0
Instruction reg.	0	1	0	0	0	0	0	0	0	0
Mode control reg.	0	0	0	0			Mode data

DB5	DB4	DB3	DB2	DB1	DB0	Cursor/blink
1/0	1/0	0	0	0	0	Cursor off
		0	1			Cursor on
		1	0			Cursor off, character blink
		1	1			Cursor blink
					1	Cursor off
		0	0
		0	1			Cursor on
		1	0			Cursor off, character blink
		1	1			Cursor blink
		0	0	1	0
Display ON/OFF	Master/slave	Blink	Cursor	Graphic/character mode	Ext./Int. CG

1: Master mode 0: Slave mode

1: Display ON

0: Display OFF

CG

External CG Internal CG

Graphic/character

display

Character display (Character mode)

Graphic mode

9

HD61830/HD61830B

2. Set Character Pitch: (Execution time: 4 s) Vp indicates the number of vertical dots per character. The space between the vertically-displayed characters is included in the determination. This value is meaningful only during character display (in the character mode) and becomes invalid in the graphic mode.

H p indicates the number of horizontal dots per character in display, including the space between horizontally-displayed characters. In the graphic mode, the Hp indicates the number of bits of 1-byte display data to be displayed.

There are three Hp values (Table 1).

Register	R/W	RS	DB7	DB6	DB5	DB4	DB3	DB2	DB1	DB0
Instruction reg.	0	1	0	0	0	0	0	0	0	1
Character pitch reg.	0	0		(Vp – 1) binary			0	(Hp – 1) binary

Table 1	Hp Values
Hp	DB2	DB1	DB0											Horizontal Character Pitch
6	1	0	1					6
7	1	1	0					7
8	1	1	1					8

10

HD61830/HD61830B

3. Set Number of Characters: (Execution time: 4 µs) HN indicates the number of horizontal characters in the character mode or the number of horizontal bytes in the graphic mode. If the total sum of horizontal dots on the screen is taken as n,

n = Hp × HN

HN can be set to an even number from 2 to 128 (decimal).

Register	R/W	RS	DB7	DB6	DB5	DB4	DB3	DB2	DB1	DB0
Instruction reg.	0	1	0	0	0	0	0	0	1	0
Number-of-characters reg.	0	0	0			(HN – 1) binary

4. Set Number of Time Divisions (Inverse of Display Duty Ratio): (Execution time: 4 µs) NX indicates the number of time divisions in multiplex display.

1/NX is the display duty ratio.

A value of 1 to 128 (decimal) can be set to NX.

Register	R/W	RS	DB7	DB6	DB5	DB4	DB3	DB2	DB1	DB0
Instruction reg.	0	1	0	0	0	0	0	0	1	1
Number-of-time-divisions reg.	0	0	0			(NX – 1) binary

5. Set Cursor Position: (Execution time: 4 µs) Cp indicates the position in a character where the cursor is displayed in the character mode. For example, in 5 × 7 dot font, the cursor is displayed under a character by specifying Cp = 8 (decimal). The cursor horizontal length is equal to the horizontal character pitch H p. A value of 1 to 16 (decimal) can be set to Cp. If a smaller value than the vertical character pitch Vp is set (Cp ≤ Vp), and a character overlaps with the cursor, the cursor has higher priority of display (at cursor display on). If Cp is greater than Vp, no cursor is displayed. The cursor horizontal length is equal to Hp.

Register	R/W	RS			DB7										DB6							DB5	DB4	DB3	DB2	DB1	DB0
Instruction reg.	0	1		0											0							0	0	0	1	0	0
Cursor position reg.	0	0		0											0							0	0		(Cp – 1) binary

11

HD61830/HD61830B

6. Set Display Start Low Order Address: (Execution time: 4 s) Cause display start addresses to be written in the display start address registers. The display start address indicates a RAM address at which the data displayed at the top left end on the screen is stored. In the graphic mode, the start address is composed of high/low order 16 bits. In the character display, it is composed of the lower 4 bits of high order address (DB3–DB0) and 8 bits of low order address. The upper 4 bits of high order address are ignored.

Register	R/W	RS	DB7	DB6	DB5	DB4	DB3	DB2		DB1	DB0
Instruction reg.	0	1	0	0	0	0	1	0		0	0
Display start address reg.	0	0			(Start low order address) binary
(low order byte)

Set Display Start High Order Address

Register	R/W	RS	DB7	DB6		DB5	DB4	DB3	DB2		DB1	DB0
Instruction reg.	0	1	0	0		0	0	1	0		0	1
Display start address reg.	0	0			(Start high order address) binary
(high order byte)

7. Set Cursor Address (Low Order) (RAM Write Low Order Address): (Execution time: 4 s) Cause cursor addresses to be written in the cursor address counters. The cursor address indicates an address for sending or receiving display data and character codes to or from the RAM.

That is, data at the address specified by the cursor address are read/written. In the character mode, the cursor is displayed at the character specified by the cursor address.

A cursor address consists of the low-order address (8 bits) and the high-order address (8 bits). Satisfy the following requirements setting the cursor address (Table 2).

The cursor address counter is a 16-bit up-counter with set and reset functions. When bit N changes from 1 to 0, bit N + 1 is incremented by 1. When setting the low order address, the LSB (bit 1) of the high order address is incremented by 1 if the MSB (bit 8) of the low order address changes from 1 to 0. Therefore, set both the low order address and the high order address as shown in the Table 2.

Register	R/W	RS			DB7										DB6								DB5	DB4	DB3	DB2		DB1	DB0
Instruction reg.	0	1		0											0								0	0	1	0		1	0
Cursor address counter	0	0																				(Cursor low order address) binary
(low order byte)

12

HD61830/HD61830B

Set Cursor Address (High Order) (RAM Write High Order Address)

Register	R/W	RS	DB7	DB6	DB5	DB4	DB3	DB2	DB1	DB0
Instruction reg.	0	1	0	0	0	0	1	0	1	1
Cursor address counter	0	0		(Cursor high order address) binary
(high order byte)

Table 2	Cursor Address Setting
Condition		Requirement
When you want to rewrite (set ) both the low order		Set the low order address and then set the high
address and the high order address.		order address.
When you want to rewrite only the low order address.		Do not fail to set the high order address again after
		setting the low order address.

When you want to rewrite only the high order address. Set the high order address. You do not have to set the low order address again.

13