Hitachi hd44780u schematic

HD44780U (LCD-II)

(Dot Matrix Liquid Crystal Display Controller/Driver)

ADE-207-272(Z)

'99.9

Rev. 0.0

Description

The HD44780U dot-matrix liquid crystal display controller and driver LSI displays alphanumerics,
Japanese kana characters, and symbols. It can be configured to drive a dot-matrix liquid crystal display
under the control of a 4- or 8-bit microprocessor. Since all the functions such as display RAM, character
generator, and liquid crystal driver, required for driving a dot-matrix liquid crystal display are internally
provided on one chip, a minimal system can be interfaced with this controller/driver.

A single HD44780U can display up to one 8-character line or two 8-character lines.

The HD44780U has pin function compatibility with the HD44780S which allows the user to easily replace
an LCD-II with an HD44780U. The HD44780U character generator ROM is extended to generate 208 5 ×
8 dot character fonts and 32 5 × 10 dot character fonts for a total of 240 different character fonts.

The low power supply (2.7V to 5.5V) of the HD44780U is suitable for any portable battery-driven product
requiring low power dissipation.

Features

• 5 × 8 and 5 × 10 dot matrix possible

• Low power operation support:
 2.7 to 5.5V

• Wide range of liquid crystal display driver power
 3.0 to 11V

• Liquid crystal drive waveform
 A (One line frequency AC waveform)

• Correspond to high speed MPU bus interface
 2 MHz (when VCC = 5V)

• 4-bit or 8-bit MPU interface enabled

• 80 × 8-bit display RAM (80 characters max.)

• 9,920-bit character generator ROM for a total of 240 character fonts
 208 character fonts (5 × 8 dot)
 32 character fonts (5 × 10 dot)

1

HD44780U

• 64 × 8-bit character generator RAM
 8 character fonts (5 × 8 dot)
 4 character fonts (5 × 10 dot)

• 16-common × 40-segment liquid crystal display driver

• Programmable duty cycles
 1/8 for one line of 5 × 8 dots with cursor
 1/11 for one line of 5 × 10 dots with cursor
 1/16 for two lines of 5 × 8 dots with cursor

• Wide range of instruction functions:
 Display clear, cursor home, display on/off, cursor on/off, display character blink, cursor shift,

display shift

• Pin function compatibility with HD44780S

• Automatic reset circuit that initializes the controller/driver after power on

• Internal oscillator with external resistors

• Low power consumption

Ordering Information

Type No. Package CGROM

HD44780UA00FS
HCD44780UA00
HD44780UA00TF

HD44780UA02FS
HCD44780UA02
HD44780UA02TF

HD44780UBxxFS
HCD44780UBxx
HD44780UBxxTF

Note: xx: ROM code No.

FP-80B
Chip
TFP-80F

FP-80B
Chip
TFP-80F

FP-80B
Chip
TFP-80F

Japanese standard font

European standard font

Custom font

2

HD44780U Block Diagram

HD44780U

RS
R/W
E

DB4 to
DB7

DB0 to
DB3

Reset
circuit

ACL

MPU
inter-

face

Input/

output

buffer

Instruction

register (IR)

8

Instruction

decoder

7

Data

8

register

(DR)

Busy

flag

OSC1 OSC2

CPG

Address

counter

7

8 8

Display
data RAM
(DDRAM)

80 × 8 bits

7

8

8

7

Timing

generator

40-bit

shift

register

40

16-bit

shift

register

40-bit

latch

circuit

Common

signal
driver

Segment

signal
driver

LCD drive

voltage

selector

CL1
CL2

M

D

COM1 to
COM16

SEG1 to
SEG40

GND

V

CC

Character
generator

Character

generator

RAM

(CGRAM)

64 bytes

(CGROM)

9,920 bits

Parallel/serial converter

V1 V2 V3 V4 V5

ROM

controller

55

and

attribute circuit

Cursor

and

blink

3

HD44780U

HD44780U Pin Arrangement (FP-80B)

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

807978777675747372717069686766

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

65

SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10

SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1

GND

OSC1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

FP-80B

(Top view)

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

SEG39
SEG40
COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DB7
DB6
DB5
DB4
DB3
DB2

252627282930313233343536373839

D

V1V2V3V4V5

OSC2

CL1

CL2

V

CC

M

RS

R/W

40

E

DB0

DB1 SEG38

4

HD44780U Pin Arrangement (TFP-80F)

SEG21

SEG22

SEG23

SEG24

SEG25

SEG26

SEG27

SEG28

80797877767574737271706968676665646362

SEG29

SEG30

SEG31

SEG32

SEG33

SEG34

SEG35

SEG36

SEG37

SEG38

SEG39

SEG40

61

HD44780U

SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10

SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

21222324252627282930313233343536373839

V1V2V3V4V5

GND

OSC1

OSC2

TFP-80F

(Top view)

CC

V

CL1

CL2

40

RS

R/W

E

DB0

DB1

DB2

DB3

D

M

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

COM16
COM15
COM14
COM13
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
DB7
DB6
DB5
DB4

5

HD44780U

HD44780U Pad Arrangement

Chip size:
Coordinate:
Origin:
Pad size:

2 1 80 63

Y

4.90 × 4.90 mm
Pad center (µm)
Chip center
114 × 114 µm

Type code

2

2

23

HD44780U

42

X

6

HD44780U

HCD44780U Pad Location Coordinates

Coordinate Coordinate

Pad No. Function X (um) Y (um) Pad No. Function X (um) Y (um)

1 SEG22 –2100 2313 41 DB2 2070 –2290
2 SEG21 –2280 2313 42 DB3 2260 –2290
3 SEG20 –2313 2089 43 DB4 2290 –2099
4 SEG19 –2313 1833 44 DB5 2290 –1883
5 SEG18 –2313 1617 45 DB6 2290 –1667
6 SEG17 –2313 1401 46 DB7 2290 –1452
7 SEG16 –2313 1186 47 COM1 2313 –1186
8 SEG15 –2313 970 48 COM2 2313 –970

9 SEG14 –2313 755 49 COM3 2313 –755
10 SEG13 –2313 539 50 COM4 2313 –539
11 SEG12 –2313 323 51 COM5 2313 –323
12 SEG11 –2313 108 52 COM6 2313 –108
13 SEG10 –2313 –108 53 COM7 2313 108
14 SEG9 –2313 –323 54 COM8 2313 323
15 SEG8 –2313 –539 55 COM9 2313 539
16 SEG7 –2313 –755 56 COM10 2313 755
17 SEG6 –2313 –970 57 COM11 2313 970
18 SEG5 –2313 –1186 58 COM12 2313 1186
19 SEG4 –2313 –1401 59 COM13 2313 1401
20 SEG3 –2313 –1617 60 COM14 2313 1617
21 SEG2 –2313 –1833 61 COM15 2313 1833
22 SEG1 –2313 –2073 62 COM16 2313 2095
23 GND –2280 –2290 63 SEG40 2296 2313
24 OSC1 –2080 –2290 64 SEG39 2100 2313
25 OSC2 –1749 –2290 65 SEG38 1617 2313
26 V1 –1550 –2290 66 SEG37 1401 2313
27 V2 –1268 –2290 67 SEG36 1186 2313
28 V3 –941 –2290 68 SEG35 970 2313
29 V4 –623 –2290 69 SEG34 755 2313
30 V5 –304 –2290 70 SEG33 539 2313
31 CL1 –48 –2290 71 SEG32 323 2313
32 CL2 142 –2290 72 SEG31 108 2313
33 V
34 M 475 –2290 74 SEG29 –323 2313
35 D 665 –2290 75 SEG28 –539 2313
36 RS 832 –2290 76 SEG27 –755 2313
37 R/W 1022 –2290 77 SEG26 –970 2313
38 E 1204 –2290 78 SEG25 –1186 2313
39 DB0 1454 –2290 79 SEG24 –1401 2313
40 DB1 1684 –2290 80 SEG23 –1617 2313

CC

309 –2290 73 SEG30 –108 2313

7

HD44780U

Pin Functions

No. of

Signal

RS 1 I MPU Selects registers.

R/W 1 I MPU Selects read or write.

E 1 I MPU Starts data read/write.
DB4 to DB7

DB0 to DB3 4 I/O MPU Four low order bidirectional tristate data bus pins.

CL1 1 O Extension driver Clock to latch serial data D sent to the extension

CL2 1 O Extension driver Clock to shift serial data D
M 1 O Extension driver Switch signal for converting the liquid crystal

D 1 O Extension driver Character pattern data corresponding to each

COM1 to COM16 16 O LCD Common signals that are not used are changed

SEG1 to SEG40 40 O LCD Segment signals
V1 to V5 5 — Power supply Power supply for LCD drive

VCC, GND 2 — Power supply VCC: 2.7V to 5.5V, GND: 0V
OSC1, OSC2 2 — Oscillation

Lines I/O

4 I/O MPU Four high order bidirectional tristate data bus

Device
Interfaced with Function

0: Instruction register (for write) Busy flag:

address counter (for read)

1: Data register (for write and read)

0: Write
1: Read

pins. Used for data transfer and receive between
the MPU and the HD44780U. DB7 can be used
as a busy flag.

Used for data transfer and receive between the
MPU and the HD44780U.
These pins are not used during 4-bit operation.

driver

drive waveform to AC

segment signal

to non-selection waveforms. COM9 to COM16
are non-selection waveforms at 1/8 duty factor
and COM12 to COM16 are non-selection
waveforms at 1/11 duty factor.

V

–V5 = 11 V (max)

CC

When crystal oscillation is performed, a resistor

resistor clock

must be connected externally. When the pin input
is an external clock, it must be input to OSC1.

8

HD44780U

Function Description

Registers

The HD44780U has two 8-bit registers, an instruction register (IR) and a data register (DR).

The IR stores instruction codes, such as display clear and cursor shift, and address information for display
data RAM (DDRAM) and character generator RAM (CGRAM). The IR can only be written from the MPU.

The DR temporarily stores data to be written into DDRAM or CGRAM and temporarily stores data to be
read from DDRAM or CGRAM. Data written into the DR from the MPU is automatically written into
DDRAM or CGRAM by an internal operation. The DR is also used for data storage when reading data
from DDRAM or CGRAM. When address information is written into the IR, data is read and then stored
into the DR from DDRAM or CGRAM by an internal operation. Data transfer between the MPU is then
completed when the MPU reads the DR. After the read, data in DDRAM or CGRAM at the next address is
sent to the DR for the next read from the MPU. By the register selector (RS) signal, these two registers can
be selected (Table 1).

Busy Flag (BF)

When the busy flag is 1, the HD44780U is in the internal operation mode, and the next instruction will not
be accepted. When RS = 0 and R/ W = 1 (Table 1), the busy flag is output to DB7. The next instruction
must be written after ensuring that the busy flag is 0.

Address Counter (AC)

The address counter (AC) assigns addresses to both DDRAM and CGRAM. When an address of an
instruction is written into the IR, the address information is sent from the IR to the AC. Selection of either
DDRAM or CGRAM is also determined concurrently by the instruction.

After writing into (reading from) DDRAM or CGRAM, the AC is automatically incremented by 1
(decremented by 1). The AC contents are then output to DB0 to DB6 when RS = 0 and R/W = 1 (Table 1).

Table 1 Register Selection

RS R/W Operation

0 0 IR write as an internal operation (display clear, etc.)
0 1 Read busy flag (DB7) and address counter (DB0 to DB6)
1 0 DR write as an internal operation (DR to DDRAM or CGRAM)
1 1 DR read as an internal operation (DDRAM or CGRAM to DR)

9

HD44780U

Display Data RAM (DDRAM)

Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its extended
capacity is 80 × 8 bits, or 80 characters. The area in display data RAM (DDRAM) that is not used for
display can be used as general data RAM. See Figure 1 for the relationships between DDRAM addresses
and positions on the liquid crystal display.

The DDRAM address (ADD) is set in the address counter (AC) as hexadecimal.

• 1-line display (N = 0) (Figure 2)

 When there are fewer than 80 display characters, the display begins at the head position. For

example, if using only the HD44780, 8 characters are displayed. See Figure 3.
When the display shift operation is performed, the DDRAM address shifts. See Figure 3.

AC
(hexadecimal)

Display position
(digit)

DDRAM
address
(hexadecimal)

High order

bits

AC6AC5 AC4 AC3AC2 AC1AC0

Low order

bits

Figure 1 DDRAM Address

123 45 7980

00 01 02 03 04 4E 4F

Figure 2 1-Line Display

Display
position

DDRAM
address

For
shift left

For
shift right

12345678

00 01 02 03 04 05 06 07

01 02 03 04 05 06 07 08

00 01 02 03 04 05 06

4F

Example: DDRAM address 4E

1001110

. . . . . . . . . . . . . . . . . .

10

Figure 3 1-Line by 8-Character Display Example

HD44780U

• 2-line display (N = 1) (Figure 4)

 Case 1: When the number of display characters is less than 40 × 2 lines, the two lines are displayed

from the head. Note that the first line end address and the second line start address are not
consecutive. For example, when just the HD44780 is used, 8 characters × 2 lines are displayed. See
Figure 5.

When display shift operation is performed, the DDRAM address shifts. See Figure 5.

Display
position

DDRAM
address
(hexadecimal)

123 45 3940

00 01 02 03 04 26 27
40 41 42 43 44 66 67

. . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . .

Figure 4 2-Line Display

Display
position

DDRAM
address

For
shift left

For
shift right

12345678

00 01 02 03 04 05 06 07
40 41 42 43 44 45 46 47

01 02 03 04 05 06 07 08
41 42 43 44 45 46 47 48

00 01 02 03 04 05 06

27

40 41 42 43 44 45 46

67

Figure 5 2-Line by 8-Character Display Example

11

HD44780U

 Case 2: For a 16-character × 2-line display, the HD44780 can be extended using one 40-output

extension driver. See Figure 6.
When display shift operation is performed, the DDRAM address shifts. See Figure 6.

Display
position

DDRAM
address

For
shift left

For
shift right

1 2345678910111213141516

00 01 02 03 04 05 06 07 08 09 0A 0B0C0D0E0F

40 41 42 43 44 45 46 47 48 49 4A 4B4C4D4E4F

HD44780U display Extension driver

display

0201 0304 05 06 07 08 09 0A 0B0C0D0E0F10

4142 43 44 45 46 47 48 49 4A 4B4C4D4E 4F 50

00 01 02 03 04 05 06 07 08 09 0A 0B0C0D0E27

40 41 42 43 44 45 46 47 48 49 4A 4B4C4D4E67

Figure 6 2-Line by 16-Character Display Example

12

HD44780U

Character Generator ROM (CGROM)

The character generator ROM generates 5 × 8 dot or 5 × 10 dot character patterns from 8-bit character
codes (Table 4). It can generate 208 5 × 8 dot character patterns and 32 5 × 10 dot character patterns. User­defined character patterns are also available by mask-programmed ROM.

Character Generator RAM (CGRAM)

In the character generator RAM, the user can rewrite character patterns by program. For 5 × 8 dots, eight
character patterns can be written, and for 5 × 10 dots, four character patterns can be written.

Write into DDRAM the character codes at the addresses shown as the left column of Table 4 to show the
character patterns stored in CGRAM.

See Table 5 for the relationship between CGRAM addresses and data and display patterns.

Areas that are not used for display can be used as general data RAM.

Modifying Character Patterns

• Character pattern development procedure

The following operations correspond to the numbers listed in Figure 7:

1. Determine the correspondence between character codes and character patterns.

2. Create a listing indicating the correspondence between EPROM addresses and data.

3. Program the character patterns into the EPROM.

4. Send the EPROM to Hitachi.

5. Computer processing on the EPROM is performed at Hitachi to create a character pattern listing, which

is sent to the user.

6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples

are sent to the user for evaluation. When it is confirmed by the user that the character patterns are
correctly written, mass production of the LSI proceeds at Hitachi.

13

HD44780U

UserHitachi

Start

Computer

processing

Create character

pattern listing

No

Evaluate

character

patterns

OK?

Yes

Art work

M/T

Masking

Trial

Determine

character patterns

5

Create EPROM

address data listing

Write EPROM

EPROM → Hitachi

1

2

3

4

14

Sample

Sample

evaluation

OK?

Yes

Mass

production

Note: For a description of the numbers used in this figure, refer to the preceding page.

6

No

Figure 7 Character Pattern Development Procedure

HD44780U

• Programming character patterns

This section explains the correspondence between addresses and data used to program character patterns
in EPROM. The HD44780U character generator ROM can generate 208 5 × 8 dot character patterns and
32 5 × 10 dot character patterns for a total of 240 different character patterns.

 Character patterns

EPROM address data and character pattern data correspond with each other to form a 5 × 8 or 5 ×
10 dot character pattern (Tables 2 and 3).

Table 2 Example of Correspondence between EPROM Address Data and Character Pattern

(5 × 8 Dots)

EPROM Address

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

A11

0 0 0 0

0 0 0 1

0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1

0 1 1 0

0 1 1 0 0 0 1 0

Character code

Notes: 1. EPROM addresses A11 to A4 correspond to a character code.

2. EPROM addresses A3 to A0 specify a line position of the character pattern.

3. EPROM data O4 to O0 correspond to character pattern data.

4. EPROM data O5 to O7 must be specified as 0.

5. A lit display position (black) corresponds to a 1.

6. Line 9 and the following lines must be blanked with 0s for a 5 × 8 dot character fonts.

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1
1 1 0 0

1 1 0 1
1 1 1 0
1 1 1 1

Line
position

O4 O3 O2 O1 O0

Data

LSB

1 0 0 0 0
1 0 0 0 0
1 0 1 1 0
1 1 0 0 1
1 0 0 0 1
1 0 0 0 1
1 1 1 1 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0

0 0 0 0 0
0 0 0 0 0

0 0 0 0 0

Cursor position

15

HD44780U

 Handling unused character patterns

1. EPROM data outside the character pattern area: Always input 0s.

2. EPROM data in CGRAM area: Always input 0s. (Input 0s to EPROM addresses 00H to FFH.)

3. EPROM data used when the user does not use any HD44780U character pattern: According to the user
application, handled in one of the two ways listed as follows.

a. When unused character patterns are not programmed: If an unused character code is written into

DDRAM, all its dots are lit. By not programing a character pattern, all of its bits become lit. (This is
due to the EPROM being filled with 1s after it is erased.)

b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused

character codes are written into DDRAM. (This is equivalent to a space.)

Table 3 Example of Correspondence between EPROM Address Data and Character Pattern

(5 × 10 Dots)

EPROM Address

A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

A11

0 0 0 0

0 0 0 1

0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1

0 1 1 0

0 1 0 1 0 0 1 0

Character code

Notes: 1. EPROM addresses A11 to A3 correspond to a character code.

2. EPROM addresses A3 to A0 specify a line position of the character pattern.

3. EPROM data O4 to O0 correspond to character pattern data.

4. EPROM data O5 to O7 must be specified as 0.

5. A lit display position (black) corresponds to a 1.

6. Line 11 and the following lines must be blanked with 0s for a 5 × 10 dot character fonts.

0 1 1 1
1 0 0 0
1 0 0 1

1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1

1 1 1 0
1 1 1 1

Line
position

Data

LSB

O4 O3 O2 O1 O0

0 0 0 0 0
0 0 0 0 0
0 1 1 0 1
1 0 0 1 1
1 0 0 0 1
1 0 0 0 1
0 1 1 1 1
0 0 0 0 1
0 0 0 0 1
0 0 0 0 1
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0

Cursor position

16

HD44780U

Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A00)

Upper 4

Lower
4 Bits

xxxx0000

Bits

0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111

0001 1000 1001

CG

RAM

(1)

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

xxxx1001

xxxx1010

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

(2)

(3)

xxxx1011

xxxx1100

xxxx1101

xxxx1110

xxxx1111

(4)

(5)

(6)

(7)

(8)

Note: The user can specify any pattern for character-generator RAM.

17

HD44780U

Table 4 Correspondence between Character Codes and Character Patterns (ROM Code: A02)

Upper 4

Lower
4 Bits

xxxx0000

0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111

Bits

0001 1000 1001

CG

RAM

(1)

xxxx0001

xxxx0010

xxxx0011

xxxx0100

xxxx0101

xxxx0110

xxxx0111

xxxx1000

xxxx1001

xxxx1010

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(1)

(2)

(3)

xxxx1011

xxxx1100

xxxx1101

xxxx1110

xxxx1111

18

(4)

(5)

(6)

(7)

(8)