Page 1
查询HD404354供应商
Description
The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program
productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input
capture timer, and two low-power dissipation modes.
HD404358 Series
Rev. 6.0
Sept. 1998
The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the
HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the
HD407A4359 with 16-kword PROM.
The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum
instruction cycle time: 0.47 µs)
The HD407A4359 is a PROM version (ZTATmicrocomputer). A program can be written to the PROM
by a PROM writer, which can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The ZTAT version is 27256-compatible.)
ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• 34 I/O pins
One input-only pin
33 input/output pins: 4 pins are intermediate-voltage NMOS open drain with high-current pins (15
mA, max.)
• On-chip A/D converter (8-bit × 8-channel)
Low power voltage 2.7 V to 6.0 V
• Three timers
One event counter input
One timer output
One input capture timer
• Eight-bit clock-synchronous serial interface (1 channel)
• Alarm output
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HD404358 Series
• Built-in oscillators
Ceramic oscillator or crystal
External clock drive is also possible
• Seven interrupt sources
Two by external sources
Three by timers
One by A/D converter
One by serial interface
• Two low-power dissipation modes
Standby mode
Stop mode
• Instruction cycle time
0.47 µs (f
HD40A4354, HD40A4356, HD40A4358,
HD407A4359
0.8 µs (f
HD404354, HD404356, HD404358
= 8.5 MHz, 1/4 division ratio):
OSC
= 5 MHz, 1/4 division ratio):
OSC
Ordering Information
Instruction Cycle
Type
Mask ROM Standard versions HD404354 HD404354S 4,096 384 DP-42S
ZTAT (f
Time Product Name Model Name
(f
= 5 MHz) HD404354H FP-44A
OSC
HD404356 HD404356S 6,144 DP-42S
HD404356H FP-44A
HD404358 HD404358S 8,192 DP-42S
HD404358H FP-44A
High speed versions HD40A4354 HD40A4354S 4,096 384 DP-42S
(f
= 8.5 MHz) HD40A4354H FP-44A
OSC
HD40A4356 HD40A4356S 6,144 DP-42S
HD40A4356H FP-44A
HD40A4358 HD40A4358S 8,192 DP-42S
HD40A4358H FP-44A
= 8.5 MHz) HD407A4359 HD407A4359S 16,384 512 DP-42S
OSC
HD407A4359H FP-44A
ROM
(Words)
RAM
(Digit) Package
2
Page 3
Pin Arrangement
RA
R00/SCK
R0
/SI
1
R0
/SO
2
R0
/TOC
3
TEST
RESET
OSC
OSC
GND
AV
SS
R30/AN
R31/AN
R32/AN
R33/AN
R40/AN
R41/AN
R42/AN
R43/AN
AV
CC
V
CC
HD404358 Series
1
1
2
3
4
5
6
7
1
8
2
9
10
11
12
0
13
1
14
2
15
3
16
4
17
5
18
6
19
7
DP-42S
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R2
3
R2
2
R2
1
R2
0
R1
3
R1
2
R1
1
R1
0
R8
3
R8
2
R8
1
R8
0
D
8
D
7
D
6
D
5
D4/STOPC
D
/BUZZ
3
D
/EVNB
2
D
/INT
1
1
D
/INT
0
0
TEST
RESET
OSC
OSC
GND
AV
R30/AN
R31/AN
R32/AN
R33/AN
R40/AN
SS
/TOC
NC
R03R02R01R00RA1R23R22R21R20R1
3
/SCK
/SI
/SO
4443424140393837363534
1
2
3
1
4
2
5
6
7
0
8
1
9
2
10
3
11
4
FP-44A
33
32
31
30
29
28
27
26
25
24
23
R1
R1
R1
R8
R8
R8
R8
D
D
D
D
2
1
0
3
2
1
0
8
7
6
5
1213141516171819202122
0
/INT
0
D
1
/INT
1
D
/BUZZ
/EVNB
3
2
D
D
NC
/STOPC
4
D
5
/AN
1
R4
6
/AN
2
R4
7
/AN
3
R4
CCVCC
AV
3
Page 4
HD404358 Series
Pin Description
Pin Number
Item Symbol DP-42S FP-44A I/O Function
Power
supply
Test TEST 6 1 I Cannot be used in user applications. Connect this pin
Reset RESET 7 2 I Resets the MCU
Oscillator OSC
Port D0–D
Interrupt INT0, INT122, 23 17, 18 I Input pins for external interrupts
Stop clear STOPC 26 21 I Input pin for transition from stop mode to active mode
Serial
Interface
Timer TOC 5 43 O Timer output pin
Alarm BUZZ 25 20 O Square waveform output pin
A/D
converter
V
CC
21 16 Applies power voltage
GND 10 5 Connected to ground
to GND.
8 3 I Input/output pin for the internal oscillator. Connect
1
these pins to the ceramic oscillator or crystal oscillator,
OSC
2
8
RA
1
R00–R13,
–R43,
R3
0
–R8
R8
0
or OSC
94O
22–30 17–21,
23–26
I/O Input/output pins addressed individually by bits; D0–D
are all standard-voltage I/O pins.
1 39 I One-bit standard-voltage input port pin
3
2–5,
12–19,
31–38
40–43,
7–14
27–34
I/O Four-bit input/output pins consisting of standard-voltage
pins
to an external oscillator circuit.
1
R20–R2339–42 35–38 I/O Four-bit input/output pins consisting of intermediate
voltage pins
SCK 2 40 I/O Serial interface clock input/output pin
SI 3 41 I Serial interface receive data input pin
SO 4 42 O Serial interface transmit data output pin
EVNB 24 19 I Event count input pin
AV
AV
CC
SS
20 15 Power supply for the A/D converter. Connect this pin
as close as possible to the V
voltage as V
. If the power supply voltage to be used
CC
for the A/D converter is not equal to V
µF bypass capacitor between the AV
(However, this is not necessary when the AV
directly connected to the V
pin and at the same
CC
, connect a 0.1-
CC
and AVSS pins.
CC
pin.)
CC
pin is
CC
11 6 Ground for the A/D converter. Connect this pin as
close as possible to GND at the same voltage as GND.
AN0–AN712–19 7–14 I Analog input pins for the A/D converter
8
4
Page 5
Block Diagram
INT
0
INT
1
EVNB
TOC
Interrupt
control
Timer A
Timer B
Timer C
STOPC
TEST
RESET
System control
RAM
(384 4 bits)
×
(512 4 bits)
×
1
OSC
2
VCCOSC
W
(2 bits)
X
(4 bits)
SPX
(4 bits)
Y
(4 bits)
SPY
(4 bits)
GND
HD404358 Series
D
0
D
1
D
2
D
3
D
4
D portR0 port
D
5
D
6
D
7
D
8
R0
0
R0
1
R0
2
R0
3
R1
0
R1
1
R1
R1 port
R1
2
3
SI
SO
SCK
AV
SS
AN
0
•
•
•
AN
7
AV
CC
BUZZ
Data bus
Intermediate
voltage pin
Directional
signal line
•
•
•
Serial
interface
A/D
converter
Buzzer
Internal address bus
Internal data bus
ST
(1 bit)CA(1 bit)
(4 bits)
(4 bits)
(10 bits)
Instruction
decoder
ROM
×
(4,096 10 bits) (6,144 10 bits)
×
(16,384 10 bits)(8,192 10 bits)
SP
A
B
ALU
(14 bits)
×
×
PC
Internal data bus
R2 port
R3 port
R4 port
R8 port
RA port
R2
R2
R2
R2
R3
R3
R3
R3
R4
R4
R4
R4
R8
R8
R8
R8
RA
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
1
5
Page 6
HD404358 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000-$0FFF (HD404354, HD40A4354), $0000–$17FF (HD404356, HD40A4356),
$0000–$1FFF (HD404358, HD40A4358), $0000–$3FFF (HD407A4359)): The entire ROM area can be
used for program coding.
$0000
$000F
$0010
$003F
$0040
$0FFF
$1000
$17FF
$1800
$1FFF
$2000
$3FFF
Vector address
(16 words)
Zero-page subroutine
(64 words)
Pattern (4,096 words)
Program (4,096 words)
For HD404354, HD40A4354
Program
(6,144 words)
For HD404356, HD40A4356
Program
(8,192 words)
For HD404358, HD40A4358
Program
(16,384 words)
HD407A4359
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(jump to RESET, STOPC routine)
JMPL instruction
(jump to INT routine)
JMPL instruction
(jump to INT routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to timer C routine)
JMPL instruction
(jump to A/D converter routine)
JMPL instruction
(jump to serial routine)
0
1
Note: Since the ROM address areas between $0000–$0FFF overlap, the user can
determine how these areas are to be used.
Figure 1 ROM Memory Map
6
Page 7
HD404358 Series
RAM Memory Map
The HD404354, HD40A4354, HD404356, HD40A4356, HD404358 and HD40A4358 MCUs contain 384digit × 4-bit RAM areas. The HD407A4359 MCU contain 512-digit × 4-bit RAM areas. Both of these
RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control
bits area, special function register area, and register flag area are mapped onto the same RAM memory
space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described
below.
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01F, $024–$03F)
This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023)
This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD,
and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on
using the instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($050–$17F for HD404354/HD40A4354/HD404356/HD40A4356/HD404358/HD40A4358,
$050–$1FF for HD407A4359)
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
7
Page 8
HD404358 Series
RAM Memory Map
$000 $000
$040
$050
$180
$200
$3C0
$3FF
RAM-mapped registers
Memory registers (MR)
HD404354, HD40A4354,
HD404356, HD40A4356,
HD404358, HD40A4358
Data (304 digits)
HD407A4359
Data (432 digits)
Not used
Stack (64 digits)
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$016
$017
$018
$019
$01A
Interrupt control bits area
Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)
Timer B (TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register (MIS)
Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)
A/D channel register (ACR)
A/D data register lower (ADRL)
A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)
Not used
Not used
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
R
R
W
W
Initial values
after reset
0000
0000
Undefined
Undefined
-000
0000
*2
/0000
Undefined
00--
0000
*2
/0000
Undefined
-000
0000
1000
0000
--00
*1
1. Two registers are mapped
Notes:
on the same area ($00A,
$00B, $00E, $00F).
2. Undefined.
R: Read only
W: Write only
R/W: Read/write
Timer read register B lower (TRBL)
$00A
Timer read register B upper (TRBU)
$00B
Timer read register C lower (TRCL)
$00E
Timer read register C upper (TRCU)
$00F
$020
$023
$024
$025
$026
Timer mode register B2 (TMB2)
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$038
$03F
Register flag area
Port mode register B (PMRB)
Port mode register C (PMRC)
Not used
Port D0–D
Port D4–D
Port D DCR
Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)
Port R4 DCR (DCR4)
Port R8 DCR (DCR8)
R
R
R
R
DCR
3
DCR
7
8
Not used
Not used
Not used
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
Figure 2 RAM Memory Map
(DCD0)
(DCD1)
(DCD2)
0000
W
00-0
W
-000
W
W
0000
0000
W
---0
W
0000
W
0000
W
W
0000
0000
W
0000
W
0000W
W
W
W
W
8
Page 9
0
1
Bit 3 Bit 2 Bit 1 Bit 0
IM0
INT
(IM of
(IM of timer A)
0
IMTA
)
IF0
INT
(IF of
(IF of timer A)
0
IFTA
)
RSP
(Reset SP bit)
IM1
(IM of INT
1
)
IE
(Interrupt
enable flag)
IF1
(IF of INT1)
HD404358 Series
$000
$001
2
3
32
33
34
35
IMTC
(IM of timer C)
IMS
(IM of serial)
Bit 3 Bit 2 Bit 1 Bit 0
Not used Not used
RAME
(RAM enable
flag)
IFTC
(IF of timer C)
IFS
(IF of serial)
Interrupt control bits area
ADSF
(A/D start flag)
IAOF
(I
off flag)
AD
Not used
Register flag area
IMTB
(IM of timer B)
IMAD
(IM of A/D)
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
IFTB
(IF of timer B)
IFAD
(IF of A/D)
ICSF
(Input capture
status flag)
$002
$003
$020
$021
$022
$023
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD REM/REMD TM/TMD
IE
IM
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
Not used
Allowed Allowed Allowed
Not executed Allowed Allowed
Not executed Allowed Inhibited
Allowed Not executed Inhibited
Allowed Inhibited Allowed
Not executed Not executed Inhibited
IF:
Interrupt request flag
Interrupt mask
IM:
Interrupt enable flag
IE:
Stack pointer
SP:
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
Page 10
HD404358 Series
$000
$003
PMRA $004
SMR $005
SRL $006
SRU $007
TMA $008
TMB1 $009
TRBL/TWBL $00A
TRBU/TWBU $00B
MIS $00C
TMC $00D
TRCL/TWCL $00E
TRCU/TWCU $00F
ACR $016
ADRL $017
ADRU $018
AMR1$019
AMR2 $01A
Bit 3 Bit 2 Bit 1
Interrupt control bits area
/BUZZ R03/TOC R02/SO
D
3
R0
0
/SCK
Serial transmit clock speed selection
R01/SI
Serial data register (lower digit)
Serial data register (upper digit)
Not used
*
1
Clock source selection (timer A)
Clock source selection (timer B)
Timer B register (lower digit)
Timer B register (upper digit)
*
2
*
1
SO PMOS control
Clock source selection (timer C)
Not used
Timer C register (lower digit)
Timer C register (upper digit)
Not used
Not used
Analog channel selection
A/D data register (lower digit)
A/D data register (upper digit)
/AN R32/AN
R3
3
3
Not used
R31/AN
2
R4/AN
4
–AN
1
7
Not used
Bit 0
R30/AN
*
3
0
$020
$023
PMRB $024
PMRC $025
TMB2 $026
DCD0 $02C
DCD1 $02D
DCD2 $02E
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
DCR4 $034
DCR8 $038
$03F
Register flag area
D
/STOPC
4
D2/EVNB*6D1/INT
Buzzer output
Not used
Not used
DCD
3
Port D
2
Port D6 DCD
Port D
Port D7 DCD
DCD
Not used
Not used
Port R0
DCR
Port R02 DCR
3
DCR
3
DCR
3
DCR
3
Port R12 DCR
DCR
Port R2
2
Port R3
DCR
2
Port R4
DCR
2
Port R13 DCR
Port R2
Port R3
Port R4
Not used
Port R83 DCR Port R82 DCR
Not used
Figure 5 Special Function Register Area
D0/INT
1
*4
0
*5
EVNB detection edge selection
Port D
DCD
Port D0 DCD
1
Port D5 DCD
Port D4 DCD
Port D8 DCD
Port R01 DCR
Port R11 DCR
Port R21 DCR
Port R3
Port R41 DCR
Port R8
Port R00 DCR
Port R10 DCR
Port R20 DCR
DCR
Port R3
1
DCR
0
Port R40 DCR
DCR Port R80 DCR
1
Notes:
1.
Auto-reload on/off
2.
Pull-up MOS control
3.
A/D conversion time
4.
SO output level control in idle states
5.
Serial clock source selection
6.
Input capture selection
10
Page 11
HD404358 Series
Memory registers
MR(0)
64
MR(1)
65
MR(2)
66
MR(3)
67
MR(4)
68
MR(5)
69
MR(6)
70
MR(7)
71
MR(8)
72
MR(9)
73
MR(10)
74
MR(11)
75
MR(12)
76
MR(13)
77
MR(14)
78
MR(15)
79
PC –PC :
13
ST: Status flag
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
Program counter
0
CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Stack area
960 $3C0
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
1023
Level 1
$3FF
1020
1021
1022
1023
Bit 3 Bit 2 Bit 1 Bit 0
ST
PC
CA
PC
PC
PC
10
PC
PC
3
PC
13
PC
9
PC
6
PC
2
PC
12
PC
8
PC
5
PC
1
$3FC
11
$3FD
7
$3FE
4
$3FF
0
11
Page 12
HD404358 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.
30
Accumulator
B register
W register
X register
Y register
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
(A)
30
(B)
0
1
(W)
30
(X)
30
(Y)
30
SPX register
SPY register
Carry
Status
Program counter
Initial value: 0,
no R/W
Stack pointer
Initial value: $3FF, no R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: 1, no R/W
13
95
1111
(SPX)
30
(SPY)
0
(CA)
0
(ST)
0
(PC)
0
(SP)
Figure 7 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
12
Page 13
HD404358 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,
not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,
CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or
bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,
regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack
during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.
The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
Reset
The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation,
RESET must be high for at least two instruction cycles.
Initial values after MCU reset are listed in table 1.
Interrupts
The MCU has 7 interrupt sources: two external signals (INT0 and INT1), three timer/counters (timers A, B,
and C), serial interface, and A/D converter.
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the
interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)
and the IF to 0 and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in
table 3.
13
Page 14
HD404358 Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
14
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HD404358 Series
Table 1 Initial Values After MCU Reset
Item Abbr. Initial Value Contents
Program counter (PC) $0000 Indicates program execution point
Status flag (ST) 1 Enables conditional branching
Stack pointer (SP) $3FF Stack level 0
Interrupt
flags/mask
I/O Port data register (PDR) All bits 1 Enables output at level 1
Timer/
counters,
serial
interface
Interrupt enable flag (IE) 0 Inhibits all interrupts
Interrupt request flag (IF) 0 Indicates there is no interrupt
Interrupt mask (IM) 1 Prevents (masks) interrupt requests
Data control register (DCD0 –
Port mode register A (PMRA) 0000 Refer to description of port mode
Port mode register B bits
2–0
Port mode register C (PMRC) 00 - 0 Refer to description of port mode
Timer mode register A (TMA) - 000 Refer to description of timer mode
Timer mode register B1 (TMB1) 0000 Refer to description of timer mode
Timer mode register B2 (TMB2) - 000 Refer to description of timer mode
Timer mode register C (TMC) 0000 Refer to description of timer mode
Serial mode register (SMR) 0000 Refer to description of serial mode
Prescaler S (PSS) $000 —
Timer counter A (TCA) $00 —
Timer counter B (TCB) $00 —
Timer counter C (TCC) $00 —
Timer write register B (TWBU,
Timer write register C (TWCU,
Octal counter 000 —
DCD1)
(DCD2) - - - 0
(DCR0 –
DCR4,
DCR8)
(PMRB2 –
PMRB0)
TWBL)
TWCL)
All bits 0 Turns output buffer off (to high
All bits 0
000 Refer to description of port mode
$X0 —
$X0 —
from start address of ROM area
request
impedance)
register A
register B
register C
register A
register B1
register B2
register C
register
15
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HD404358 Series
Initial
Item Abbr.
A/D A/D mode register 1 (AMR1) 0000 Refer to description of A/D mode register
A/D mode register 2 (AMR2) - - 00
A/D channel register (ACR) - 000 Refer to description of A/D channel register
A/D data register (ADRL) 0000 Refer to description of A/D data register
(ADRU) 1000
Bit registers Watchdog timer on flag (WDON) 0 Refer to description of timer C
A/D start flag (ADSF) 0 Refer to description of A/D converter
IAD off flag (IAOF) 0 Refer to the description of A/D converter
Input capture status flag (ICSF) 0 Refer to description of timer B
Input capture error flag (ICEF) 0 Refer to description of timer B
Others Miscellaneous register (MIS) 00 - - Refer to description of operati n g modes, I/O,
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist.
Value Contents
and serial interface
Status After Cancellation of
Item Abbr.
Carry flag (CA) Pre-stop-mode values are not
Accumulator (A)
B register (B)
W register (W)
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
Serial data register (SRL, SRU)
RAM Pre-stop-mode values are
RAM enable flag (RAME) 1 0
Port mode register
B bit 3
(PMRB3) Pre-stop-mode values are
Stop Mode by STOPC Input
guaranteed; values must be
initialized by program
retained
retained
Status After all Other Types of
Reset
Pre-MCU-reset values are not
guaranteed; values must be
initialized by program
0
16
Page 17
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt Priority Vector Address
RESET, STOPC* — $0000
INT
0
INT
1
Timer A 3 $0006
Timer B 4 $0008
Timer C 5 $000A
A/D 6 $000C
Serial 7 $000E
Note: * The STOPC interrupt request is valid only in stop mode.
1 $0002
2 $0004
HD404358 Series
17
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HD404358 Series
INT0 interrupt
interrupt
INT
1
Timer A interrupt
Timer B interrupt
Timer C interrupt
A/D interrupt
Serial interrupt
$ 000,0
IE
$ 000,2
IFO
$ 000,3
IMO
$ 001,0
IF1
$ 001,1
IM1
$ 001,2
IFTA
$ 001,3
IMTA
$ 002,0
IFTB
$ 002,1
IMTB
$ 002,2
IFTC
$ 002,3
IMTC
$ 003,0
IFAD
$ 003,1
IMAD
$ 003,2
IFS
$ 003,3
IMS
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
Vector
address
Priority control logic
18
Note: $m,n is RAM address $m, bit number n.
Figure 8 Interrupt Control Circuit
Page 19
HD404358 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
INT
0
INT
1
IE 1111111
IF0 · IM0 1000000
IF1 · IM1 * 100000
IFTA · IMTA **10000
IFTB · IMTB ***1000
IFTC · IMTC ****100
IFAD · IMAD **** *10
IFS · IMS ******1
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
123456
Timer A Timer B Timer C A/D Serial
Instruction
execution*
IE reset
Stacking
Vector address
generation
Execution of JMPL
instruction at vector address
Interrupt
acceptance
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
19
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HD404358 Series
Power on
RESET = 0?
Yes
Reset MCU
No
Interrupt
request?
No
Execute instruction
←
PC (PC) + 1
←
PC $0002
←
PC $0004
Yes
No
Accept interrupt
Yes
Yes
IE = 1?
Yes
←
IE 0
←
Stack (PC)
←
Stack (CA)
←
Stack (ST)
INT
0
interrupt?
No
INT
1
interrupt?
←
PC $0006
←
PC $0008
←
PC $000A
←
PC $000C
←
PC $000E
Yes
Yes
Yes
Yes
(serial interrupt)
Figure 10 Interrupt Processing Flowchart
No
Timer-A
interrupt?
No
Timer-B
interrupt?
No
Timer-C
interrupt?
No
A/D
interrupt?
No
20
Page 21
HD404358 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE Interrupt Enabled/Disabled
0 Disabled
1 Enabled
External Interrupts (INT0, INT1): Two external interrupt signals.
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising
edge of signals input to INT0 and INT1, as listed in table 5.
Table 5 External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)
IF0, IF1 Interrupt Request
0No
1 Yes
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.
Table 6 External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)
IM0, IM1 Interrupt Request
0 Enabled
1 Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA Interrupt Request
0No
1 Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as listed in table 8.
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HD404358 Series
Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA Interrupt Request
0 Enabled
1 Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.
Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB Interrupt Request
0No
1 Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer
B interrupt request flag, as listed in table 10.
Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB Interrupt Request
0 Enabled
1 Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.
Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC Interrupt Request
0No
1 Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as listed in table 12.
Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC Interrupt Request
0 Enabled
1 Disabled (masked)
22
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HD404358 Series
Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.
Table 13 Serial Interrupt Request Flag (IFS: $003, Bit 2)
IFS Interrupt Request
0No
1 Yes
Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.
Table 14 Serial Interrupt Mask (IMS: $003, Bit 3)
Mask IMS Interrupt Request
0 Enabled
1 Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in
table 15.
Table 15 A/D Interrupt Request Flag (IFAD: $003, Bit 0)
IFAD Interrupt Request
0No
1 Yes
A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 16.
Table 16 A/D Interrupt Mask (IMAD: $003, Bit 1)
IMAD Interrupt Request
0 Enabled
1 Disabled (masked)
23
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HD404358 Series
Operating Modes
The MCU has three operating modes as shown in table 17. The operations in each mode are listed in tables
18 and 19. Transitions between operating modes are shown in figure 11.
Table 17 Operating Modes and Clock Status
Mode Name
Active Standby Stop
Activation method RESET cancellation,
interrupt request, STOPC
cancellation in stop mode
Status System
oscillator
Cancellation
method
Note: OP implies in operation
OP OP Stopped
RESET input, STOP/ SBY
instruction
Table 18 Operations in Low-Power Dissipation Modes
SBY instruction STOP instruction
RESET input, interrupt
request
RESET input, STOPC
input in stop mode
Function Stop Mode Standby Mode
CPU Reset Retained
RAM Retained Retained
Timer A Reset OP
Timer B Reset OP
Timer C Reset OP
Serial Reset OP
A/D Reset OP
I/O Reset Retained
Note: OP implies in operation
Table 19 I/O Status in Low-Power Dissipation Modes
Output Input
Standby Mode Stop Mode Active Mode
RA
1
R0–D8, R0–R4,
R8,
— — Input enabled
Retained or output of
peripheral functions
High impedance Input enabled
24
Page 25
Reset by
RESET input or
by watchdog timer
RAME = 0 RAME = 1
RESET 1 RESET 2
HD404358 Series
Active
Standby mode Stop mode
mode
STOPC
SBY
Oscillate
f
:
OSC
:
Stop
ø
CPU
:
ø
f
cyc
PER
:
Main oscillation frequency
f
OSC
f
ø
ø
cyc
CPU
PER
:
/4
f
OSC
:
System clock
:
Clock for other peripheral
instruction
Interrupt
f
OSC
ø
ø
CPU
PER
:
Oscillate
:
f
cyc
f
:
cyc
STOP
instruction
f
OSC
ø
ø
CPU
PER
:
:
:
Stop
Stop
Stop
functions
Figure 11 MCU Status Transitions
Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC
and OSC2.
1
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.
The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation
in standby mode is shown in figure 12.
25
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HD404358 Series
Stop
Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop
No
RESET = 0?
No
STOPC = 0?
Yes
RAME = 1
Yes
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
Yes
No
IF0 • IMO = 1?
RESET = 0?
RAME = 0
Standby
Yes
IF1 • IM1 = 1?
No
Yes
No
IFTA • IMTA
= 1?
Yes
No
IFTB •
IMTB = 1?
Yes
No
IFTC •
IMTC = 1?
Yes
No
IFAD •
IMAD = 1?
Yes
No
IMS = 1?
IFS •
No
Yes
Restart
processor clocks
Reset MCU
Restart
processor clocks
Execute
next instruction
No
Execute
next instruction
IF = 1,
IM = 0, and
IE = 1?
Yes
Accept interrupt
Figure 12 MCU Operation Flowchart
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops.
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC
must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.
26
Page 27
HD404358 Series
Stop mode
Oscillator
Internal
clock
RESET
or STOPC
t
STOP instruction execution
≥ tRC (stabilization period)
res
Figure 13 Timing of Stop Mode Cancellation
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC
as well as by R E SE T . In either case, the MCU starts instruction execution from the starting address
(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by STOPC and by RESET. When stop mode is cancelled by R E SE T , RAME = 0;
when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop
mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop
mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is
used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.
t
res
MCU Operation Sequence: The MCU operates in the sequence shown in figure 15. It is reset by an
asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 0 ?
Yes
RAME = 0
Reset MCU
No
MCU
operation
cycle
Figure 14 MCU Operating Sequence (Power On)
27
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HD404358 Series
MCU operation
cycle
IF:
Interrupt request flag
IM:
Interrupt mask
IE:
Interrupt enable flag
PC:
Program counter
CA:
Carry flag
ST:
Status flag
Low-power mode
operation cycle
Yes
IF = 1?
No
Instruction
execution
SBY/STOP
instruction?
No
←
PC Next
location
Yes
No
IM = 0 and
IE = 1?
Yes
←
IE 0
Stack (PC),
←
(CA),
(ST)
←
PC Vector
address
28
Figure 15 MCU Operating Sequence (MCU Operation Cycle)
Page 29
Low-power mode
operation cycle
HD404358 Series
IF = 1 and
IM = 0?
Yes
Hardware NOP
execution
←
PC Next
Iocation
No
No
Standby mode
IF = 1 and
IM = 0?
Yes
Hardware NOP
execution
←
PC Next
Iocation
Instruction
execution
No
Stop mode
STOPC = 0?
Yes
RAME = 1
Reset MCU
MCU operation
cycle
For IF and IM operation, refer to figure 12.
Figure 16 MCU Operating Sequence (Low-Power Mode Operation)
29
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HD404358 Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 17. As shown in table 20, a ceramic
oscillator or crystal oscillator can be connected to OSC1 and OSC2. The system oscillator can also be
operated by an external clock. See figure 18 for the layout of crystal and ceramic oscillator.
OSC
OSC
1/4
f
cyc
t
cyc
Timing
generator
circuit
ø
CPU
ø
PER
f
2
1
System
oscillator
OSC
division
circuit
CPU with ROM,
RAM, registers,
flags, and I/O
Peripheral
function
interrupt
Figure 17 Clock Generation Circuit
TEST
RESET
OSC
1
OSC
2
GND
30
AV
SS
Figure 18 Typical Layout of Crystal and Ceramic Oscillator
Page 31
Table 20 Oscillator Circuit Examples
Circuit Configuration Circuit Constants
External clock
operation
External
oscillator
OSC
HD404358 Series
1
Ceramic oscillator
(OSC
, OSC2)
1
C
Ceramic
C
Open
1
2
OSC
2
Ceramic oscillator:
OSC
1
R
f
OSC
2
CSA4.00MG
(Murata)
= 1 MΩ ±20%
R
f
= C2 = 30 pF ±20%
C
1
GND
Crystal oscillator
(OSC
, OSC2)
1
C
Crystal
C
1
OSC
1
R
f
OSC
2
2
Rf = 1 MΩ ±20%
= C2 = 10 to 22 pF ±20%
C
1
Crystal: Equivalent to circuit
shown below
= 7 pF max.
C
0
= 100 Ω max.
R
S
GND
OSC
LSC
1
R
S
OSC
2
C
O
Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray
capacitance of the board, the user should consult with the crystal or ceramic oscillator
manufacturer to determine the circuit parameters.
2. Wiring among OSC
, OSC2, and elements should be as short as possible, and must not cross
1
other wiring (see figure 18).
31
Page 32
HD404358 Series
Input/Output
The MCU has 33 input/output pins (D0–D8, R0–R4, R8) and an input pin (RA1). The features are described
below.
• Four pins (R20–R23) are high-current (15 mA max) input/output with intermediate voltage NMOS open
drain pins.
• The D0–D4, R0, R3–R4 input/output pins are multiplexed with peripheral function pins such as for the
timers or serial interface. For these pins, the peripheral function setting is done prior to the D or R port
setting. Therefore, when a peripheral function is selected for a pin, the pin function and input/output
selection are automatically switched according to the setting.
• Input or output selection for input/output pins and port or peripheral function selection for multiplexed
pins are set by software.
• Peripheral function output pins are CMOS output pins. Only the R02/SO pin can be set to NMOS open-
drain output by software.
• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output
pins are in high-impedance state.
• Each input/output pin except for R2 has a built-in pull-up MOS, which can be individually turned on or
off by software.
I/O buffer configuration is shown in figure 19, programmable I/O circuits are listed in table 21, and I/O pin
circuit types are shown in table 22.
Table 21 Programmable I/O Circuits
MIS3 (bit 3 of MIS) 0 1
DCD, DCR 0 1 0 1
PDR 01010101
CMOS buffer PMOS ———On———On
NMOS — — On — — — On —
Pull-up MOS —————On—On
Note: — indicates off status.
32
Page 33
HD404358 Series
Pull-up
MOS
V
CC
V
CC
Input control signal
Pull-up control signal
Buffer control signal
Output data
HLT
MIS3
DCD, DCR
PDR
Input data
Figure 19 I/O Buffer Configuration
33
Page 34
HD404358 Series
Table 22 Circuit Configurations of I/O Pins
I/O Pin Type Circuit Pins
Input/output
pins
V
CC
V
CC
Input control signal
V
CC
V
CC
Input control signal
Pull-up control signal
Buffer control
signal
Output data
Input data
Pull-up control signal
Buffer control
signal
Output data
Input data
HLT
MIS3
DCR, DCD
PDR
HLT
MIS3
DCR
MIS2
PDR
HLT
D0–D8,
R0
R10–R13,
R3
R4
R8
R0
R20–R2
, R01, R0
0
–R33,
0
–R43,
0
–R8
0
3
2
3
3
Input pins
Peripheral
function pins
Input/output
pins
Notes on next page.
DCR
Output data
PDR
Input data
Input control signal
RA
Input data
1
Input control signal
V
CC
V
CC
Pull-up control signal
Output data
Input data
SCK
HLT
MIS3
SCK
SCK
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Page 35
HD404358 Series
I/O Pin Type Circuit Pins
Peripheral
function pins
Output pins
V
CC
V
CC
Pull-up control signal
PMOS control
signal
Output data
HLT
MIS3
MIS2
SO
SO
TOC, BUZZ
SI,
, INT1,
INT
0
EVNB, STOPC
AN0–AN
Input pins
V
CC
V
CC
V
CC
V
CC
Input control signal
Pull-up control signal
Output data
Input data
HLT
MIS3
TOC, BUZZ
HLT
MIS3
PDR
HLT
MIS3
PDR
A/D input
Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT
signal goes low, and input/output pins enter the high-impedance state.
2. The HLT signal is 1 in active and standby modes.
7
35
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HD404358 Series
Evaluation Chip Set and ZTAT/Mask ROM Product Differences
As shown in figure 20, the NMOS intermediate breakdown voltage open drain pin circuit in the evaluation
chip set differs from that used in the ZTAT microcomputer and built-in mask ROM microcomputer
products.
Please note that although these outputs in the ZTAT microcomputer and built-in mask ROM
microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs
cannot be set to high impedance in the evaluation chip set.
Table 23 Program Control of High Impedance States
Register Set Value
DCR 0 1
PDR * 1
Notes: *An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation.
This applies to the ZTAT and built-in mask ROM microcomputer NMOS open drain pins.
HLT
V
CC
V
CC
MIS3
DCR
PDR
CPU input
Input control signal
Evaluation Chip Set Circuit Structure
HLT
DCR
PDR
CPU input
Input control signal
ZTAT and Built-in Mask ROM Microcomputer Circuit Structure
Figure 20 NMOS Intermediate Breakdown Voltage Open Drain Pin Circuits
36
Page 37
HD404358 Series
D Port (D0–D8): Consist of 9 input/output pins addressed by one bit.
Pins D0–D8 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.
Output data is stored in the port data register (PDR) for each pin. All pins D0–D8 are tested by the TD and
TDD instructions.
The on/off statuses of the output buffers are cont rol l ed by D-port d at a control regis t ers (DC D0–DC D2: $02C–
$02E) that are mapped to memory addresses (figure 21).
Pins D0–D2, D4 are multiplexed with peripheral function pins INT0, INT1, EVNB, and STOPC,
respectively. The peripheral function modes of these pins are selected by bits 0–3 (PMRB0–PMRB3) of
port mode register B (PMRB: $024) (figure 22).
Pin D3 is multiplexed with peripheral function pin BUZZ. The peripheral function mode of this pin is
selected by bit 3 (PMRA3) of port mode register A (PMRA: $004) (figure 23).
R Ports (R00–R43, R8): 24 input/output pins addressed in 4-bit units. Data is input to these ports by the
LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output data is stored
in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R ports are
controlled by R-port data control registers (DCR0–DCR4: $030–$034, DCR8: $038) that are mapped to
memory addresses (figure 21).
Pin R00 is multiplexed with peripheral function pin SCK. The peripheral function mode of this pin is
selected by bit 3 (SMR3) of serial mode register (SMR: $005) (figure 24).
Pins R01–R03 are multiplexed with peripheral pins SI, SO and TOC, respectively. The peripheral function
modes of these pins are selected by bits 0–2 (PMRA0–PMRA2) of port mode register A (PMRA: $004), as
shown in figures 23.
Port R3 is multiplexed with peripheral function pins AN0–AN3, respectively. The peripheral function
modes of these pins can be selected by individual pins, by setting A/D mode register 1 (AMR1: $019)
(figure 25).
Ports R4 is multiplexed with peripheral function pins AN4–AN7, respectively. The peripheral function
modes of these pins can be selected in 4-pin units by setting bit 1 (AMR21) of A/D mode register 2
(AMR2: $01A) (figure 26).
Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each
input/output pin. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous
register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data
register (PDR) of the corresponding pin—enabling on/off control of that pin alone (table 21 and figure 27).
The on/off status of each transistor and the peripheral function mode of each pin can be set independently.
How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be
connected to VCC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by
their pull-up MOS transistors or by resistors of about 100 kΩ.
37
Page 38
HD404358 Series
Data control register
(DCD0 to 2: $02C to $02E)
(DCR0 to 4: $030 to $034, DCR8: $038)
DCD0, DCD2, DCR0 to DCR4, DCR8
Bit
Initial value
Read/Write
Bit name
3
0
W
DCD03,
DCD13,
DCR03–
DCR43,
DCR83
DCD02,
DCD12,
DCR02–
DCR42,
DCR82
Bits 0 to 3 CMOS Buffer On/Off Selection
0
1
Off (high-impedance)
On
Correspondence between ports and DCD/DCR bits
Register Name
DCD0
DCD1
DCD2
DCR0
DCR1
DCR2
DCR3
DCR4
DCR8
Bit 3
D
3
D
7
Not used
R0
3
R1
3
R2
3
R3
3
R4
3
R8
3
Bit 2
D
2
D
6
Not used
R0
2
R1
2
R2
2
R3
2
R4
2
R8
2
W
2
0
1
0
W
DCD01,
DCD11,
DCR01–
DCR41,
DCR81
Bit 1
D
1
D
5
Not used
R0
R1
R2
R3
R4
R8
DCD00–
DCD20,
DCR00–
DCR40,
DCR80
1
1
1
1
1
1
W
0
0
Bit 0
D
0
D
4
D
8
R0
0
R1
0
R2
0
R3
0
R4
0
R8
0
38
Figure 21 Data Control Registers (DCD, DCR)
Page 39
Port mode register B (PMRB: $024)
HD404358 Series
Bit
Initial value
Read/Write
Bit name
PMRB2
PMRB3
Note: PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not
*
D2/EVNB Mode Selection
0
D
1
EVNB
D4/STOPC Mode Selection
0
D
4
1
STOPC
2
3
0
W
PMRB3
*
PMRB2
W
2
0
1
0
W
PMRB1
0
0
W
PMRB0
PMRB0
0
1
PMRB1
0
1
D0/INT0 Mode Selection
D
0
INT
0
D1/INT1 Mode Selection
D
1
INT
1
reset but retains its value.
Figure 22 Port Mode Register B (PMRB)
Port mode register A (PMRA: $004)
Bit
Initial value
Read/Write
Bit name
PMRA2
0
1
PMRA3
0
1
3
0
W
PMRA3
2
0
W
PMRA2
R03/TOC Mode Selection
R0
3
TOC
D3/BUZZ Mode Selection
D
3
BUZZ
Figure 23 Port Mode Register A (PMRA)
1
0
W
PMRA1
0
0
W
PMRA0
PMRA0
0
1
PMRA1
0
1
R02/SO Mode Selection
R0
2
SO
R01/SI Mode Selection
R0
1
SI
39
Page 40
HD404358 Series
Serial mode register (SMR: $005)
Bit
Initial value
Read/Write
Bit name
3
0
W
SMR3
R00/SCK
SMR3
0
1
Mode Selection
R0
0
SCK
Figure 24 Serial Mode Register (SMR)
A/D mode register 1 (AMR1: $019)
Bit
Initial value
Read/Write
Bit name
3
0
W
AMR13
2
0
W
AMR12
2
0
W
SMR2
1
0
W
AMR11
1
0
W
SMR1
0
0
W
SMR0
SMR2 SMR0SMR1
Transmit clock selection.
Refer to figure 55 in the
serial interface section.
0
0
W
AMR10
AMR12
0
1
AMR13
0
1
R32/AN2 Mode Selection
R3
2
AN
2
R33/AN3 Mode Selection
R3
3
AN
3
Figure 25 A/D Mode Register 1 (AMR1)
AMR10
0
1
AMR11
0
1
R30/AN0 Mode Selection
R3
0
AN
0
R31/AN1 Mode Selection
R3
1
AN
1
40
Page 41
A/D mode register 2 (AMR2: $01A)
HD404358 Series
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
—
—
Not used
1
0
W
AMR21
AMR20
AMR20
AMR21
Figure 26 A/D Mode Register 2 (AMR2)
Miscellaneous register (MIS: $00C)
Bit
Initial value
Read/Write
Bit name
3
0
W
MIS3
2
0
W
MIS2
Not used
W
0
0
Conversion Time
0
1
34t
67t
cyc
cyc
R4/AN4–AN7 Pin Selection
0
1
—
—
R4
AN4–AN
1
7
0
—
—
Not used
Pull-Up MOS
MIS3
0
1
On/Off Selection
Pull-up MOS off
Pull-up MOS on
(refer to table 21)
MIS2
0
1
Figure 27 Miscellaneous Register (MIS)
CMOS Buffer
On/Off Selection
for Pin R0
/SO
2
PMOS active
PMOS off
41
Page 42
HD404358 Series
Prescalers
The MCU has a built-in prescaler labeled as prescaler S (PSS).
The prescalers operating conditions are listed in table 24, and the prescalers output supply is shown in
figure 28. The timers A–C input clocks except external events, the serial transmit clock except the external
clock are selected from the prescaler outputs, depending on corresponding mode registers.
Prescaler Operation
Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset,
prescaler S divides the system clock.
Table 24 Prescaler Operating Conditions
Prescaler Input Clock Reset Conditions Stop Conditions
Prescaler S System clock MCU reset MCU reset, stop mode
Timer A
System
clock
Clock
selector
Prescaler S
Figure 28 Prescaler Output Supply
Timer B
Timer C
Serial
Alarm output
circuit
42
Page 43
HD404358 Series
Timers
The MCU has four timer/counters (A to C).
• Timer A: Free-running timer
• Timer B: Multifunction timer
• Timer C: Multifunction timer
Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunction timers, whose functions are
listed in table 25. The operating modes are selected by software.
Table 25 Timer Functions
Functions Timer A Timer B Timer C
Clock source Prescaler S Available Available Available
External event — Available —
Timer functions Free-running Available Available Available
Event counter — Available —
Reload — Available Available
Watchdog — — Available
Input capture — Available —
Timer output PWM — — Available
Note: — implies not available.
43
Page 44
HD404358 Series
Timer A
Timer A Functions: Timer A has the following functions.
• Free-running timer
The block diagram of timer A is shown in figure 29.
Timer A interrupt
request flag
(IFTA)
Timer
counter A
(TCA)
Timer mode
register A
(TMA)
Overflow
Internal data bus
System
clock
ø
PER
Clock
Selector
24832128
ччччччч
Prescaler S (PSS)
512
1024
2048
÷
3
Figure 29 Timer A Block Diagram
Timer A Operations:
• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:
$008).
Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied
to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow
sets the timer A interrupt request flag (IFTA: $001, bit 2). Timer A continues to be incremented after
reset to $00, and therefore it generates regular interrupts every 256 clocks.
Registers for Timer A Operation: Timer A operating modes are set by the following registers.
• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode
and input clock source as shown in figure 30.
44
Page 45
Timer mode register A (TMA: $008)
HD404358 Series
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
W
TMA2
TMA1
Source
TMA1TMA2 TMA0
1
00
1
0
1
0
1
0
1
0
1
0
1
Prescaler
PSS
PSS
PSS
PSS
PSS
PSS
PSS
PSS
Figure 30 Timer Mode Register A (TMA)
1
0
W
Input Clock
Frequency
2048t
1024t
512t
128t
32t
cyc
8t
cyc
4t
cyc
2t
cyc
0
0
W
TMA0
cyc
cyc
cyc
cyc
45
Page 46
HD404358 Series
Timer B
Timer B Functions: Timer B has the following functions.
• Free-running/reload timer
• External event counter
• Input capture timer
The block diagram for each operation mode of timer B is shown in figures 31 and 32.
Interrupt request
Timer read
register B upper
(TRBU)
Timer read
register B lower
(TRBL)
flag of timer B
(IFTB)
EVNB
System
clock
Edge
detector
ø
PER
24832128
ччччччч
Prescaler S (PSS)
2
Selector
Clock
Free-running
timer control
signal
512
2048
Edge detection control signal
Timer counter B
(TCB)
Timer write
register B upper
(TWBU)
Timer write
register B lower
(TWBL)
3
Timer mode
register B1
(TMB1)
Timer mode
register B2
(TMB2)
Figure 31 Timer B Free-Running and Reload Operation Block Diagram
Overflow
Internal data bus
46
Page 47
HD404358 Series
EVNB
Edge
detector
Input capture
status flag
(ICSF)
Read
signal
controller
Selector
Error
Clock
Input capture
timer control
Input capture
error flag
signal
(ICEF)
Timer read
register B upper
(TRBU)
Timer counter B
3
Interrupt request
Timer read
register B lower
(TRBL)
(TCB)
flag of timer B
(IFTB)
Overflow
Internal data bus
System
clock
24832128
ø
PER
2
ччччччч
Prescaler S (PSS)
512
2048
Edge detection control signal
Figure 32 Timer B Input Capture Operation Block Diagram
Timer mode
register B1
(TMB1)
Timer mode
register B2
(TMB2)
47
Page 48
HD404358 Series
Timer B Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register B1 (TMB1: $009).
Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by
software and incremented by one at each clock input. If an input clock is applied to timer B after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is
initialized to its initial value set in timer write register B; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer B interrupt request flag (IFTB: $002, bit 0). IFTB is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• External event counter operation: Timer B is used as an external event counter by selecting the external
event input as an input clock source. In this case, pin D2/EVNB must be set to EVNB by port mode
register B (PMRB: $024).
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
external event detection edge by timer mode register 2 (TMB2: $026). When both rising and falling
edges detection is selected, the time between the falling edge and rising edge of input signals must be
2t
or longer.
cyc
Timer B is incremented by one at each detection edge selected by timer mode register 2 (TMB2: $026).
The other operation is basically the same as the free-running/reload timer operation.
• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges
input to pin EVNB.
Either falling or rising edge, or both falling and rising edges of input signals can be selected as the
trigger input edge by timer mode register 2 (TMB2: $026).
When a trigger edge is input to EVNB, the count of timer B is written to timer read register B (TRBL:
$00A, TRBU: $00B), and the timer B interrupt request flag (IFTB: $002, bit 0) and the input capture
status flag (ICSF: $021, bit 0) are set. Timer B is reset to $00, and then incremented again. While ICSF
is set, if a trigger input edge is applied to timer B, or if timer B generates an overflow, the input capture
error flag (ICEF: $021, bit 1) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0.
Registers for Timer B Operation: By using the following registers, timer B operation modes are selected
and the timer B count is read and written.
Timer mode register B1 (TMB1: $009)
Timer mode register B2 (TMB2: $026)
Timer write register B (TWBL: $00A, TWBU: $00B)
Timer read register B (TRBL: $00A, TRBU: $00B)
Port mode register B (PMRB: $024)
• Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 33. It is reset to $0
by MCU reset.
48
Page 49
HD404358 Series
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to timer
write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.
When selecting the input capture timer operation, select the internal clock as the input clock source.
Timer mode register B1 (TMB1: $009)
Bit
Initial value
Read/Write
Bit name
TMB13
0
1
3
0
W
TMB13
2
0
W
TMB12
Free-Running/Reload
Timer Selection
Free-running timer
Reload timer
Figure 33 Timer Mode Register B1 (TMB1)
1
0
W
TMB11
W
TMB10
TMB12 TMB10TMB11
0
1
0
0
Input Clock Period and Input
Clock Source
0
0
1
1
0
1
0
0
1
1
0
1
2048t
cyc
512t
cyc
128t
cyc
32t
cyc
8t
cyc
4t
cyc
2t
cyc
/EVNB (external event input)
D
2
49
Page 50
HD404358 Series
• Timer mode register B2 (TMB2: $026): Three-bit write-only register that selects the detection edge of
signals input to pin EVNB and input capture operation as shown in figure 34. It is reset to $0 by MCU
reset.
Timer mode register B2 (TMB2: $026)
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
W
TMB22
TMB22
0
1
1
0
W
TMB21
TMB21
0
1
Free-Running/Reload and Input Capture Selection
Free-running/reload
Input capture
0
0
W
TMB20
TMB20
0
1
0
1
EVNB Edge Detection Selection
No detection
Falling edge detection
Rising edge detection
Rising and falling edge detection
Figure 34 Timer Mode Register B2 (TMB2)
• Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of the lower digit
(TWBL) and the upper digit (TWBU). The lower digit is reset to $0 by MCU reset, but the upper digit
value is invalid (figures 35 and 36).
Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,
the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the
timer B value. Timer B is initialized to the value in timer write register B at the same time the upper
digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value
needs no change, writing only to the upper digit initializes timer B.
50
Timer write register B (lower digit) (TWBL: $00A)
Bit
Initial value
Read/Write
Bit name
3
0
W
TWBL3
2
0
W
TWBL2
1
0
W
TWBL1
0
0
W
TWBL0
Figure 35 Timer Write Register B Lower Digit (TWBL)
Page 51
Timer write register B (upper digit) (TWBU: $00B)
HD404358 Series
Bit
Initial value
Read/Write
Bit name
3
Undefined
W
TWBU3
2
Undefined
W
TWBU2
1
Undefined
W
TWBU1
0
Undefined
W
TWBU0
Figure 36 Timer Write Register B Upper Digit (TWBU)
• Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of the lower digit
(TRBL) and the upper digit (TRBU) that holds the count of the timer B upper digit (figures 37 and 38).
The upper digit (TRBU) must be read first. At this time, the count of the timer B upper digit is obtained,
and the count of the timer B lower digit is latched to the lower digit (TRBL). After this, by reading
TRBL, the count of timer B when TRBU is read can be obtained.
When the input capture timer operation is selected and if the count of timer B is read after a trigger is
input, either the lower or upper digit can be read first.
Timer read register B (lower digit) (TRBL: $00A)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRBL3
2
Undefined
R
TRBL2
1
Undefined
R
TRBL1
0
Undefined
R
TRBL0
Figure 37 Timer Read Register B Lower Digit (TRBL)
Timer read register B (upper digit) (TRBU: $00B)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRBU3
2
Undefined
R
TRBU2
1
Undefined
R
TRBU1
0
Undefined
R
TRBU0
Figure 38 Timer Read Register B Upper Digit (TRBU)
51
Page 52
HD404358 Series
• Port mode register B (PMRB: $024): Write-only register that selects D2/EVNB pin function as shown in
figure 39. It is reset to $0 by MCU reset.
Port mode register B (PMRB: $024)
Bit
Initial value
Read/Write
Bit name
PMRB2
PMRB3
Note: PMRB3 is reset to 0 only by RESET input. When STOPC is input in stop mode, PMRB3 is not
*
D2/EVNB Mode Selection
0
D
1
EVNB
D4/STOPC Mode Selection
0
D
4
1
STOPC
2
3
0
W
PMRB3
*
PMRB2
W
2
0
1
0
W
PMRB1
0
0
W
PMRB0
PMRB0
0
1
PMRB1
0
1
D0/INT0 Mode Selection
D
0
INT
0
D1/INT1 Mode Selection
D
1
INT
1
reset but retains its value.
Figure 39 Port Mode Register B (PMRB)
52
Page 53
Timer C
Timer C Functions: Timer C has the following functions.
• Free-running/reload timer
• Watchdog timer
• Timer output operation (PWM output)
The block diagram of timer C is shown in figure 40.
HD404358 Series
TOC
System
clock
Watchdog on
flag (WDON)
ø
PER
Clock
Selector
2
4832
÷÷÷
Prescaler S (PSS)
128
ччччч
Watchdog timer
controller
Timer output
control logic
Timer
output
control
signal
512
1024
2048
System reset signal
Timer read register C upper (TRCU)
Timer read
register C lower
Timer counter C
(TCC)
Timer write
register C upper
(TWCU)
Free-running
timer control
signal
3
Timer write
register C lower
Interrupt request
(TRCL)
(TWCL)
Timer mode
register C (TMC)
flag of timer C
(IFTC)
Overflow
Internal data bus
Figure 40 Timer C Block Diagram
Port mode
register A (PMRA)
53
Page 54
HD404358 Series
Timer C Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register C (TMC: $00D).
Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by
software and incremented by one at each clock input. If an input clock is applied to timer C after it has
reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is
initialized to its initial value set in timer write register C; if the free-running timer function is enabled,
the timer is initialized to $00 and then incremented again.
The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2). IFTC is reset by software or
MCU reset. Refer to figure 3 and table 1 for details.
• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program
routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of
control and an overflow is generated, the MCU is reset. The watchdog timer operation flowchart is
shown in figure 41. Program run can be controlled by initializing timer C by software before it reaches
$FF.
$FF + 1
Overflow
Timer C
count value
CPU
operation
$00
Normal
operation
Timer C
clear
Normal
operation
Timer C
clear
Program
runaway
Reset
Time
Normal
operation
Figure 41 Watchdog Timer Operation Flowchart
• Timer output operation: The PWM output modes can be selected for timer C by setting port mode
register A (PMRA: $004).
By selecting the timer output mode, pin R03/TOC is set to TOC. The output from TOC is reset low by
MCU reset.
PWM output: When PWM output mode is selected, timer C provides the variable-duty pulse output
function. The output waveform differs depending on the contents of timer mode register C (TMC:
$00D) and timer write register C (TWCL: $00E, TWCU: $00F). The output waveform is shown in
figure 42.
54
Page 55
TMC3 = 0
(free-running
timer)
TMC3 = 1
(reload timer)
×
T (N + 1)
T 256
T
×
T (256 – N)
HD404358 Series
×
Notes: T: Input clock period supplied to counter. (The clock source and system clock division
ratio are determined by timer mode register C.)
N: Value of timer write register C. (When N = 255 ($FF), PWM output is fixed low.)
Figure 42 PWM Output Waveform
Notes on Use
When using the timer output as PWM output, note the following point. From the update of the timer write
register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty
settings, as shown in table 26. The PWM output should therefore not be used until after the overflow
interrupt following the update of the timer write register. After the overflow, the PWM output will have the
set period and duty cycle.
In this case, the lower digit (TWCL) must be written to first, bit writing only to the lower digit does not
change the timer C value. Timer C is changed to the value in timer write register B at the same time the
upper digit (TWCU) is written to.
Table 26 PWM Output Following Update of Timer Write Register
PWM Output
Mode
Reload
Timer Write Register is Updated
during High PWM Output
Timer write
register
updated to
value N
Interrupt
request
Timer Write Register is Updated
during Low PWM Output
Timer write
register
updated to
value N
Interrupt
request
TT × (255 – N)T
T
TT × (255 – N)
55
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HD404358 Series
Registers for Timer C Operation: By using the following registers, timer C operation modes are selected
and the timer C count is read and written.
Timer mode register C (TMC: $00D)
Port mode register A (PMRA: $004)
Timer write register C (TWCL: $00E, TWCU: $00F)
Timer read register C (TRCL: $00E, TRCU: $00F)
• Timer mode register C (TMC: $00D): Four-bit write-only register that selects the free-running/reload
timer function, input clock source, and the prescaler division ratio as shown in figure 43. It is reset to $0
by MCU reset.
Writing to this register is valid from the second instruction execution cycle after the execution of the
previous timer mode register C write instruction. Setting timer C’s initialization by writing to timer
write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.
Timer mode register C (TMC: $00D)
Bit
Initial value
Read/Write
Bit name
TMC3
0
1
3
0
W
TMC3
Free-Running/Reload
Timer Selection
Free-running timer
Reload timer
2
0
W
TMC2
Figure 43 Timer Mode Register C (TMC)
1
0
W
TMC1
TMC2 TMC0TMC1 Input Clock Period
0
0
W
TMC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2048t
1024t
512t
128t
32t
cyc
8t
cyc
4t
cyc
2t
cyc
cyc
cyc
cyc
cyc
56
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HD404358 Series
• Port mode register A (PMRA: $004): Write-only register that selects R03/TOC pin function as shown in
figure 44. It is reset to $0 by MCU reset.
Port mode register A (PMRA: $004)
Bit
Initial value
Read/Write
Bit name
PMRA2
0
1
PMRA3
0
1
3
0
W
PMRA3
2
0
W
PMRA2
R03/TOC Mode Selection
R0
3
TOC
D3/BUZZ Mode Selection
D
3
BUZZ
1
0
W
PMRA1
0
0
W
PMRA0
PMRA0
0
1
PMRA1
0
1
R02/SO Mode Selection
R0
2
SO
R01/SI Mode Selection
R0
1
SI
Figure 44 Port Mode Register A (PMRA)
• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of the lower digit
(TWCL) and the upper digit (TWCU) as shown in figures 45 and 46. The operation of timer write
register C is basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).
Timer write register C (lower digit) (TWCL: $00E)
Bit
Initial value
Read/Write
Bit name
3
0
W
TWCL3
2
0
W
TWCL2
1
0
W
TWCL1
0
0
W
TWCL0
Figure 45 Timer Write Register C Lower Digit (TWCL)
Timer write register C (upper digit) (TWCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
Undefined
W
TWCU3
2
Undefined
W
TWCU2
1
Undefined
W
TWCU1
0
Undefined
W
TWCU0
Figure 46 Timer Write Register C Upper Digit (TWCU)
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HD404358 Series
• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of the lower digit
(TRCL) and the upper digit (TRCU) that holds the count of the timer C upper digit (figures 47 and 48).
The operation of timer read register C is basically the same as that of timer read register B (TRBL:
$00A, TRBU: $00B).
Timer read register C (lower digit) (TRCL: $00E)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRCL3
2
Undefined
R
TRCL2
1
Undefined
R
TRCL1
0
Undefined
R
TRCL0
Figure 47 Timer Read Register C Lower Digit (TRCL)
Timer read register C (upper digit) (TRCU: $00F)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R
TRCU3
2
Undefined
R
TRCU2
1
Undefined
R
TRCU1
0
Undefined
R
TRCU0
Figure 48 Timer Read Register C Upper Digit (TRCU)
58
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HD404358 Series
Alarm Output Function
The MCU has a built-in pulse output function called BUZZ. The pulse frequency can be selected from the
prescaler S’s outputs, and the output frequency depends on the state of port mode register C (PMRC: $025).
The duty cycle of the pulse output is fixed at 50%.
BUZZ
Alarm output
controller
Alarm output
control signal
Port mode
register A
(PMRA)
Selector
2
Port mode
Internal data bus
register C
(PMRC)
System
clock
ø
PER
256
512
÷
÷
Prescaler S (PSS)
1024
÷
2048
÷
Figure 49 Alarm Output Function Block Diagram
Port Mode Register C (PMRC: $025): Four-bit write-only register that selects the alarm frequencies as
shown in figure 50. It is reset to $0 by MCU reset.
Port mode register C (PMRC: $025)
Bit
Initial value
Read/Write
Bit name
3
0
W
PMRC3
2
0
W
PMRC2
1
Undefined
W
PMRC1
0
0
W
PMRC0
PMRC3
0
1
PMRC2 System Clock Divisor
÷2048
0
÷1024
1
÷512
0
÷256
1
Figure 50 Port Mode Register C (PMRC)
PMRC0
0
1
PMRC1
0
1
Serial Clock Division Ratio
Prescaler output divided by 2
Prescaler output divided by 4
Output Level Control in Idle States
Low level
High level
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HD404358 Series
Port Mode Register A (PMRA: $004): Four-bit write-only register that selects D3/BUZZ pin function as
shown in figure 44. It is reset to $0 by MCU reset.
Serial Interface
The serial interface serially transfers and receives 8-bit data, and includes the following features.
• Multiple transmit clock sources
External clock
Internal prescaler output clock
System clock
• Output level control in idle states
Five registers, an octal counter, and a selector are also configured for the serial interface as follows.
Serial data register (SRL: $006, SRU: $007)
Serial mode register (SMR: $005)
Port mode register A (PMRA: $004)
Port mode register C (PMRC: $025)
Miscellaneous register (MIS: $00C)
Octal counter (OC)
Selector
The block diagram of the serial interface is shown in figure 51.
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HD404358 Series
SO
SCK
SI
System
clock
Idle
controller
I/O
controller
ø
PER
Clock
1/2 1/2
Selector
2832
ччччч
Prescaler S (PSS)
128
512
2048
÷
Octal
counter (OC)
3
Selector
Serial interrupt
request flag
(IFS)
Serial data
register (SR)
Transfer
control
signal
Internal data bus
Serial mode
register
(SMR)
Port mode
register C
(PMRC)
Figure 51 Serial Interface Block Diagram
Serial Interface Operation
Selecting and Changing the Operating Mode: Table 27 lists the serial interface’s operating modes. To
select an operating mode, use one of these combinations of port mode register A (PMRA: $004) and the
serial mode register (SMR: $005) settings; to change the operating mode, always initialize the serial
interface internally by writing data to the serial mode register. Note that the serial interface is initialized by
writing data to the serial mode register. Refer to the following Serial Mode Register section for details.
Table 27 Serial Interface Operating Modes
SMR PMRA
Bit 3 Bit 1 Bit 0 Operating Mode
1 0 0 Continuous clock output mode
1 Transmit mode
1 0 Receive mode
1 Transmit/receive mode
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HD404358 Series
Pin Setting: The R00/SCK pin is controlled by writing data to the serial mode register (SMR: $005). The
R01/SI and R02/SO pins are controlled by writing data to port mode register A (PMRA: $004). Refer to the
following Registers for Serial Interface section for details.
Transmit Clock Source Setting: The transmit clock source is set by writing data to the serial mode
register (SMR: $005) and port mode register C (PMRC: $025). Refer to the following Registers for Serial
Interface section for details.
Data Setting: Transmit data is set by writing data to the serial data register (SRL: $006, SRU, $007).
Receive data is obtained by reading the contents of the serial data register. The serial data is shifted by the
transmit clock and is input from or output to an external system.
The output level of the SO pin is invalid until the first data is output after MCU reset, or until the output
level control in idle states is performed.
Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000
by this instruction, and it increments at the rising edge of the transmit clock. When the eighth transmit
clock signal is input or when serial transmission/receive is discontinued, the octal counter is reset to 000,
the serial interrupt request flag (IFS: $003, bit 2) is set, and the transfer stops.
When the prescaler output is selected as the transmit clock, the transmit clock frequency is selected as 4t
to 8192t
by setting bits 0 to 2 (SMR0– SMR2) of serial mode register (SMR: $005) and bit 0 (PMRC0)
cyc
of port mode register C (PMRC: $025) as listed in table 28.
Table 28 Serial Transmit Clock (Prescaler Output)
PMRC SMR
Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency
0000÷ 2048 4096t
1 ÷ 512 1024t
10÷ 128 256t
1 ÷ 32 64t
100÷ 8 16t
1 ÷ 24t
1000÷ 4096 8192t
1 ÷ 1024 2048t
10÷ 256 512t
1 ÷ 64 128t
100÷ 16 32t
1 ÷ 48t
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
cyc
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HD404358 Series
Operating States: The serial interface has the following operating states; transitions between them are
shown in figure 52.
STS wait state
Transmit clock wait state
Transfer state
Continuous clock output state (only in internal clock mode)
• STS wait state: The serial interface enters STS wait state by MCU reset (00, 10 in figure 59). In STS
wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is
then executed (01, 11), the serial interface enters transmit clock wait state.
• Transmit clock wait state: Transmit clock wait state is between the STS execution and the falling edge
of the first transmit clock. In transmit clock wait state, input of the transmit clock (02, 12) increments
the octal counter, shifts the serial data register, and enters the serial interface in transfer state. However,
note that if continuous clock output mode is selected in internal clock mode, the serial interface does not
enter transfer state but enters continuous clock output state (17).
The serial interface enters STS wait state by writing data to the serial mode register (SMR: $005) (04,
14) in transmit clock wait state.
• Transfer state: Transfer state is between the falling edge of the first clock and the rising edge of the
eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction sets the
octal counter to 000, and the serial interface enters another state. When the STS instruction is executed
(05, 15), transmit clock wait state is entered. When eight clocks are input, transmit clock wait state is
entered (03) in external clock mode, and STS wait state is entered (13) in internal clock mode. In
internal clock mode, the transmit clock stops after outputting eight clocks.
In transfer state, writing data to the serial mode register (SMR: $005) (06, 16) initializes the serial
interface, and STS wait state is entered.
If the state changes from transfer to another state, the serial interrupt request flag (IFS: $003, bit 2) is set
by the octal counter that is reset to 000.
• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered
only in internal clock mode. In this state, the serial interface does not transmit/receive data but only
outputs the transmit clock from the SCK pin.
When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock
wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.
If the serial mode register (SMR: $005) is written to in continuous clock output mode (18), STS wait
state is entered.
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HD404358 Series
External clock mode
SMR write
Transmit clock wait state
(Octal counter = 000)
Internal clock mode
Continuous clock output state
(PMRA 0, 1 = 0, 0)
Transmit clock 17
(Octal counter = 000,
transmit clock disabled)
04
01
03
8 transmit clocks
SMR write
18
SMR write
Transmit clock wait state
(Octal counter = 000)
STS wait state
STS instruction
Transmit clock
02
STS instruction (IFS 1)
(Octal counter = 000,
transmit clock disabled)
14
11
Transmit clock
12
STS instruction (IFS 1)
06
05
←
STS wait state
STS instruction
15
←
00
MCU reset
SMR write (IFS 1)
Transfer state
(Octal counter = 000)
8 transmit clocks
13
SMR write (IFS 1)
16
Transfer state
(Octal counter = 000)
←
MCU reset10
←
Note: Refer to the Operating States section for the corresponding encircled numbers.
Figure 52 Serial Interface State Transitions
Output Level Control in Idle States: In idle states, that is, STS wait state and transmit clock wait state,
the output level of the SO pin can be controlled by setting bit 1 (PMRC1) of port mode register C (PMRC:
$025) to 0 or 1. The output level control example is shown in figure 53. Note that the output level cannot be
controlled in transfer state.
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HD404358 Series
State
MCU reset
PMRA write
SMR write
PMRC write
SRL, SRU write
STS instruction
SCK pin (input)
SO pin
IFS
State
Transmit clock
wait state
STS wait state
Port selection
External clock selection
Output level control in
Undefined LSB MSB
STS wait state Transfer state
idle states
Data write for transmission
External clock mode
Transmit clock
wait state
Transfer state
Output level control in
Flag reset at transfer completion
Transmit clock
wait state
STS wait state
Dummy write for
state transition
idle states
STS wait state
MCU reset
PMRA write
SMR write
PMRC write
SRL, SRU write
STS instruction
SCK pin (output)
SO pin
IFS
Port selection
Internal clock selection
Output level control in
Undefined LSB MSB
idle states
Data write for transmission
Internal clock mode
Flag reset at transfer completion
Output level control in
Figure 53 Example of Serial Interface Operation Sequence
idle states
65
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HD404358 Series
Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a
spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit
clock error of this type can be detected as shown in figure 54.
State
Transmit clock
wait state
Transfer completion
Interrupts inhibited
Transmit clock error detection flowchart
←
(IFS 1)
←
IFS 0
SMR write
IFS = 1
Normal
termination
Transfer state Transfer state
Yes
No
Transmit clock wait state
Transmit clock
error processing
SCK pin (input)
SMR write
IFS
66
Noise
12345678
Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.
Flag set because octal
counter reaches 000
Transmit clock error detection procedure
Figure 54 Transmit Clock Error Detection
Flag reset at
transfer completion
Page 67
HD404358 Series
If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse
by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $003, bit 2) is set, and
transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is
entered. After the transfer completion processing is performed and IFS is reset, writing to the serial mode
register (SMR: $005) changes the state from transfer to STS wait. At this time IFS is set again, and
therefore the error can be detected.
Notes on Use:
• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit
clock wait state or in transfer state, the serial interface must be initialized by writing to the serial mode
register (SMR: $005) again.
• Serial interrupt request flag (IFS: $003, bit 2) set: If the state is changed from transfer to another by
writing to the serial mode register (SMR: $005) or executing the STS instruction during the first low
pulse of the transmit clock, the serial interrupt request flag is not set. To set the serial interrupt request
flag, serial mode register write or STS instruction execution must be programmed to be executed after
confirming that the SCK pin is at 1, that is, after executing the input instruction to port R0.
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
Serial Mode Register (SMR: $005)
Serial Data Register (SRL: $006, SRU: $007)
Port Mode Register A (PMRA: $004)
Port Mode Register C (PMRC: $025)
Miscellaneous Register (MIS: $00C)
Serial Mode Register (SMR: $005): This register has the following functions (figure 55).
• R00/SCK pin function selection
• Transmit clock selection
• Prescaler division ratio selection
• Serial interface initialization
Serial mode register (SMR: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.
A write signal input to serial mode register (SMR: $005) discontinues the input of the transmit clock to the
serial data register and octal counter, and the octal counter is reset to 000. Therefore, if a write is performed
during data transfer, the serial interrupt request flag (IFS: $003, bit 2) is set.
Written data is valid from the second instruction execution cycle after the write operation, so the STS
instruction must be executed at least two cycles after that.
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HD404358 Series
Serial mode register (SMR: $005)
Bit
Initial value
Read/Write
Bit name
SMR3
0
1
3
0
W
SMR3
R00/SCK
Mode Selection
R0
0
SCK
2
0
W
SMR2
SMR2 SMR0SMR1
1
0
W
SMR1
0
1
0
0
W
SMR0
0
1
0
1
0
1
0
1
0
1
0
1
Figure 55 Serial Mode Register (SMR)
SCK
Output
Output
Input
Clock Source
Prescaler
System clock
External clock
Prescaler
Division Ratio
Refer to
table 28
—
—
Port Mode Register C (PMRC: $025): This register has the following functions (figure 56).
• Prescaler division ratio selection
• Output level control in idle states
Port mode register C (PMRC: $025) is a 4-bit write-only register. It cannot be written during data transfer.
By setting bit 0 (PMRC0) of this register, the prescaler division ratio is selected. Bit 0 (PMRC0) can be
reset to 0 by MCU reset. By setting bit 1 (PMRC1), the output level of the SO pin is controlled in idle
states. The output level changes at the same time that PMRC1 is written to.
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Port mode register C (PMRC: $025)
HD404358 Series
Bit
Initial value
Read/Write
Bit name
3
0
W
PMRC3
Alarm output function.
Refer to figure 50.
2
0
W
PMRC2
1
Undefined
W
PMRC1
0
0
W
PMRC0
PMRC0
0
1
PMRC1
0
1
Serial Clock Division Ratio
Prescaler output divided by 2
Prescaler output divided by 4
Output Level Control in Idle States
Low level
High level
Figure 56 Port Mode Register C (PMRC)
Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 57 and
58).
• Transmission data write and shift
• Receive data shift and read
Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the
transmit clock; data is input, LSB first, through the SI pin at the rising edge of the transmit clock.
Input/output timing is shown in figure 59.
Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the
accuracy of the resultant data cannot be guaranteed.
Serial data register (lower digit) (SRL: $006)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R/W
SR3
2
Undefined
R/W
SR2
1
Undefined
R/W
SR1
0
Undefined
R/W
SR0
Figure 57 Serial Data Register (SRL)
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HD404358 Series
Serial data register (upper digit) (SRU: $007)
Bit
Initial value
Read/Write
Bit name
3
Undefined
R/W
SR7
2
Undefined
R/W
SR6
1
Undefined
R/W
SR5
0
Undefined
R/W
SR4
Figure 58 Serial Data Register (SRU)
Transmit clock
12345678
Serial output
data
Serial input data
latch timing
LSB MSB
Figure 59 Serial Interface Output Timing
Port Mode Register A (PMRA: $004): This register has the following functions (figure 60).
• R01/SI pin function selection
• R02/SO pin function selection
Port mode register A (PMRA: $004) is a 4-bit write-only register, and is reset to $0 by MCU reset.
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Port mode register A (PMRA: $004)
HD404358 Series
Bit
Initial value
Read/Write
Bit name
PMRA2
0
1
PMRA3
0
1
3
0
W
PMRA3
R03/TOC Mode Selection
R0
3
TOC
D3/BUZZ Mode Selection
D
3
BUZZ
2
0
W
PMRA2
1
0
W
PMRA1
0
0
W
PMRA0
PMRA0
0
1
PMRA1
0
1
R02/SO Mode Selection
R0
2
SO
R01/SI Mode Selection
R0
1
SI
Figure 60 Port Mode Register A (PMRA)
Miscellaneous Register (MIS: $00C): This register has the following functions (figure 61).
• R02/SO pin PMOS control
Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.
Miscellaneous register (MIS: $00C)
Bit
Initial value
Read/Write
Bit name
MIS3
0
1
3
0
W
MIS3
Pull-Up MOS
On/Off Selection
Pull-up MOS off
Pull-up MOS on
(refer to table 21)
MIS2
2
0
W
Not used
MIS2
Figure 61 Miscellaneous Register (MIS)
1
—
—
0
1
0
—
—
Not used
CMOS Buffer
On/Off Selection
for Pin R0
PMOS active
PMOS off
/SO
2
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HD404358 Series
A/D Converter
The MCU has a built-in A/D converter that uses a sequential comparison method with a resistor ladder. It
can measure eight analog inputs with 8-bit resolution. The block diagram of the A/D converter is shown in
figure 62.
4
A/D interrupt
request flag
(IFAD)
A/D mode
register 1
(AMR1)
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
AV
AV
CC
SS
Selector
D/A
3
Encoder
+
Comp
–
A/D
controller
Control signal
for conversion
time
A/D start flag
(ADSF)
Operating mode signal
(1 in stop mode)
Figure 62 A/D Converter Block Diagram
A/D mode
register 2
(AMR2)
A/D data
register
(ADRU, L)
Internal data bus
A/D channel
register (ACR)
IAD off flag
(IAOF)
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HD404358 Series
Registers for A/D Converter Operation
A/D Mode Register 1 (AMR1: $019): Four-bit write-only register which selects digital or analog ports, as
shown in figure 63.
A/D mode register 1 (AMR1: $019)
Bit
Initial value
Read/Write
Bit name
AMR12
0
1
AMR13
0
1
3
0
W
AMR13
2
0
W
AMR12
R32/AN2 Mode Selection
R3
2
AN
2
R33/AN3 Mode Selection
R3
3
AN
3
1
0
W
AMR11
0
0
W
AMR10
AMR10
0
1
AMR11
0
1
R30/AN0 Mode Selection
R3
0
AN
0
R31/AN1 Mode Selection
R3
1
AN
1
Figure 63 A/D Mode Register 1 (AMR1)
A/D Mode register 2 (AMR2: $01A): Two-bit write-only register which is used to set the A/D conversion
period and to select digital or analog ports. Bit 0 of the A/D mode register selects the A/D conversion
period, and bit 1 selects port R4 as pins AN4–AN7 in 4-pin units (figure 64).
A/D mode register 2 (AMR2: $01A)
Bit
Initial value
Read/Write
Bit name
AMR21
0
1
3
—
—
Not used
R4/AN4–AN7 Pin Selection
R4
AN4–AN
Not used
7
—
—
2
1
0
W
AMR21
0
0
W
AMR20
AMR20
0
1
Figure 64 A/D Mode Register 2 (AMR2)
Conversion Time
34t
cyc
67t
cyc
73
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HD404358 Series
A/D Channel Register (ACR: $016): Three-bit write-only register which indicates analog input pin
information, as shown in figure 65.
A/D channel register (ACR: $016)
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
W
ACR2
1
1
0
W
ACR1
ACR1ACR2 ACR0
0
00
1
0
1
1
0
0
1
1
0
1
0
0
W
ACR0
Analog Input Selection
AN
0
AN
1
AN
2
AN
3
AN
4
AN
5
AN
6
AN
7
Figure 65 A/D Channel Register (ACR)
A/D Start Flag (ADSF: $02C, Bit 2): One-bit flag that initiates A/D conversion when set to 1. At the
completion of A/D conversion, the converted data is stored in the A/D data register and the A/D start flag is
cleared. Refer to figure 66.
74
A/D start flag (ADSF: $020, bit 2)
Bit
Initial value
Read/Write
Bit name
3
—
—
Not used
2
0
R/W
ADSF
A/D Start Flag (ADSF)
0
1
A/D conversion completed
A/D conversion started
Figure 66 A/D Start Flag (ADSF)
1
0
W
WDON
0
—
—
Not used
WDON
Refer to the description of timers
Page 75
HD404358 Series
IAD Off Flag (IAOF: $021, Bit 2): By setting the IAD off flag to 1, the current flowing through the
resistance ladder can be cut off even while operating in standby or active mode, as shown in figure 67.
IAD off flag (IAOF: $021, bit 2)
Bit
Initial value
Read/Write
Bit name
IAD Off Flag (IAOF)
0
1
Refer to the description of operating
modes
IAD current flows
I
AD
3
0
R/W
RAME
current is cut off
RAME
R/W
IAOF
2
0
1
0
R/W
ICEF
0
0
R/W
ICSF
ICSF
Refer to the description of timers
ICEF
Refer to the description of timers
Figure 67 IAD Off Flag (IAOF)
A/D Data Register (ADRL: $017, ADRU: $018): Eight-bit read-only register consisting of a 4-bit lower
digit and 4-bit upper digit. This register is not cleared by reset. After the completion of A/D conversion, the
resultant eight-bit data is held in this register until the start of the next conversion (figures 68, 69, and 70).
ADRU: $018 ADRL: $017
3210
MSB LSB
3210
Figure 68 A/D Data Registers (ADRU, ADRL)
Bit 0Bit 7
75
Page 76
HD404358 Series
A/D data register (lower digit) (ADRL: $017)
Bit
Initial value
Read/Write
Bit name
3
0
R
ADRL3
2
0
R
ADRL2
1
0
R
ADRL1
0
0
R
ADRL0
Figure 69 A/D Data Register Lower Digit (ADRL)
A/D data register (upper digit) (ADRU: $018)
Bit
Initial value
Read/Write
Bit name
3
1
R
ADRU3
2
0
R
ADRU2
ADRU1
1
0
R
0
0
R
ADRU0
Figure 70 A/D Data Register Upper Digit (ADRU)
Notes on Usage
• Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
• Do not write to the A/D start flag during A/D conversion
• Data in the A/D data register during A/D conversion is undefined
• Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D
converter does not operate in stop mode. In addition, to save power while in these modes, all current
flowing through the converter’s resistance ladder is cut off.
• If the power supply for the A/D converter is to be different from VCC, connect a 0.1-µF bypass capacitor
between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly
connected to the VCC pin.)
• The contents of the A/D data register are not guaranteed during A/D conversion. To ensure that the A/D
converter oparates stably, do not execute port output instructions during A/D convention.
• The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected
as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to VCC. When using a
shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by
MIS3 and PDR is set to 1, a pin selected by A/D mode register 1 or 2 (AMR1 or AMR2) as an analog
pin will remain pulled up (figure 71).
76
Page 77
HD404358 Series
V
CC
V
CC
Input control signal
HLT
MIS3
AMR
A/D mode register value
DCR
PDR
CPU input
A/D input
ACR
A/D channel register value
Figure 71 R Port/Analog Multiplexed Pin Circuit
77
Page 78
HD404358 Series
Pin Description in PROM Mode
The HD4074359 is a PROM version of a ZTAT microcomputer. In PROM mode, the MCU stops
operating, thus allowing the user to program the on-chip PROM.
Pin Number MCU Mode PROM Mode
DP-42S FP-44A Pin I/O Pin I/O
139RA
240R0
341R0
442R0
543R0
1
/SCK I/O V
0
/SI I/O V
1
/SO I/O O
2
/TOC I/O O
3
6 1 TEST I V
72RESET I RESET I
8 3 OSC
9 4 OSC
1
2
10 5 GND GND
11 6 AV
12 7 R30/AN
13 8 R31/AN
14 9 R32/AN
15 10 R33/AN
16 11 R40/AN
17 12 R41/AN
18 13 R42/AN
19 14 R43/AN
20 15 AV
21 16 V
22 17 D0/INT
23 18 D1/INT
SS
0
1
2
3
4
5
6
7
CC
CC
0
1
24 19 D2/EVNB I/O A
25 20 D3/BUZZ I/O A
26 21 D4/STOPC I/O
27 23 D
28 24 D
29 25 D
30 26 D
5
6
7
8
IO
IV
0
CC
CC
1
2
PP
CC
O
GND
I/O O
I/O O
I/O O
I/O O
I/O O
I/O M
I/O M
0
1
2
3
4
0
1
I/O
V
CC
V
CC
I/O O
I/O O
I/O A
I/O A
I/O A
I/O V
3
4
1
2
3
4
9
CC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I/O
I/O
I
I
I
I
I
78
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HD404358 Series
Pin Number MCU Mode PROM Mode
DP-42S FP-44A Pin I/O Pin I/O
31 27 R8
32 28 R8
33 29 R8
34 30 R8
35 31 R1
36 32 R1
37 33 R1
38 34 R1
39 35 R2
40 36 R2
41 37 R2
42 38 R2
0
1
2
3
0
1
2
3
0
1
2
3
Notes: 1. I/O: Input/output pin; I: Input pin; O: Output pin
2. O
to O4 consist of two pins each. The each pair together before using them.
0
I/O CE I
I/O OE I
I/O A
I/O A
I/O A
I/O A
I/O A
I/O A
I/O A
I/O A
I/O A
I/O A
13
14
5
6
7
8
0
10
11
12
I
I
I
I
I
I
I
I
I
I
79
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HD404358 Series
Programming the Built-In PROM
The MCU’s built-in PROM is programmed in PROM mode. PROM mode is set by pulling RESET, M0,
and M1 low, as shown in figure 72. In PROM mode, the MCU does not operate, but it can be programmed
in the same way as any other commercial 27256-type EPROM using a standard PROM programmer and a
100-to-28-pin socket adapter. Recommended PROM programmers and socket adapters are listed in table
29.
Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion
circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into
five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if,
for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,
a 32-kbyte address space ($0000–$7FFF) must be specified.
Table 29 Recommended PROM Programmers and Socket Adapters
PROM Programmer Socket Adapter
Manufacture Model Name Package Manufacture Model Name
DATA I/O corp 121 B DP-42S Hitachi HS4359ESS01H
FP-44A HS4359ESH01H
AVAL corp PKW-1000 DP-42S Hitachi HS4359ESS01H
FP-44A HS4359ESH01H
CE, OE
RESET
HD407A4359
PROM mode pins
A
14–A0
O4–O
V
GND
V
Control signals
Address bus
O
7
O
6
O
5
0
M
0
M
1
CC
PP
O4–O
0
Socket adapter PROM programmer
O7–O
Data bus
0
V
CC
GND
V
PP
Figure 72 PROM Mode Connections
80
Page 81
HD404358 Series
Warnings
1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address
$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in
unused addresses to $FF.
Note that the plastic-package version cannot be erased and reprogrammed.
2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1
positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure
that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the
programmer.
3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTAT devices
require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.
Programming and Verification
The built-in PROM of the MCU can be programmed at high speed without risk of voltage stress or damage
to data reliability.
Programming and verification modes are selected as listed in table 30.
For details of PROM programming, refer to the following Notes on PROM Programming section.
Table 30 PROM Mode Selection
Pin
Mode CE OE V
Programming Low High V
Verification High Low V
Programming inhibited High High V
PP
PP
PP
PP
O0–O
Data input
Data output
High impedance
4
81
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HD404358 Series
Addressing Modes
RAM Addressing Modes
The MCU has three RAM addressing modes, as shown in figure 73 and described below.
Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits in total) are used
as a RAM address.
Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains
the opcode, and the contents of the second word (10 bits) are used as a RAM address.
Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from
$040 to $04F, are accessed with the LAMR and XMRA instructions.
W register X register Y register
1st word of Instruction
Opcode
W
W
1
0X3X2X1X0Y3Y2Y1
RAM address
AP
AP8AP7AP6AP5AP4AP
9
Register Direct Addressing
d
d
9
8
RAM address
AP
AP AP AP AP AP AP AP AP
9
87654321
Direct Addressing
000100
2nd word of Instruction
d
d
d
7
6
5
d
4
Instruction
Opcode
3AP2AP1
d
d
3
2
m
m
3
2m1m0
d
1
AP
Y
AP
d
0
0
0
0
82
RAM address
AP
AP8AP7AP AP5AP46AP3AP2AP
9
Memory Register Addressing
Figure 73 RAM Addressing Modes
AP
0
1
Page 83
HD404358 Series
ROM Addressing Modes and the P Instruction
The MCU has four ROM addressing modes, as shown in figure 74 and described below.
Direct Addressing Mode: A program can branch to any address in the ROM memory space by executing
the JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits
(PC13–PC0) with 14-bit immediate data.
Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program
can branch to any address in the current page by executing the BR instruction. This instruction replaces the
eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction
is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next
physical page, as shown in figure 76. This means that the execution of the BR instruction on a page
boundary will make the program branch to the next page.
Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.
Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–
$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data
are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight highorder bits (PC13–PC6).
Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit
immediate data, the accumulator, and the B register by executing the TBR instruction.
P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction
as shown in figure 75. If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator
and the B register. If bit 9 is 1, eight bits of ROM data are written to the R1 and R2 port output registers. If
both bits 8 and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and
R2 port output registers at the same time.
The P instruction has no effect on the program counter
83
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HD404358 Series
[JMPL]
[BRL]
[CALL]
1st word of instruction
Opcode
Program counter
Program counter
2nd word of instruction
p
2
3
0
1
PC9PC8PC7PC6PC5PC4PC3PC2PC1PC
PCPCPCPC
10111213
8d7d6d5d4d3d2d1d0
0
d9d
p
p
p
Direct Addressing
Instruction
[BR]
Opcode
PC
PCPCPC
111213
PC
10 7
90
b
7b6b5b4b3b2b1b0
PC6PC5PC4PC3PC2PC1PCPC8PC
Current Page Addressing
Instruction
[CAL]
Opcode
a5a
4a3a2a1a0
00000000
[TBR]
Program counter
Opcode
Program counter
PCPC PC
PCPC
PC
98PC76PC54PC3
10111213
Zero Page Addressing
Instruction
p
p
3
2p1
p
0
B
3
00
PC
PC9PC8PC7PC6PC5PC4PC3PC2PC1PC
PCPCPC
10111213
Table Data Addressing
Figure 74 ROM Addressing Modes
PC PC
B register
B1B
B
2
PC
PC1PC
2
Accumulator
0A3A2A1A0
0
0
84
Page 85
Instruction
HD404358 Series
[P]
Opcode
Referenced ROM address
ROM data
Accumulator, B register
ROM data
Output registers R1, R2
RO
RO
p
p
3
2p1
p
0
00
RA
RA9RA8RA7RA6RA5RA4RA3RA2RA1RA
RARARA
10111213
Address Designation
RO
9
8RO7RO6RO5RO4RO3RO2RO1
BBBBAA
3210 3210
RO
9
8RO7RO6RO5RO4RO3RO2RO1
R23R22R21R20R13R12R11R1
Pattern Output
Figure 75 P Instruction
B
3
B register
B1B
B
2
A
Accumulator
0A3A2A1A0
RO
0
A
If RO = 1
8
RO
0
If RO = 1
0
9
0
85
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HD404358 Series
BR AAA
AAA NOP
256 (n – 1) + 255
256n
BR AAA
BR BBB
BBB NOP
256n + 254
256n + 255
256 (n + 1)
Figure 76 Branching when the Branch Destination is on a Page Boundary
86
Page 87
HD404358 Series
Absolute Maximum Ratings
Item Symbol Value Unit Notes
Supply voltage V
Programming voltage V
Pin voltage V
Total permissible input current ∑I
Total permissible output current –∑I
Maximum input current I
Maximum output current –I
Operating temperature T
Storage temperature T
CC
PP
T
O
O
O
O
opr
stg
Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation
must be under the conditions stated in the electrical characteristics tables. If these conditions are
exceeded, the LSI may malfunction or its reliability may be affected.
1. Applies to pin TEST (V
) of HD407A4359.
PP
2. Applies to all standard voltage pins.
3. Applies to intermediate-voltage pins.
4. The total permissible input current is the total of input currents simultaneously flowing in from all
the I/O pins to GND.
5. The total permissible output current is the total of output currents simultaneously flowing out from
V
to all I/O pins.
CC
6. The maximum input current is the maximum current flowing from each I/O pin to GND.
7. Applies to ports D
to D8, R0, R1, R3, R4, and R8.
0
8. Applies to port R2.
9. The maximum output current is the maximum current flowing from V
–0.3 to +7.0 V
–0.3 to +14.0 V 1
–0.3 to VCC + 0.3 V 2
–0.3 to +15.0 V 3
105 mA 4
50 mA 5
4 mA 6, 7
30 mA 6, 8
4 mA 7, 9
–20 to +75 °C
–55 to +125 °C
to each I/O pin.
CC
87
Page 88
HD404358 Series
Electrical Characteristics
DC Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C; HD404354/
HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20
to +75°C, unless otherwise specified)
Item Symbol Pins Min Typ Max Unit Test Condition Notes
Input high
voltage
V
IH
RESET, SCK,
, INT1,
INT
0
0.8V
STOPC, EVNB
SI 0.7 V
Input low
voltage
OSC
1
V
IL
RESET, SCK,
, INT1,
INT
0
VCC – 0.5 — VCC + 0.3 V
–0.3 — 0.2V
STOPC, EVNB
SI –0.3 — 0.3V
Output high
OSC
1
V
OH
SCK, SO, TOC VCC – 0.5 — — V –IOH = 0.5 mA
–0.3 — 0.5 V
voltage
Output low
V
OL
SCK, SO, TOC — — 0.4 V IOL = 0.4 mA
voltage
I/O leakage
current
|IIL| RESET, SCK, SI,
SO,TOC,OSC
, INT1,
INT
0
,
1
——1 µAV
STOPC, EVNB
Current
I
CC
V
CC
— — 5.0 mA VCC = 5 V,
dissipation in
active mode
Current
I
SBY
V
CC
— — 2.0 mA VCC = 5 V,
dissipation in
standby mode
Current
I
STOP
V
CC
——10µAVCC = 5 V 4
dissipation in
stop mode
Stop mode
V
STOP
V
CC
2——V
retaining
voltage
Notes: 1. Excludes current flowing through pull-up MOS and output buffers.
2. I
is the source current when no I/O current is flowing while the MCU is in reset state.
CC
Test conditions: MCU: Reset
Pins: RESET, TEST at GND
—VCC + 0.3 V
CC
—VCC + 0.3 V
CC
V
CC
V
CC
= 0 V to VCC1
in
2
= 4 MHz
f
OSC
3
= 4 MHz
f
OSC
88
Page 89
HD404358 Series
3. I
is the source current when no I/O current is flowing while the MCU timer is operating.
SBY
Test conditions: MCU: I/O reset
Standby mode
Pins: RESET at V
TEST at GND
D
0–D8
4. This is the source current when no I/O current is flowing.
Test conditions: Pins: RESET at V
TEST at GND
D
0–D8
I/O Characteristics for Standard Pins (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to
+75°C; HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V,
GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Input high
voltage
V
IH
D0–D8,
R0, R1, R3,
R4, R8, RA
Input low
voltage
V
IL
D0–D8,
R0, R1, R3,
R4, R8, RA
Output high
voltage
V
OH
D0–D8,
R0, R1, R3,
R4, R8
Output low
voltage
V
OL
D0–D8,
R0, R1, R3,
R4, R8
Input leakage
current
|IIL|D
0–D8
,
R0, R1, R3,
R4, R8, RA
Pull-up MOS
current
–I
PU
D0–D8,
R0, R1, R3,
R4, R8
Note: 1. Output buffer current is excluded.
0.7V
CC
1
–0.3 — 0.3V
1
– 0.5 — — V –IOH = 0.5 mA
V
CC
— — 0.4 V I
——1µAVin = 0 V to V
1
30 150 300 µAV
CC
, R0–R4, R8, RA1 at V
CC
, R0–R4, R8, RA1 at V
—VCC + 0.3 V
CC
CC
CC
V
= 1.6 mA
OL
1
CC
= 5 V,
CC
= 0 V
V
in
89
Page 90
HD404358 Series
I/O Characteristics for Intermediate-Voltage Pins (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta =
–20 to +75°C;HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD 40A4358: VCC = 2.7 to
6.0 V, GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Input high
V
IH
voltage
Input low
V
IL
voltage
Output high
V
OH
voltage
Output low
V
OL
voltage
I/O leakage
|IIL| R2 ——20µAV
current
Note: 1. Excludes output buffer current.
R2 0.7VCC—12V
R2 –0.3 — 0.3VCCV
R2 11.5 — — V 500 kΩ at 12 V
R2 — — 0.4 V IOL = 0.4 mA
— — 2.0 V IOL = 15 mA,
= 4.5 to 5.5 V
V
CC
= 0 V to 12 V 1
in
90
Page 91
HD404358 Series
A/D Converter Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to +75°C;
HD404354/HD404356/HD404358 /HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0
V, Ta = –20 to +75°C, unless otherwise specified)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Analog supply
AV
CC
AV
CC
voltage
Analog input
AV
in
AN0–AN7AV
voltage
Current flowing
between AV
and AV
SS
Analog input
I
AD
CC
CA
in
AN0–AN7——30pF
capacitance
Resolution 8 8 8 Bit
Number of input
channels
Absolute
accuracy
Conversion
time
Input
AN0–AN71——MΩ
impedance
Note: 1. Connect this to VCC if the A/D converter is not used.
VCC – 0.3 V
SS
CC
—AVCCV
— — 200 µAV
VCC + 0.3 V 1
= AVCC = 5.0
CC
V
0 — 8 Channel
——±2.0 LSB
34 — 67 t
cyc
91
Page 92
HD404358 Series
Standard f
= 5.0 MHz Version AC Characteristics (HD404354/HD404356/HD404358: VCC = 2.7 to
OSC
6.0 V, GND = 0 V, Ta = –20 to +75°C)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Clock oscillation
f
OSC
frequency
Instruction cycle time t
Oscillation stabilization
cyc
t
RC
time (ceramic oscillator)
Oscillation stabilization
t
RC
time (crystal oscillator)
External clock high
t
CPH
width
External clock low width t
External clock rise time t
External clock fall time t
INT
, INT1, EVNB high
0
CPL
CPr
CPf
t
IH
widths
INT
, INT1, EVNB low
0
t
IL
widths
RESET low width t
STOPC low width t
RESET rise time t
STOPC rise time t
Input capacitance C
RSTL
STPL
RSTr
STPr
in
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After V
reaches 2.7 V at power-on.
CC
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 77.
3. Refer to figure 78.
4. Refer to figure 79.
5. Refer to figure 80.
OSC1, OSC20.4 4 5.0 MHz 1/4 system clock
division ratio
0.8 1 10 µs
OSC1, OSC2— — 7.5 ms 1
OSC1, OSC2— — 40 ms 1
OSC
OSC
OSC
OSC
INT
1
1
1
1
, INT1,
0
80——ns 2
80——ns 2
— — 20 ns 2
— — 20 ns 2
2 ——t
cyc
EVNB
INT
, INT1,
0
2 ——t
cyc
EVNB
RESET 2 ——t
STOPC 1 ——t
cyc
RC
RESET — — 20 ms 4
STOPC — — 20 ms 5
All input pins
— — 15 pF f = 1 MHz, Vin = 0 V
except and R2
R2 — — 30 pF f = 1 MHz, Vin = 0 V
.
RC
3
3
4
5
92
Page 93
HD404358 Series
High-Speed f
= 8.5 MHz Version AC Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0
OSC
V, Ta = –20 to +75°C; HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V, GND = 0 V, Ta = –20
to +75°C)
Item Symbol Pins Min Typ Max Unit Test Condition Note
Clock oscillation
frequency
Instruction cycle time t
Oscillation
stabilization time
(ceramic oscillator)
Oscillation
stabilization time
(crystal oscillator)
External clock high
width
External clock low
width
External clock rise
time
External clock fall time t
INT
, INT1, EVNB high
0
widths
INT
, INT1, EVNB low
0
widths
RESET low width t
STOPC low width t
RESET rise time t
STOPC rise time t
Input capacitance C
f
OSC
cyc
t
RC
t
RC
t
CPH
t
CPL
t
CPr
CPf
t
IH
t
IL
RSTL
STPL
RSTr
STPr
OSC1, OSC
OSC1, OSC
OSC1, OSC
OSC
OSC
OSC
OSC
INT
, INT1, EVNB 2 — — t
0
INT
, INT1, EVNB 2 — — t
0
2
2
2
1
1
1
1
RESET 2——t
STOPC 1——t
RESET — — 20 ms 4
STOPC — — 20 ms 5
in
All input pins
except TEST and
R2
TEST — — 15 pF f = 1 MHz, Vin = 0 V 6
R2 — — 30 pF f = 1 MHz, Vin = 0 V
0.4 4 5.0 MHz 1/4 system clock
division ratio
0.4 4 8.5 MHz 1/4 system clock
division ratio,
V
= 4.5 to 5.5 V
CC
0.8 1 10 µs
0.47 1 10 µsVCC = 4.5 to 5.5 V
— — 7.5 ms 1
— — 40 ms 1
80 — — ns 2
47 — — ns VCC = 4.5 to 5.5 V 2
80 — — ns 2
47 — — ns VCC = 4.5 to 5.5 V 2
— — 20 ns 2
— — 15 ns VCC = 4.5 to 5.5 V 2
— — 20 ns 2
— — 15 ns VCC = 4.5 to 5.5 V 2
cyc
cyc
cyc
RC
— — 15 pF f = 1 MHz, Vin = 0 V
— — 180 pF f = 1 MHz, Vin = 0 V 7
3
3
4
5
93
Page 94
HD404358 Series
Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the
following situations:
a. After V
b. After RESET input goes low when stop mode is cancelled.
c. After STOPC input goes low when stop mode is cancelled.
To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET
or STOPC must be input for at least a duration of t
When using a crystal or ceramic oscillator, consult with the manufacturer to determine what
stabilization time is required, since it will depend on the circuit constants and stray capacitance.
2. Refer to figure 77.
3. Refer to figure 78.
4. Refer to figure 79.
5. Refer to figure 80.
6. Applies to the HD40A4354, HD40A4356, HD40A4358.
7. Applies to the HD407A4359.
reaches 2.7 V at power-on.
CC
.
RC
94
Page 95
HD404358 Series
Serial Interface Timing Characteristics (HD407A4359: VCC = 2.7 to 5.5 V, GND = 0 V, Ta = –20 to
+75°C; HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358: VCC = 2.7 to 6.0 V,
GND = 0 V, Ta = –20 to +75°C, unless otherwise specified)
During Transmit Clock Output
Item Symbol Pins Min Typ Max Unit Test Condition Note
Transmit clock cycle
time
Transmit clock high
width
Transmit clock low
width
Transmit clock rise time t
Transmit clock fall time t
Serial output data delay
time
Serial input data setup
time
Serial input data hold
time
t
Scyc
t
SCKH
t
SCKL
SCKr
SCKf
t
DSO
t
SSI
t
HSI
SCK 1——t
SCK 0.4 — — t
SCK 0.4 — — t
SCK — — 80 ns Load shown in figure 82 1
SCK — — 80 ns Load shown in figure 82 1
SO — — 300 ns Load shown in figure 82 1
SI 100 — — ns 1
SI 200 — — ns 1
Load shown in figure 82 1
cyc
Load shown in figure 82 1
Scyc
Load shown in figure 82 1
Scyc
During Transmit Clock Input
Item Symbol Pins Min Typ Max Unit Test Condition Note
Transmit clock cycle
t
Scyc
time
Transmit clock high
t
SCKH
width
Transmit clock low
t
SCKL
width
Transmit clock rise time t
Transmit clock fall time t
Serial output data delay
t
SCKr
SCKf
DSO
time
Serial input data setup
t
SSI
time
Serial input data hold
t
HSI
time
Note: 1. Refer to figure 81.
SCK 1——t
SCK 0.4 — — t
SCK 0.4 — — t
cyc
Scyc
Scyc
SCK ——80ns 1
SCK ——80ns 1
SO — — 300 ns Load shown in figure 82 1
SI 100 — — ns 1
SI 200 — — ns 1
1
1
1
95
Page 96
HD404358 Series
OSC
1
VCC – 0.5 V
0.5 V
t
CPH
1/f
CP
t
CPL
t
CPr
Figure 77 External Clock Timing
INT
, INT1, EVNB
0
0.8V
0.2V
CC
CC
t
IH
Figure 78 Interrupt Timing
RESET
0.8V
CC
t
0.2V
CC
RSTL
Figure 79 RESET Timing
t
CPf
t
IL
t
RSTr
96
STOPC
0.8V
CC
0.2V
CC
Figure 80 STOPC Timing
t
STPL
t
STPr
Page 97
t
Scyc
HD404358 Series
V – 0.5 V (0.8V )*
SCK
CC
0.4 V (0.2V )*
SO
SI
Note: * V
– 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and
CC
t
SCKf
CC
t
CC
DSO
t
SCKL
V – 0.5 V
CC
0.4 V
t
SSI
0.7V
0.3V
CC
CC
t
t
SCKr
t
SCKH
HSI
0.8VCC and 0.2VCC are the threshold voltages for transmit clock input.
Figure 81 Serial Interface Timing
V
CC
RL = 2.6 kΩ
Test
point
C =
30 pF
R =
12 kΩ
Hitachi
1S2074
or equivalent
Figure 82 Timing Load Circuit
97
Page 98
HD404358 Series
Notes on ROM Out
Please pay attention to the following items regarding ROM out.
On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404354,
HD40A4354, HD404356 and HD40A4356 as an 8-kword version (HD404358, HD40A4358). The 8-kword
and 16-kword data sizes are required to change ROM data to mask manu facturing data since the program
used is for an 8-k or 16-kword version.
This limitation applies when using an EPROM or a data base.
$0000
$000F
$0010
$003F
$0040
$0FFF
$1000
$1FFF
ROM 4-kword version:
HD404354, HD40A4354
Vector address
Zero-page subroutine
(64 words)
Pattern & program
(4,096 words)
Not used
Fill this area with 1s
ROM 6-kword version:
HD404356, HD40A4356
$0000
Vector address
$000F
$0010
Zero-page subroutine
(64 words)
$003F
$0040
Pattern & program
(6,144 words)
$17FF
$1800
Not used
$1FFF
98
Page 99
HD404358 Series
HD404354/HD404356/HD404358/HD40A4354/HD40A4356/HD40A4358
Please check off the appropriate applications and enter the necessary information.
1. ROM size
5 MHz operation
8.5 MHz operation
5 MHz operation
8.5 MHz operation
5 MHz operation
8.5 MHz operation
2. ROM code media
Please specify the first type below (the upper bits and lower bits are mixed together), when using
the EPROM on-package microcomputer type (including ZTAT™ version).
EPROM:
EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are
3. System Oscillator (OSC1, OSC2)
Ceramic oscillator
Crystal oscillator
External clock
The upper bits and lower bits are mixed together. The upper five bits and lower five bits
are programmed to the same EPROM in alternating order (i.e., LULULU...).
programmed to different EPROMS.
HD404354
HD40A4354
HD404356
HD40A4356
HD404358
HD40A4358
f = MHz
f = MHz
f = MHz
4-kword
6-kword
8-kword
Date of order
Customer
Department
Name
ROM code name
LSI number
4. Stop mode
Used
Not used
5. Package
DP-42S
FP-44A
99
Page 100
HD404358 Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Semiconductor & Integrated Circuits.
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Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
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Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
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Fax: <886> (2) 2718-8180
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
100
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