HITACHI HD404358 User Manual
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Description
The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program
productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input
capture timer, and two low-power dissipation modes.
HD404358 Series
Rev. 6.0
Sept. 1998
The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the
HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the
HD407A4359 with 16-kword PROM.
The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum
instruction cycle time: 0.47 µs)
The HD407A4359 is a PROM version (ZTATmicrocomputer). A program can be written to the PROM
by a PROM writer, which can dramatically shorten system development periods and smooth the process
from debugging to mass production. (The ZTAT version is 27256-compatible.)
ZTAT: Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.
Features
• 34 I/O pins
One input-only pin
33 input/output pins: 4 pins are intermediate-voltage NMOS open drain with high-current pins (15
mA, max.)
• On-chip A/D converter (8-bit × 8-channel)
Low power voltage 2.7 V to 6.0 V
• Three timers
One event counter input
One timer output
One input capture timer
• Eight-bit clock-synchronous serial interface (1 channel)
• Alarm output
HD404358 Series
• Built-in oscillators
Ceramic oscillator or crystal
External clock drive is also possible
• Seven interrupt sources
Two by external sources
Three by timers
One by A/D converter
One by serial interface
• Two low-power dissipation modes
Standby mode
Stop mode
• Instruction cycle time
0.47 µs (f
HD40A4354, HD40A4356, HD40A4358,
HD407A4359
0.8 µs (f
HD404354, HD404356, HD404358
= 8.5 MHz, 1/4 division ratio):
OSC
= 5 MHz, 1/4 division ratio):
OSC
Ordering Information
Instruction Cycle
Type
Mask ROM Standard versions HD404354 HD404354S 4,096 384 DP-42S
ZTAT (f
Time Product Name Model Name
(f
= 5 MHz) HD404354H FP-44A
OSC
HD404356 HD404356S 6,144 DP-42S
HD404356H FP-44A
HD404358 HD404358S 8,192 DP-42S
HD404358H FP-44A
High speed versions HD40A4354 HD40A4354S 4,096 384 DP-42S
(f
= 8.5 MHz) HD40A4354H FP-44A
OSC
HD40A4356 HD40A4356S 6,144 DP-42S
HD40A4356H FP-44A
HD40A4358 HD40A4358S 8,192 DP-42S
HD40A4358H FP-44A
= 8.5 MHz) HD407A4359 HD407A4359S 16,384 512 DP-42S
OSC
HD407A4359H FP-44A
ROM
(Words)
RAM
(Digit) Package
2
Pin Arrangement
RA
R00/SCK
R0
/SI
1
R0
/SO
2
R0
/TOC
3
TEST
RESET
OSC
OSC
GND
AV
SS
R30/AN
R31/AN
R32/AN
R33/AN
R40/AN
R41/AN
R42/AN
R43/AN
AV
CC
V
CC
HD404358 Series
1
1
2
3
4
5
6
7
1
8
2
9
10
11
12
0
13
1
14
2
15
3
16
4
17
5
18
6
19
7
DP-42S
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
R2
3
R2
2
R2
1
R2
0
R1
3
R1
2
R1
1
R1
0
R8
3
R8
2
R8
1
R8
0
D
8
D
7
D
6
D
5
D4/STOPC
D
/BUZZ
3
D
/EVNB
2
D
/INT
1
1
D
/INT
0
0
TEST
RESET
OSC
OSC
GND
AV
R30/AN
R31/AN
R32/AN
R33/AN
R40/AN
SS
/TOC
NC
R03R02R01R00RA1R23R22R21R20R1
3
/SCK
/SI
/SO
4443424140393837363534
1
2
3
1
4
2
5
6
7
0
8
1
9
2
10
3
11
4
FP-44A
33
32
31
30
29
28
27
26
25
24
23
R1
R1
R1
R8
R8
R8
R8
D
D
D
D
2
1
0
3
2
1
0
8
7
6
5
1213141516171819202122
0
/INT
0
D
1
/INT
1
D
/BUZZ
/EVNB
3
2
D
D
NC
/STOPC
4
D
5
/AN
1
R4
6
/AN
2
R4
7
/AN
3
R4
CCVCC
AV
3
HD404358 Series
Pin Description
Pin Number
Item Symbol DP-42S FP-44A I/O Function
Power
supply
Test TEST 6 1 I Cannot be used in user applications. Connect this pin
Reset RESET 7 2 I Resets the MCU
Oscillator OSC
Port D0–D
Interrupt INT0, INT122, 23 17, 18 I Input pins for external interrupts
Stop clear STOPC 26 21 I Input pin for transition from stop mode to active mode
Serial
Interface
Timer TOC 5 43 O Timer output pin
Alarm BUZZ 25 20 O Square waveform output pin
A/D
converter
V
CC
21 16 Applies power voltage
GND 10 5 Connected to ground
to GND.
8 3 I Input/output pin for the internal oscillator. Connect
1
these pins to the ceramic oscillator or crystal oscillator,
OSC
2
8
RA
1
R00–R13,
–R43,
R3
0
–R8
R8
0
or OSC
94O
22–30 17–21,
23–26
I/O Input/output pins addressed individually by bits; D0–D
are all standard-voltage I/O pins.
1 39 I One-bit standard-voltage input port pin
3
2–5,
12–19,
31–38
40–43,
7–14
27–34
I/O Four-bit input/output pins consisting of standard-voltage
pins
to an external oscillator circuit.
1
R20–R2339–42 35–38 I/O Four-bit input/output pins consisting of intermediate
voltage pins
SCK 2 40 I/O Serial interface clock input/output pin
SI 3 41 I Serial interface receive data input pin
SO 4 42 O Serial interface transmit data output pin
EVNB 24 19 I Event count input pin
AV
AV
CC
SS
20 15 Power supply for the A/D converter. Connect this pin
as close as possible to the V
voltage as V
. If the power supply voltage to be used
CC
for the A/D converter is not equal to V
µF bypass capacitor between the AV
(However, this is not necessary when the AV
directly connected to the V
pin and at the same
CC
, connect a 0.1-
CC
and AVSS pins.
CC
pin.)
CC
pin is
CC
11 6 Ground for the A/D converter. Connect this pin as
close as possible to GND at the same voltage as GND.
AN0–AN712–19 7–14 I Analog input pins for the A/D converter
8
4
Block Diagram
INT
0
INT
1
EVNB
TOC
Interrupt
control
Timer A
Timer B
Timer C
STOPC
TEST
RESET
System control
RAM
(384 4 bits)
×
(512 4 bits)
×
1
OSC
2
VCCOSC
W
(2 bits)
X
(4 bits)
SPX
(4 bits)
Y
(4 bits)
SPY
(4 bits)
GND
HD404358 Series
D
0
D
1
D
2
D
3
D
4
D portR0 port
D
5
D
6
D
7
D
8
R0
0
R0
1
R0
2
R0
3
R1
0
R1
1
R1
R1 port
R1
2
3
SI
SO
SCK
AV
SS
AN
0
•
•
•
AN
7
AV
CC
BUZZ
Data bus
Intermediate
voltage pin
Directional
signal line
•
•
•
Serial
interface
A/D
converter
Buzzer
Internal address bus
Internal data bus
ST
(1 bit)CA(1 bit)
(4 bits)
(4 bits)
(10 bits)
Instruction
decoder
ROM
×
(4,096 10 bits) (6,144 10 bits)
×
(16,384 10 bits)(8,192 10 bits)
SP
A
B
ALU
(14 bits)
×
×
PC
Internal data bus
R2 port
R3 port
R4 port
R8 port
RA port
R2
R2
R2
R2
R3
R3
R3
R3
R4
R4
R4
R4
R8
R8
R8
R8
RA
0
1
2
3
0
1
2
3
0
1
2
3
0
1
2
3
1
5
HD404358 Series
Memory Map
ROM Memory Map
The ROM memory map is shown in figure 1 and described below.
Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses
of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the
vector address.
Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a
subroutine in this area in response to the CAL instruction.
Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.
Program Area ($0000-$0FFF (HD404354, HD40A4354), $0000–$17FF (HD404356, HD40A4356),
$0000–$1FFF (HD404358, HD40A4358), $0000–$3FFF (HD407A4359)): The entire ROM area can be
used for program coding.
$0000
$000F
$0010
$003F
$0040
$0FFF
$1000
$17FF
$1800
$1FFF
$2000
$3FFF
Vector address
(16 words)
Zero-page subroutine
(64 words)
Pattern (4,096 words)
Program (4,096 words)
For HD404354, HD40A4354
Program
(6,144 words)
For HD404356, HD40A4356
Program
(8,192 words)
For HD404358, HD40A4358
Program
(16,384 words)
HD407A4359
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
JMPL instruction
(jump to RESET, STOPC routine)
JMPL instruction
(jump to INT routine)
JMPL instruction
(jump to INT routine)
JMPL instruction
(jump to timer A routine)
JMPL instruction
(jump to timer B routine)
JMPL instruction
(jump to timer C routine)
JMPL instruction
(jump to A/D converter routine)
JMPL instruction
(jump to serial routine)
0
1
Note: Since the ROM address areas between $0000–$0FFF overlap, the user can
determine how these areas are to be used.
Figure 1 ROM Memory Map
6
HD404358 Series
RAM Memory Map
The HD404354, HD40A4354, HD404356, HD40A4356, HD404358 and HD40A4358 MCUs contain 384digit × 4-bit RAM areas. The HD407A4359 MCU contain 512-digit × 4-bit RAM areas. Both of these
RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control
bits area, special function register area, and register flag area are mapped onto the same RAM memory
space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described
below.
RAM-Mapped Register Area ($000–$03F):
• Interrupt Control Bits Area ($000–$003)
This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit
manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the
instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.
• Special Function Register Area ($004–$01F, $024–$03F)
This area is used as mode registers and data registers for external interrupts, serial interface,
timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in
figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and
read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.
• Register Flag Area ($020–$023)
This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).
These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD,
and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on
using the instructions are shown in figure 4.
Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be
accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.
Data Area ($050–$17F for HD404354/HD40A4354/HD404356/HD40A4356/HD404358/HD40A4358,
$050–$1FF for HD407A4359)
Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and
carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a
16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save
conditions are shown in figure 6.
The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can
only be restored by the RTNI instruction. Any unused space in this area is used for data storage.
7
HD404358 Series
RAM Memory Map
$000 $000
$040
$050
$180
$200
$3C0
$3FF
RAM-mapped registers
Memory registers (MR)
HD404354, HD40A4354,
HD404356, HD40A4356,
HD404358, HD40A4358
Data (304 digits)
HD407A4359
Data (432 digits)
Not used
Stack (64 digits)
$003
$004
$005
$006
$007
$008
$009
$00A
$00B
$00C
$00D
$00E
$00F
$016
$017
$018
$019
$01A
Interrupt control bits area
Port mode register A (PMRA)
Serial mode register (SMR)
Serial data register lower (SRL)
Serial data register upper (SRU)
Timer mode register A (TMA)
Timer mode register B1 (TMB1)
Timer B (TRBL/TWBL)
(TRBU/TWBU)
Miscellaneous register (MIS)
Timer mode register C (TMC)
Timer C (TRCL/TWCL)
(TRCU/TWCU)
A/D channel register (ACR)
A/D data register lower (ADRL)
A/D data register upper (ADRU)
A/D mode register 1 (AMR1)
A/D mode register 2 (AMR2)
Not used
Not used
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
R
R
W
W
Initial values
after reset
0000
0000
Undefined
Undefined
-000
0000
*2
/0000
Undefined
00--
0000
*2
/0000
Undefined
-000
0000
1000
0000
--00
*1
1. Two registers are mapped
Notes:
on the same area ($00A,
$00B, $00E, $00F).
2. Undefined.
R: Read only
W: Write only
R/W: Read/write
Timer read register B lower (TRBL)
$00A
Timer read register B upper (TRBU)
$00B
Timer read register C lower (TRCL)
$00E
Timer read register C upper (TRCU)
$00F
$020
$023
$024
$025
$026
Timer mode register B2 (TMB2)
$02C
$02D
$02E
$02F
$030
$031
$032
$033
$034
$038
$03F
Register flag area
Port mode register B (PMRB)
Port mode register C (PMRC)
Not used
Port D0–D
Port D4–D
Port D DCR
Port R0 DCR (DCR0)
Port R1 DCR (DCR1)
Port R2 DCR (DCR2)
Port R3 DCR (DCR3)
Port R4 DCR (DCR4)
Port R8 DCR (DCR8)
R
R
R
R
DCR
3
DCR
7
8
Not used
Not used
Not used
Timer write register B lower (TWBL)
Timer write register B upper (TWBU)
Timer write register C lower (TWCL)
Timer write register C upper (TWCU)
Figure 2 RAM Memory Map
(DCD0)
(DCD1)
(DCD2)
0000
W
00-0
W
-000
W
W
0000
0000
W
---0
W
0000
W
0000
W
W
0000
0000
W
0000
W
0000W
W
W
W
W
8
0
1
Bit 3 Bit 2 Bit 1 Bit 0
IM0
INT
(IM of
(IM of timer A)
0
IMTA
)
IF0
INT
(IF of
(IF of timer A)
0
IFTA
)
RSP
(Reset SP bit)
IM1
(IM of INT
1
)
IE
(Interrupt
enable flag)
IF1
(IF of INT1)
HD404358 Series
$000
$001
2
3
32
33
34
35
IMTC
(IM of timer C)
IMS
(IM of serial)
Bit 3 Bit 2 Bit 1 Bit 0
Not used Not used
RAME
(RAM enable
flag)
IFTC
(IF of timer C)
IFS
(IF of serial)
Interrupt control bits area
ADSF
(A/D start flag)
IAOF
(I
off flag)
AD
Not used
Register flag area
IMTB
(IM of timer B)
IMAD
(IM of A/D)
WDON
(Watchdog
on flag)
ICEF
(Input capture
error flag)
IFTB
(IF of timer B)
IFAD
(IF of A/D)
ICSF
(Input capture
status flag)
$002
$003
$020
$021
$022
$023
Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas
SEM/SEMD REM/REMD TM/TMD
IE
IM
IAOF
IF
ICSF
ICEF
RAME
RSP
WDON
ADSF
Not used
Allowed Allowed Allowed
Not executed Allowed Allowed
Not executed Allowed Inhibited
Allowed Not executed Inhibited
Allowed Inhibited Allowed
Not executed Not executed Inhibited
IF:
Interrupt request flag
Interrupt mask
IM:
Interrupt enable flag
IE:
Stack pointer
SP:
Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.
The REM or REMD instuction must not be executed for ADSF during A/D conversion.
If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,
the value in ST becomes invalid.
Figure 4 Usage Limitations of RAM Bit Manipulation Instructions
9
HD404358 Series
$000
$003
PMRA $004
SMR $005
SRL $006
SRU $007
TMA $008
TMB1 $009
TRBL/TWBL $00A
TRBU/TWBU $00B
MIS $00C
TMC $00D
TRCL/TWCL $00E
TRCU/TWCU $00F
ACR $016
ADRL $017
ADRU $018
AMR1$019
AMR2 $01A
Bit 3 Bit 2 Bit 1
Interrupt control bits area
/BUZZ R03/TOC R02/SO
D
3
R0
0
/SCK
Serial transmit clock speed selection
R01/SI
Serial data register (lower digit)
Serial data register (upper digit)
Not used
*
1
Clock source selection (timer A)
Clock source selection (timer B)
Timer B register (lower digit)
Timer B register (upper digit)
*
2
*
1
SO PMOS control
Clock source selection (timer C)
Not used
Timer C register (lower digit)
Timer C register (upper digit)
Not used
Not used
Analog channel selection
A/D data register (lower digit)
A/D data register (upper digit)
/AN R32/AN
R3
3
3
Not used
R31/AN
2
R4/AN
4
–AN
1
7
Not used
Bit 0
R30/AN
*
3
0
$020
$023
PMRB $024
PMRC $025
TMB2 $026
DCD0 $02C
DCD1 $02D
DCD2 $02E
DCR0 $030
DCR1 $031
DCR2 $032
DCR3 $033
DCR4 $034
DCR8 $038
$03F
Register flag area
D
/STOPC
4
D2/EVNB*6D1/INT
Buzzer output
Not used
Not used
DCD
3
Port D
2
Port D6 DCD
Port D
Port D7 DCD
DCD
Not used
Not used
Port R0
DCR
Port R02 DCR
3
DCR
3
DCR
3
DCR
3
Port R12 DCR
DCR
Port R2
2
Port R3
DCR
2
Port R4
DCR
2
Port R13 DCR
Port R2
Port R3
Port R4
Not used
Port R83 DCR Port R82 DCR
Not used
Figure 5 Special Function Register Area
D0/INT
1
*4
0
*5
EVNB detection edge selection
Port D
DCD
Port D0 DCD
1
Port D5 DCD
Port D4 DCD
Port D8 DCD
Port R01 DCR
Port R11 DCR
Port R21 DCR
Port R3
Port R41 DCR
Port R8
Port R00 DCR
Port R10 DCR
Port R20 DCR
DCR
Port R3
1
DCR
0
Port R40 DCR
DCR Port R80 DCR
1
Notes:
1.
Auto-reload on/off
2.
Pull-up MOS control
3.
A/D conversion time
4.
SO output level control in idle states
5.
Serial clock source selection
6.
Input capture selection
10
HD404358 Series
Memory registers
MR(0)
64
MR(1)
65
MR(2)
66
MR(3)
67
MR(4)
68
MR(5)
69
MR(6)
70
MR(7)
71
MR(8)
72
MR(9)
73
MR(10)
74
MR(11)
75
MR(12)
76
MR(13)
77
MR(14)
78
MR(15)
79
PC –PC :
13
ST: Status flag
$040
$041
$042
$043
$044
$045
$046
$047
$048
$049
$04A
$04B
$04C
$04D
$04E
$04F
Program counter
0
CA: Carry flag
Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position
Stack area
960 $3C0
Level 16
Level 15
Level 14
Level 13
Level 12
Level 11
Level 10
Level 9
Level 8
Level 7
Level 6
Level 5
Level 4
Level 3
Level 2
1023
Level 1
$3FF
1020
1021
1022
1023
Bit 3 Bit 2 Bit 1 Bit 0
ST
PC
CA
PC
PC
PC
10
PC
PC
3
PC
13
PC
9
PC
6
PC
2
PC
12
PC
8
PC
5
PC
1
$3FC
11
$3FD
7
$3FE
4
$3FF
0
11
HD404358 Series
Functional Description
Registers and Flags
The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described
below.
30
Accumulator
B register
W register
X register
Y register
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
(A)
30
(B)
0
1
(W)
30
(X)
30
(Y)
30
SPX register
SPY register
Carry
Status
Program counter
Initial value: 0,
no R/W
Stack pointer
Initial value: $3FF, no R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: Undefined, R/W
Initial value: 1, no R/W
13
95
1111
(SPX)
30
(SPY)
0
(CA)
0
(ST)
0
(PC)
0
(SP)
Figure 7 Registers and Flags
Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit
(ALU) and transfer data between memory, I/O, and other registers.
W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for
indirect RAM addressing. The Y register is also used for D-port addressing.
12
HD404358 Series
SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.
Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is
affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an
interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,
not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,
CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or
bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,
regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack
during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.
Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being
executed.
Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is
initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and
incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a
stack can be used up to 16 levels.
The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD
instruction.
Reset
The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is
cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation,
RESET must be high for at least two instruction cycles.
Initial values after MCU reset are listed in table 1.
Interrupts
The MCU has 7 interrupt sources: two external signals (INT0 and INT1), three timer/counters (timers A, B,
and C), serial interface, and A/D converter.
An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt
source, and an interrupt enable flag (IE) controls the entire interrupt process.
Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the
interrupt control bits which can be accessed by RAM bit manipulation instructions.
The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)
and the IF to 0 and the interrupt mask (IM) to 1.
A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector
addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in
table 3.
13
HD404358 Series
An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the
interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to
that interrupt source.
The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in
figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The
IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack
during the second and third cycles, and the program jumps to the vector address to execute the instruction
in the third cycle.
Program the JMPL instruction at each vector address, to branch the program to the start address of the
interrupt program, and reset the IF by a software instruction within the interrupt program.
14
HD404358 Series
Table 1 Initial Values After MCU Reset
Item Abbr. Initial Value Contents
Program counter (PC) $0000 Indicates program execution point
Status flag (ST) 1 Enables conditional branching
Stack pointer (SP) $3FF Stack level 0
Interrupt
flags/mask
I/O Port data register (PDR) All bits 1 Enables output at level 1
Timer/
counters,
serial
interface
Interrupt enable flag (IE) 0 Inhibits all interrupts
Interrupt request flag (IF) 0 Indicates there is no interrupt
Interrupt mask (IM) 1 Prevents (masks) interrupt requests
Data control register (DCD0 –
Port mode register A (PMRA) 0000 Refer to description of port mode
Port mode register B bits
2–0
Port mode register C (PMRC) 00 - 0 Refer to description of port mode
Timer mode register A (TMA) - 000 Refer to description of timer mode
Timer mode register B1 (TMB1) 0000 Refer to description of timer mode
Timer mode register B2 (TMB2) - 000 Refer to description of timer mode
Timer mode register C (TMC) 0000 Refer to description of timer mode
Serial mode register (SMR) 0000 Refer to description of serial mode
Prescaler S (PSS) $000 —
Timer counter A (TCA) $00 —
Timer counter B (TCB) $00 —
Timer counter C (TCC) $00 —
Timer write register B (TWBU,
Timer write register C (TWCU,
Octal counter 000 —
DCD1)
(DCD2) - - - 0
(DCR0 –
DCR4,
DCR8)
(PMRB2 –
PMRB0)
TWBL)
TWCL)
All bits 0 Turns output buffer off (to high
All bits 0
000 Refer to description of port mode
$X0 —
$X0 —
from start address of ROM area
request
impedance)
register A
register B
register C
register A
register B1
register B2
register C
register
15
HD404358 Series
Initial
Item Abbr.
A/D A/D mode register 1 (AMR1) 0000 Refer to description of A/D mode register
A/D mode register 2 (AMR2) - - 00
A/D channel register (ACR) - 000 Refer to description of A/D channel register
A/D data register (ADRL) 0000 Refer to description of A/D data register
(ADRU) 1000
Bit registers Watchdog timer on flag (WDON) 0 Refer to description of timer C
A/D start flag (ADSF) 0 Refer to description of A/D converter
IAD off flag (IAOF) 0 Refer to the description of A/D converter
Input capture status flag (ICSF) 0 Refer to description of timer B
Input capture error flag (ICEF) 0 Refer to description of timer B
Others Miscellaneous register (MIS) 00 - - Refer to description of operati n g modes, I/O,
Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.
2. X indicates invalid value. – indicates that the bit does not exist.
Value Contents
and serial interface
Status After Cancellation of
Item Abbr.
Carry flag (CA) Pre-stop-mode values are not
Accumulator (A)
B register (B)
W register (W)
X/SPX register (X/SPX)
Y/SPY register (Y/SPY)
Serial data register (SRL, SRU)
RAM Pre-stop-mode values are
RAM enable flag (RAME) 1 0
Port mode register
B bit 3
(PMRB3) Pre-stop-mode values are
Stop Mode by STOPC Input
guaranteed; values must be
initialized by program
retained
retained
Status After all Other Types of
Reset
Pre-MCU-reset values are not
guaranteed; values must be
initialized by program
0
16
Table 2 Vector Addresses and Interrupt Priorities
Reset/Interrupt Priority Vector Address
RESET, STOPC* — $0000
INT
0
INT
1
Timer A 3 $0006
Timer B 4 $0008
Timer C 5 $000A
A/D 6 $000C
Serial 7 $000E
Note: * The STOPC interrupt request is valid only in stop mode.
1 $0002
2 $0004
HD404358 Series
17
HD404358 Series
INT0 interrupt
interrupt
INT
1
Timer A interrupt
Timer B interrupt
Timer C interrupt
A/D interrupt
Serial interrupt
$ 000,0
IE
$ 000,2
IFO
$ 000,3
IMO
$ 001,0
IF1
$ 001,1
IM1
$ 001,2
IFTA
$ 001,3
IMTA
$ 002,0
IFTB
$ 002,1
IMTB
$ 002,2
IFTC
$ 002,3
IMTC
$ 003,0
IFAD
$ 003,1
IMAD
$ 003,2
IFS
$ 003,3
IMS
Sequence control
• Push PC/CA/ST
• Reset IE
• Jump to vector
address
Vector
address
Priority control logic
18
Note: $m,n is RAM address $m, bit number n.
Figure 8 Interrupt Control Circuit
HD404358 Series
Table 3 Interrupt Processing and Activation Conditions
Interrupt Source
INT
0
INT
1
IE 1111111
IF0 · IM0 1000000
IF1 · IM1 * 100000
IFTA · IMTA **10000
IFTB · IMTB ***1000
IFTC · IMTC ****100
IFAD · IMAD **** *10
IFS · IMS ******1
Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.
Instruction cycles
123456
Timer A Timer B Timer C A/D Serial
Instruction
execution*
IE reset
Stacking
Vector address
generation
Execution of JMPL
instruction at vector address
Interrupt
acceptance
Note: * The stack is accessed and the IE reset after the instruction
is executed, even if it is a two-cycle instruction.
Figure 9 Interrupt Processing Sequence
Execution of
instruction at
start address
of interrupt
routine
19
HD404358 Series
Power on
RESET = 0?
Yes
Reset MCU
No
Interrupt
request?
No
Execute instruction
←
PC (PC) + 1
←
PC $0002
←
PC $0004
Yes
No
Accept interrupt
Yes
Yes
IE = 1?
Yes
←
IE 0
←
Stack (PC)
←
Stack (CA)
←
Stack (ST)
INT
0
interrupt?
No
INT
1
interrupt?
←
PC $0006
←
PC $0008
←
PC $000A
←
PC $000C
←
PC $000E
Yes
Yes
Yes
Yes
(serial interrupt)
Figure 10 Interrupt Processing Flowchart
No
Timer-A
interrupt?
No
Timer-B
interrupt?
No
Timer-C
interrupt?
No
A/D
interrupt?
No
20
HD404358 Series
Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt
processing and set by the RTNI instruction, as listed in table 4.
Table 4 Interrupt Enable Flag (IE: $000, Bit 0)
IE Interrupt Enabled/Disabled
0 Disabled
1 Enabled
External Interrupts (INT0, INT1): Two external interrupt signals.
External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising
edge of signals input to INT0 and INT1, as listed in table 5.
Table 5 External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)
IF0, IF1 Interrupt Request
0No
1 Yes
External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests
caused by the corresponding external interrupt request flags, as listed in table 6.
Table 6 External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)
IM0, IM1 Interrupt Request
0 Enabled
1 Disabled (masked)
Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in
table 7.
Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)
IFTA Interrupt Request
0No
1 Yes
Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer
A interrupt request flag, as listed in table 8.
21
HD404358 Series
Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)
IMTA Interrupt Request
0 Enabled
1 Disabled (masked)
Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in
table 9.
Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)
IFTB Interrupt Request
0No
1 Yes
Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer
B interrupt request flag, as listed in table 10.
Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1)
IMTB Interrupt Request
0 Enabled
1 Disabled (masked)
Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in
table 11.
Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)
IFTC Interrupt Request
0No
1 Yes
Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer
C interrupt request flag, as listed in table 12.
Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)
IMTC Interrupt Request
0 Enabled
1 Disabled (masked)
22
HD404358 Series
Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data
transfer is suspended, as listed in table 13.
Table 13 Serial Interrupt Request Flag (IFS: $003, Bit 2)
IFS Interrupt Request
0No
1 Yes
Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial
interrupt request flag, as listed in table 14.
Table 14 Serial Interrupt Mask (IMS: $003, Bit 3)
Mask IMS Interrupt Request
0 Enabled
1 Disabled (masked)
A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in
table 15.
Table 15 A/D Interrupt Request Flag (IFAD: $003, Bit 0)
IFAD Interrupt Request
0No
1 Yes
A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D
interrupt request flag, as listed in table 16.
Table 16 A/D Interrupt Mask (IMAD: $003, Bit 1)
IMAD Interrupt Request
0 Enabled
1 Disabled (masked)
23
HD404358 Series
Operating Modes
The MCU has three operating modes as shown in table 17. The operations in each mode are listed in tables
18 and 19. Transitions between operating modes are shown in figure 11.
Table 17 Operating Modes and Clock Status
Mode Name
Active Standby Stop
Activation method RESET cancellation,
interrupt request, STOPC
cancellation in stop mode
Status System
oscillator
Cancellation
method
Note: OP implies in operation
OP OP Stopped
RESET input, STOP/ SBY
instruction
Table 18 Operations in Low-Power Dissipation Modes
SBY instruction STOP instruction
RESET input, interrupt
request
RESET input, STOPC
input in stop mode
Function Stop Mode Standby Mode
CPU Reset Retained
RAM Retained Retained
Timer A Reset OP
Timer B Reset OP
Timer C Reset OP
Serial Reset OP
A/D Reset OP
I/O Reset Retained
Note: OP implies in operation
Table 19 I/O Status in Low-Power Dissipation Modes
Output Input
Standby Mode Stop Mode Active Mode
RA
1
R0–D8, R0–R4,
R8,
— — Input enabled
Retained or output of
peripheral functions
High impedance Input enabled
24
Reset by
RESET input or
by watchdog timer
RAME = 0 RAME = 1
RESET 1 RESET 2
HD404358 Series
Active
Standby mode Stop mode
mode
STOPC
SBY
Oscillate
f
:
OSC
:
Stop
ø
CPU
:
ø
f
cyc
PER
:
Main oscillation frequency
f
OSC
f
ø
ø
cyc
CPU
PER
:
/4
f
OSC
:
System clock
:
Clock for other peripheral
instruction
Interrupt
f
OSC
ø
ø
CPU
PER
:
Oscillate
:
f
cyc
f
:
cyc
STOP
instruction
f
OSC
ø
ø
CPU
PER
:
:
:
Stop
Stop
Stop
functions
Figure 11 MCU Status Transitions
Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC
and OSC2.
1
Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction
execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the
D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and
serial interface continue to operate. The power dissipation in this mode is lower than in active mode
because the CPU stops.
The MCU enters standby mode when the SBY instruction is executed in active mode.
Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input,
the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next
instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is
0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation
in standby mode is shown in figure 12.
25
HD404358 Series
Stop
Oscillator: Stop
Peripheral clocks: Stop
All other clocks: Stop
No
RESET = 0?
No
STOPC = 0?
Yes
RAME = 1
Yes
Oscillator: Active
Peripheral clocks: Active
All other clocks: Stop
Yes
No
IF0 • IMO = 1?
RESET = 0?
RAME = 0
Standby
Yes
IF1 • IM1 = 1?
No
Yes
No
IFTA • IMTA
= 1?
Yes
No
IFTB •
IMTB = 1?
Yes
No
IFTC •
IMTC = 1?
Yes
No
IFAD •
IMAD = 1?
Yes
No
IMS = 1?
IFS •
No
Yes
Restart
processor clocks
Reset MCU
Restart
processor clocks
Execute
next instruction
No
Execute
next instruction
IF = 1,
IM = 0, and
IE = 1?
Yes
Accept interrupt
Figure 12 MCU Operation Flowchart
Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power
dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops.
Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC
must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When
the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained,
but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register,
carry flag, and serial data register cannot be guaranteed.
26
HD404358 Series
Stop mode
Oscillator
Internal
clock
RESET
or STOPC
t
STOP instruction execution
≥ tRC (stabilization period)
res
Figure 13 Timing of Stop Mode Cancellation
Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC
as well as by R E SE T . In either case, the MCU starts instruction execution from the starting address
(address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs
between cancellation by STOPC and by RESET. When stop mode is cancelled by R E SE T , RAME = 0;
when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop
mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop
mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is
used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the
beginning of the program.
t
res
MCU Operation Sequence: The MCU operates in the sequence shown in figure 15. It is reset by an
asynchronous RESET input, regardless of its status.
The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt
flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is
cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY
instruction, make sure all interrupt flags are cleared or all interrupts are masked.
Power on
RESET = 0 ?
Yes
RAME = 0
Reset MCU
No
MCU
operation
cycle
Figure 14 MCU Operating Sequence (Power On)
27
HD404358 Series
MCU operation
cycle
IF:
Interrupt request flag
IM:
Interrupt mask
IE:
Interrupt enable flag
PC:
Program counter
CA:
Carry flag
ST:
Status flag
Low-power mode
operation cycle
Yes
IF = 1?
No
Instruction
execution
SBY/STOP
instruction?
No
←
PC Next
location
Yes
No
IM = 0 and
IE = 1?
Yes
←
IE 0
Stack (PC),
←
(CA),
(ST)
←
PC Vector
address
28
Figure 15 MCU Operating Sequence (MCU Operation Cycle)
Low-power mode
operation cycle
HD404358 Series
IF = 1 and
IM = 0?
Yes
Hardware NOP
execution
←
PC Next
Iocation
No
No
Standby mode
IF = 1 and
IM = 0?
Yes
Hardware NOP
execution
←
PC Next
Iocation
Instruction
execution
No
Stop mode
STOPC = 0?
Yes
RAME = 1
Reset MCU
MCU operation
cycle
For IF and IM operation, refer to figure 12.
Figure 16 MCU Operating Sequence (Low-Power Mode Operation)
29
HD404358 Series
Internal Oscillator Circuit
A block diagram of the clock generation circuit is shown in figure 17. As shown in table 20, a ceramic
oscillator or crystal oscillator can be connected to OSC1 and OSC2. The system oscillator can also be
operated by an external clock. See figure 18 for the layout of crystal and ceramic oscillator.
OSC
OSC
1/4
f
cyc
t
cyc
Timing
generator
circuit
ø
CPU
ø
PER
f
2
1
System
oscillator
OSC
division
circuit
CPU with ROM,
RAM, registers,
flags, and I/O
Peripheral
function
interrupt
Figure 17 Clock Generation Circuit
TEST
RESET
OSC
1
OSC
2
GND
30
AV
SS
Figure 18 Typical Layout of Crystal and Ceramic Oscillator
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