HITACHI HD404358 User Manual

HD404354

HD404358 Series

Rev. 6.0

Sept. 1998

Description

The HD404358 Series is a 4-bit HMCS400-Series microcomputer designed to increase program productivity and also incorporate large-capacity memory. Each microcomputer has an A/D converter, input capture timer, and two low-power dissipation modes.

The HD404358 Series includes seven chips: the HD404354, HD40A4354 with 4-kword ROM; the HD404356, HD40A4356 with 6-kword ROM; the HD404358, HD40A4358 with 8-kword ROM; the HD407A4359 with 16-kword PROM.

The HD40A4354, HD40A4356, HA40A4358, and HD407A4359 are high speed versions (minimum instruction cycle time: 0.47 s)

The HD407A4359 is a PROM version (ZTAT microcomputer). A program can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The ZTAT version is 27256-compatible.)

ZTAT : Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

•34 I/O pins

One input-only pin

33 input/output pins: 4 pins are intermediate-voltage NMOS open drain with high-current pins (15 mA, max.)

•On-chip A/D converter (8-bit 8-channel)

Low power voltage 2.7 V to 6.0 V

•Three timers

One event counter input

One timer output

One input capture timer

•Eight-bit clock-synchronous serial interface (1 channel)

•Alarm output

HD404358 Series

•Built-in oscillators

Ceramic oscillator or crystal

External clock drive is also possible

•Seven interrupt sources

Two by external sources

Three by timers

One by A/D converter

One by serial interface

•Two low-power dissipation modes

Standby mode

Stop mode

•Instruction cycle time

0.47 s (fOSC = 8.5 MHz, 1/4 division ratio): HD40A4354, HD40A4356, HD40A4358, HD407A4359

0.8 s (fOSC = 5 MHz, 1/4 division ratio): HD404354, HD404356, HD404358

Ordering Information

Instruction Cycle

ROM

RAM

Type

Time

Product Name

Model Name

(Words)

(Digit)

Package

Mask ROM

Standard versions

HD404354

HD404354S

4,096

384

DP-42S

(fOSC= 5 MHz)

HD404354H

FP-44A

HD404356

HD404356S

6,144

DP-42S

HD404356H

FP-44A

HD404358

HD404358S

8,192

DP-42S

HD404358H

FP-44A

High speed versions

HD40A4354

HD40A4354S

4,096

384

DP-42S

(fOSC= 8.5 MHz)

HD40A4354H

FP-44A

HD40A4356

HD40A4356S

6,144

DP-42S

HD40A4356H

FP-44A

HD40A4358

HD40A4358S

8,192

DP-42S

HD40A4358H

FP-44A

ZTAT

(fOSC= 8.5 MHz)

HD407A4359

HD407A4359S

16,384

512

DP-42S

HD407A4359H

FP-44A

HD404358 Series

Pin Arrangement

		RA 1																							R23
				1																		42


R00/SCK				2																		41			R22


	R01/SI			3																		40			R21


R02/SO				4																		39			R20


R03/TOC				5																		38			R13
R03/TOC				5																		38			R13
		TEST		6																		37			R12
		TEST		6																		37			R12
	RESET			7																		36			R11
	RESET			7																		36			R11
		OSC1		8																		35			R10
		OSC1		8																		35			R10
		OSC2		9																		34			R83
		OSC2		9																		34			R83
		GND		10								DP-42S										33			R82
		GND		10																		33			R82
		AVSS		11																		32			R81


R30/AN0				12																		31			R80


R31/AN1				13																		30			D8


R32/AN2				14																		29			D7


R33/AN3				15																		28			D6


R40/AN4				16																		27			D5
R40/AN4				16																		27			D5
R41/AN5				17																		26			D4/STOPC


R42/AN6				18																		25			D3/BUZZ


R43/AN7				19																		24			D2/EVNB
R43/AN7				19																		24			D2/EVNB
		AVCC		20																		23			D1/INT1
		AVCC		20																		23			D1/INT1
		V CC		21																		22			D0/INT0



					/TOC	/SO	/SI			/SCK				1		3		2		1	0	3
				NC	3	2	1			0				1		3		2		1	0	3
				NC	R0	R0		R0			R0				RA		R2	R2		R2	R2		R1


				44	43	42		41			40				39		38	37		36	35		34
TEST			1																					33		R12


RESET			2																					32		R11


OSC1			3																					31		R10
OSC1			3																					31		R10
OSC2			4																					30		R83
OSC2			4																					30		R83
GND			5									FP-44A												29		R82
GND			5																					29		R82
AVSS			6																					28		R81


R30/AN0			7																					27		R80


R31/AN1			8																					26		D8


R32/AN2			9																					25		D7


R33/AN3			10																					24		D6


R40/AN4			11	12	13	14		15			16				17		18	19		20	21		22	23		D5




				1	2	3			AV			V		0		1		2		3 /STOPC			NC
				/AN	/AN	/AN			CC				CC / INT			/ INT			/EVNB	/BUZZ
				5	6	7								0		1
				R4 R4 R4											D D				D	D	4
																					D

HD404358 Series

Pin Description

Pin Number

Item

Symbol

DP-42S

FP-44A

I/O

Function

Power

VCC

Applies power voltage

supply

GND

Connected to ground

Test

TEST

Cannot be used in user applications. Connect this pin

to GND.

Reset

RESET

Resets the MCU

Oscillator

OSC1

Input/output pin for the internal oscillator. Connect

these pins to the ceramic oscillator or crystal oscillator,

or OSC1 to an external oscillator circuit.

OSC2

Port

D0–D8

22–30

17–21,

I/O

Input/output pins addressed individually by bits; D0–D8

23–26

are all standard-voltage I/O pins.

RA1

One-bit standard-voltage input port pin

R00–R13,

2–5,

40–43,

I/O

Four-bit input/output pins consisting of standard-voltage

R30–R43,

12–19,

7–14

pins

R80–R83

31–38

27–34

R20–R23

39–42

35–38

I/O

Four-bit input/output pins consisting of intermediate

voltage pins

Interrupt

INT0, INT1

22, 23

17, 18

Input pins for external interrupts

Stop clear

STOPC

Input pin for transition from stop mode to active mode

Serial

SCK

I/O

Serial interface clock input/output pin

Interface

Serial interface receive data input pin

Serial interface transmit data output pin

Timer

TOC

Timer output pin

EVNB

Event count input pin

Alarm

BUZZ

Square waveform output pin

A/D

AVCC

Power supply for the A/D converter. Connect this pin

converter

as close as possible to the VCC pin and at the same

voltage as VCC. If the power supply voltage to be used

for the A/D converter is not equal to VCC, connect a 0.1-

F bypass capacitor between the AVCC and AVSS pins.

(However, this is not necessary when the AVCC pin is

directly connected to the VCC pin.)

AVSS

Ground for the A/D converter. Connect this pin as

close as possible to GND at the same voltage as GND.

AN0–AN7

12–19

7–14

Analog input pins for the A/D converter

HD404358 Series

Block Diagram

					1	2
				RESET	TEST STOPC OSC	CC	GND
				RESET	TEST STOPC OSC	OSC V	GND
INT0					System control
		Interrupt			System control
		Interrupt
		control			RAM					D0
INT1					RAM
INT1					(384 × 4 bits)					D1
					(512 × 4 bits)					D2
									D port	D3
						W				D4
						W				D5
		Timer A				(2 bits)				D5
		Timer A				(2 bits)				D6
										D6
						X				D7
						(4 bits)				D8
									port	R00
EVNB		Timer B				SPX			port	R01
						SPX			R0	R02
						(4 bits)			R0	R02
						Y				R03
						Y
						(4 bits)
				bus					port	R10
TOC		Timer C		bus					port	R11
			Internal data bus	Internal address		SPY		Internal data bus	port R1	R12
						SPY				R13
						(4 bits)				R13
SI										R20
SO		Serial								R21
		interface							R2	R22
SCK									R2	R22
SCK										R23
							ALU			R23
							ALU
AVSS										R30
									port	R30
AN0	•								port	R31
•	•	A/D				ST	CA		R3	R32
•	•	A/D				ST	CA		R3	R32
•	•	converter				(1 bit)	(1 bit)			R33
AN7										R33
AN7
AVCC						A
AVCC						(4 bits)				R40
						(4 bits)			port	R40
						B			port	R41
						B			R4	R42
						(4 bits)			R4	R42
BUZZ		Buzzer				SP				R43
						SP
						(10 bits)
Data bus									port	R80
Data bus					Instruction		PC			R81
					Instruction		PC			R81
					decoder		(14 bits)			R82
					decoder		(14 bits)		R8
									R8
Intermediate										R83
Intermediate
voltage pin					ROM
					ROM
				(4,096 × 10 bits) (6,144 × 10 bits)					port
				(16,384 × 10 bits)(8,192 × 10 bits)					port	RA1
Directional									RA	RA1
Directional
signal line
signal line
										5

HD404358 Series

Memory Map

ROM Memory Map

The ROM memory map is shown in figure 1 and described below.

Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address.

Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction.

Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000-$0FFF (HD404354, HD40A4354), $0000–$17FF (HD404356, HD40A4356), $0000–$1FFF (HD404358, HD40A4358), $0000–$3FFF (HD407A4359)): The entire ROM area can be used for program coding.

$0000		$0000	JMPL instruction
	Vector address	$0001	(jump to RESET, STOPC routine)
	(16 words)
$000F	(16 words)	$0002	JMPL instruction
$000F		$0002	JMPL instruction
$0010		$0003	(jump to INT 0 routine)
		$0003	(jump to INT 0 routine)
	Zero-page subroutine	$0004	JMPL instruction
		$0004	JMPL instruction
		$0005	(jump to INT 1 routine)
	(64 words)
$003F	(64 words)	$0006	JMPL instruction
		$0006	JMPL instruction
		$0007	(jump to timer A routine)
$0040


	Pattern (4,096 words)	$0008	JMPL instruction
	Pattern (4,096 words)	$0008	JMPL instruction
$0FFF	Program (4,096 words)	$0009	(jump to timer B routine)
	For HD404354, HD40A4354	$0009	(jump to timer B routine)
	For HD404354, HD40A4354	$000A	JMPL instruction
$1000		$000A	JMPL instruction
$1000	Program	$000B	(jump to timer C routine)
$17FF	(6,144 words)	$000C	JMPL instruction
$17FF	For HD404356, HD40A4356	$000D	(jump to A/D converter routine)
$1800	Program	$000E	JMPL instruction
	Program	$000F	(jump to serial routine)
	(8,192 words)	$000F	(jump to serial routine)
$1FFF	For HD404358, HD40A4358
$2000	Program
	Program
	(16,384 words)
	HD407A4359
$3FFF
$3FFF

Note: Since the ROM address areas between $0000–$0FFF overlap, the user can determine how these areas are to be used.

Figure 1 ROM Memory Map

HD404358 Series

RAM Memory Map

The HD404354, HD40A4354, HD404356, HD40A4356, HD404358 and HD40A4358 MCUs contain 384digit × 4-bit RAM areas. The HD407A4359 MCU contain 512-digit × 4-bit RAM areas. Both of these RAM areas consist of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space labeled as a RAM-mapped register area. The RAM memory map is shown in figure 2 and described below.

RAM-Mapped Register Area ($000–$03F):

•Interrupt Control Bits Area ($000–$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

•Special Function Register Area ($004–$01F, $024–$03F)

This area is used as mode registers and data registers for external interrupts, serial interface, timer/counters, A/D converter, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers.

•Register Flag Area ($020–$023)

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/ SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4.

Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6.

Data Area ($050–$17F for HD404354/HD40A4354/HD404356/HD40A4356/HD404358/HD40A4358, $050–$1FF for HD407A4359)

Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage.

HD404358 Series

RAM Memory Map

$000

$040 $050

$180

$200

$3C0

$3FF

Initial values

after reset

$000

Interrupt control bits area

RAM-mapped registers

$003

$004

Port mode register A

(PMRA)

0000

Memory registers (MR)

$005

Serial mode register

(SMR)

0000

$006

Serial data register lower

(SRL)

R/W

Undefined

HD404354, HD40A4354,

$007

Serial data register upper (SRU)

R/W

Undefined

HD404356, HD40A4356,

$008

Timer mode register A

(TMA)

-000

HD404358, HD40A4358

$009

Timer mode register B1

(TMB1)

0000

Data (304 digits)

$00A

Timer B

(TRBL/TWBL)

R/W

*2/0000

$00B

(TRBU/TWBU)

R/W

Undefined

HD407A4359

$00C

Miscellaneous register

(MIS)

00--

Data (432 digits)

$00D

Timer mode register C

(TMC)

0000

$00E

Timer C

(TRCL/TWCL)

R/W

*2/0000

$00F

(TRCU/TWCU)

R/W

Undefined

Not used

Stack (64 digits)

$016

A/D channel register

(ACR)

-000

$017

A/D data register lower

(ADRL)

0000

$018

A/D data register upper

(ADRU)

1000

$019

A/D mode register 1

(AMR1)

0000

$01A

A/D mode register 2

(AMR2)

--00

Not used

$020

$023

$024

Port mode register B

(PMRB)

0000

$025

Port mode register C

(PMRC)

00-0

$026

Timer mode register B2

(TMB2)

-000

Not used

$02C

Port D0–D3 DCR

(DCD0)

0000

Notes: 1. Two registers are mapped

$02D

Port D4–D7 DCR

(DCD1)

0000

$02E

Port D8 DCR

(DCD2)

---0

on the same area ($00A,

$00B, $00E, $00F).

$02F

Not used

2. Undefined.

$030

Port R0 DCR

(DCR0)

0000

$031

Port R1 DCR

(DCR1)

0000

R: Read only

$032

Port R2 DCR

(DCR2)

0000

W: Write only

$033

Port R3 DCR

(DCR3)

0000

R/W: Read/write

$034

Port R4 DCR

(DCR4)

0000

Not used

$038

Port R8 DCR

(DCR8)

0000

$03F

Not used

$00A

Timer read register B lower (TRBL)

Timer write register B lower (TWBL)

$00B

Timer read register B upper (TRBU)

Timer write register B upper (TWBU) W

$00E

Timer read register C lower (TRCL)

Timer write register C lower (TWCL)

$00F

Timer read register C upper (TRCU)

Timer write register C upper (TWCU) W

Figure 2 RAM Memory Map

HD404358 Series

Bit 3

Bit 2

Bit 1

Bit 0

IM0

IF0

RSP

(Interrupt

$000

(IM of INT0)

(IF of INT0)

(Reset SP bit)

enable flag)

IMTA

IFTA

IM1

IF1

$001

(IM of timer A)

(IF of timer A)

(IM of INT1)

(IF of INT1)

IMTC

IFTC

IMTB

IFTB

$002

(IM of timer C)

(IF of timer C)

(IM of timer B)

(IF of timer B)

IMS

IFS

IMAD

IFAD

$003

(IM of serial)

(IF of serial)

(IM of A/D)

(IF of A/D)

Interrupt control bits area

Bit 3

Bit 2

Bit 1

Bit 0

ADSF

WDON

Not used

(Watchdog

Not used

$020

(A/D start flag)

on flag)

RAME

IAOF

ICEF

ICSF

(RAM enable

(Input capture

$021

(IAD off flag)

flag)

error flag)

status flag)

$022

IF:

Interrupt request flag

Not used

$023

IM:

Interrupt mask

IE:

Interrupt enable flag

			SP: Stack pointer
	Register flag area		SP: Stack pointer
	Register flag area

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

	SEM/SEMD	REM/REMD	TM/TMD
IE
IM	Allowed	Allowed	Allowed
IAOF
IF
ICSF	Not executed	Allowed	Allowed
ICEF	Not executed	Allowed	Allowed
ICEF
RAME
RSP	Not executed	Allowed	Inhibited
WDON	Allowed	Not executed	Inhibited
ADSF	Allowed	Inhibited	Allowed
Not used	Not executed	Not executed	Inhibited

Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.

The REM or REMD instuction must not be executed for ADSF during A/D conversion. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes invalid.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404358 Series

Bit 3

Bit 2

Bit 1

Bit 0

$000

Interrupt control bits area

$003

PMRA $004

D3 /BUZZ

R03/TOC

R01/SI

R02/SO

SMR $005

R00 /SCK

Serial transmit clock speed selection

SRL $006

Serial data register (lower digit)

SRU $007

Serial data register (upper digit)

TMA $008

Not used

Clock source selection (timer A)

TMB1 $009

Clock source selection (timer B)

TRBL/TWBL $00A

Timer B register (lower digit)

TRBU/TWBU $00B

Timer B register (upper digit)

MIS $00C

SO PMOS control

Not used

TMC $00D

Clock source selection (timer C)

TRCL/TWCL $00E

Timer C register (lower digit)

TRCU/TWCU $00F

Timer C register (upper digit)

Not used

ACR $016

Not used

Analog channel selection

ADRL $017

A/D data register (lower digit)

ADRU $018

A/D data register (upper digit)

AMR1$019

R33/AN3

R32/AN2

R31/AN1

R30/AN0

AMR2 $01A

Not used

R4/AN4–AN7

Not used

$020

$023

PMRB $024

D4/STOPC

D2/EVNB

D1/INT1

D0/INT0

PMRC $025

Buzzer output

TMB2 $026

Not used

EVNB detection edge selection

Not used

DCD0 $02C

Port D3 DCD

Port D2 DCD

Port D1 DCD

Port D0 DCD

DCD1 $02D

Port D7 DCD

Port D6 DCD

Port D5 DCD

Port D4 DCD

DCD2 $02E

Not used

Port D8 DCD

Not used

DCR0 $030

Port R03 DCR

Port R02 DCR

Port R01 DCR Port R00 DCR

DCR1 $031

Port R13 DCR

Port R12 DCR

Port R11 DCR Port R10 DCR

DCR2 $032

Port R23 DCR

Port R22 DCR

Port R21 DCR Port R20 DCR

DCR3 $033

Port R33 DCR

Port R32 DCR

Port R31 DCR Port R30 DCR

DCR4 $034

Port R43 DCR

Port R42 DCR

Port R41 DCR Port R40 DCR

Not used

DCR8 $038 Port R83 DCR Port R82 DCR Port R81 DCR Port R80 DCR

Not used

$03F

Notes: 1. Auto-reload on/off

2.Pull-up MOS control

3.A/D conversion time

4.SO output level control in idle states

5.Serial clock source selection

6.Input capture selection

Figure 5 Special Function Register Area

HD404358 Series

Memory registers

64	MR(0)	$040
65	MR(1)	$041
66	MR(2)	$042
67	MR(3)	$043
68	MR(4)	$044
69	MR(5)	$045
70	MR(6)	$046
71	MR(7)	$047
72	MR(8)	$048
73	MR(9)	$049

74MR(10) $04A

75MR(11) $04B

76MR(12) $04C

77MR(13) $04D

78MR(14) $04E

79MR(15) $04F

Stack area

960	Level 16	$3C0
	Level 15
	Level 14
	Level 13
	Level 12
	Level 11
	Level 10			Bit 3	Bit 2	Bit 1	Bit 0
	Level 9			Bit 3	Bit 2	Bit 1	Bit 0
	Level 8		1020	ST	PC13	PC12	PC11	$3FC
	Level 7		1020	ST	PC13	PC12	PC11	$3FC
	Level 6		1021	PC10	PC9	PC8	PC7	$3FD
	Level 5		1021	PC10	PC9	PC8	PC7	$3FD
	Level 4		1022	CA	PC6	PC5	PC4	$3FE
	Level 3		1022	CA	PC6	PC5	PC4	$3FE
	Level 2		1023	PC3	PC2	PC1	PC0	$3FF
1023	Level 1	$3FF	1023	PC3	PC2	PC1	PC0	$3FF

PC13–PC0 : Program counter

ST: Status flag

CA: Carry flag

Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position

HD404358 Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations. They are shown in figure 7 and described below.

					3			0
Accumulator	Initial value: Undefined, R/W					(A)

					3			0
B register	Initial value: Undefined, R/W					(B)

						1		0
W register	Initial value: Undefined, R/W						(W)

					3			0
X register	Initial value: Undefined, R/W					(X)

					3			0
Y register	Initial value: Undefined, R/W					(Y)

					3			0
SPX register	Initial value: Undefined, R/W					(SPX)

					3			0
SPY register	Initial value: Undefined, R/W					(SPY)

								0
Carry	Initial value: Undefined, R/W							(CA)

								0
Status	Initial value: 1, no R/W							(ST)

Program counter	13							0
Program counter
Initial value: 0,			(PC)
no R/W
no R/W		9			5			0
		9			5			0
Stack pointer		1	1	1	1	(SP)
Initial value: $3FF, no R/W		1	1	1	1	(SP)
Initial value: $3FF, no R/W

Figure 7 Registers and Flags

Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit (ALU) and transfer data between memory, I/O, and other registers.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for indirect RAM addressing. The Y register is also used for D-port addressing.

HD404358 Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction, not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL, CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read, regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a stack can be used up to 16 levels.

The SP can be initialized to $3FF in another way: by resetting the RSP bit with the REM or REMD instruction.

Reset

The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation, RESET must be high for at least two instruction cycles.

Initial values after MCU reset are listed in table 1.

Interrupts

The MCU has 7 interrupt sources: two external signals (INT0 and INT1), three timer/counters (timers A, B, and C), serial interface, and A/D converter.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1.

A block diagram of the interrupt control circuit is shown in figure 8, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 7 interrupt sources are listed in table 3.

HD404358 Series

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source.

The interrupt processing sequence is shown in figure 9 and an interrupt processing flowchart is shown in figure 10. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program.

HD404358 Series

Table 1

Initial Values After MCU Reset

Item

Abbr.

Initial Value

Contents

Program counter

(PC)

$0000

Indicates program execution point

from start address of ROM area

Status flag

(ST)

Enables conditional branching

Stack pointer

(SP)

$3FF

Stack level 0

Interrupt

Interrupt enable flag

(IE)

Inhibits all interrupts

flags/mask

Interrupt request flag

(IF)

Indicates there is no interrupt

request

Interrupt mask

(IM)

Prevents (masks) interrupt requests

I/O

Port data register

(PDR)

All bits 1

Enables output at level 1

Data control register

(DCD0 –

All bits 0

Turns output buffer off (to high

DCD1)

impedance)

(DCD2)

- - - 0

(DCR0 –

All bits 0

DCR4,

DCR8)

Port mode register A

(PMRA)

0000

Refer to description of port mode

Port mode register B bits

(PMRB2 –

000

Refer to description of port mode

2–0

PMRB0)

Port mode register C

(PMRC)

00 - 0

Refer to description of port mode

Timer/

Timer mode register A

(TMA)

- 000

Refer to description of timer mode

counters,

serial

interface

Timer mode register B1

(TMB1)

0000

Refer to description of timer mode

Timer mode register B2

(TMB2)

- 000

Refer to description of timer mode

Timer mode register C

(TMC)

0000

Refer to description of timer mode

Serial mode register

(SMR)

0000

Refer to description of serial mode

Prescaler S

(PSS)

$000

—

Timer counter A

(TCA)

$00

—

Timer counter B

(TCB)

$00

—

Timer counter C

(TCC)

$00

—

Timer write register B

(TWBU,

$X0

—

TWBL)

Timer write register C

(TWCU,

$X0

—

TWCL)

Octal counter

000

—

HD404358 Series

			Initial
Item		Abbr.	Value	Contents

A/D	A/D mode register 1	(AMR1)	0000	Refer to description of A/D mode register

	A/D mode register 2	(AMR2)	- - 00

	A/D channel register	(ACR)	- 000	Refer to description of A/D channel register

	A/D data register	(ADRL)	0000	Refer to description of A/D data register

		(ADRU)	1000

Bit registers	Watchdog timer on flag	(WDON)	0	Refer to description of timer C

	A/D start flag	(ADSF)	0	Refer to description of A/D converter

	IAD off flag	(IAOF)	0	Refer to the description of A/D converter

	Input capture status flag	(ICSF)	0	Refer to description of timer B

	Input capture error flag	(ICEF)	0	Refer to description of timer B

Others	Miscellaneous register	(MIS)	00 - -	Refer to description of operating modes, I/O,
				and serial interface

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. – indicates that the bit does not exist.

		Status After Cancellation of	Status After all Other Types of
Item	Abbr.	Stop Mode by STOPC Input	Reset

Carry flag	(CA)

Accumulator	(A)

B register	(B)

W register	(W)

X/SPX register	(X/SPX)

Y/SPY register	(Y/SPY)

Pre-stop-mode values are not guaranteed; values must be initialized by program

Pre-MCU-reset values are not guaranteed; values must be initialized by program

Serial data register

(SRL, SRU)

RAM

Pre-stop-mode values are

retained

RAM enable flag

(RAME)

Port mode register

(PMRB3)

Pre-stop-mode values are

B bit 3

retained

HD404358 Series

Table 2	Vector Addresses and Interrupt Priorities
Reset/Interrupt		Priority	Vector Address

RESET, STOPC*		—	$0000

INT0		1	$0002

INT1		2	$0004

Timer A		3	$0006

Timer B		4	$0008

Timer C		5	$000A

A/D		6	$000C

Serial		7	$000E

Note: * The STOPC interrupt request is valid only in stop mode.

HD404358 Series

	$ 000,0
		IE
	$ 000,2
INT0 interrupt		IFO
INT0 interrupt		IFO
	$ 000,3
	$ 000,3
		IMO
		IMO

	$ 001,0
INT1 interrupt	$	IF1
INT1 interrupt		IF1
		001,1
		001,1
		IM1
		IM1

	$ 001,2
Timer A interrupt		IFTA

	$ 001,3
	$ 001,3
	$	IMTA

		002,0
Timer B interrupt		IFTB

	$ 002,1
	$ 002,1
		IMTB
		IMTB

	$ 002,2
Timer C interrupt		IFTC

	$ 002,3
	$ 002,3
		IMTC
		IMTC

	$ 003,0
A/D interrupt		IFAD

	$ 003,1
	$ 003,1
		IMAD
		IMAD

	$ 003,2
Serial interrupt		IFS
	$ 003,3
	$ 003,3
		IMS
		IMS

Sequence control

• Push PC/CA/ST

• Reset IE

• Jump to vector address

Vector address

Priority control logic

Note: $m,n is RAM address $m, bit number n.

Figure 8 Interrupt Control Circuit

HD404358 Series

Table 3	Interrupt Processing and Activation Conditions
		Interrupt Source

		INT0	INT1	Timer A	Timer B	Timer C	A/D	Serial

IE	1		1	1	1	1	1	1

IF0 · IM0	1		0	0	0	0	0	0

IF1 · IM1	*		1	0	0	0	0	0

IFTA · IMTA	*		*	1	0	0	0	0

IFTB · IMTB	*		*	*	1	0	0	0

IFTC ·IMTC	*		*	*	*	1	0	0

IFAD · IMAD	*		*	*	*	*	1	0

IFS · IMS	*		*	*	*	*	*	1

Note: Bits marked * can be either 0 or 1. Their values have no effect on operation.

Instruction cycles
	1		2	3	4	5		6

Instruction execution*

Stacking

Interrupt

acceptance Vector address IE reset

generation

		Execution of JMPL
		instruction at vector address


			Execution of
			instruction at
			start address
Note:	* The stack is accessed and the IE reset after the instruction		of interrupt
Note:			routine
	is executed, even if it is a two-cycle instruction.		routine
	is executed, even if it is a two-cycle instruction.

Figure 9 Interrupt Processing Sequence

HD404358 Series

Power on
RESET = 0?	No
RESET = 0?
Yes	Interrupt	Yes
	Interrupt	Yes
	request?
	No	No
		No	IE = 1?
			IE = 1?
			Yes
Reset MCU	Execute instruction		Accept interrupt
	PC ←(PC) + 1		IE ← 0
	PC ←(PC) + 1		Stack ←	(PC)
			Stack ←	(CA)
			Stack ←	(ST)
	PC← $0002	Yes	INT0
		Yes
			interrupt?
			No
	PC← $0004	Yes	INT1
			interrupt?
			No
	PC← $0006	Yes	Timer-A
	PC← $0006		interrupt?
			interrupt?
			No
	PC← $0008	Yes	Timer-B
	PC← $0008		Timer-B
			interrupt?
			No
	PC←$000A	Yes	Timer-C
	PC←$000A		Timer-C
			interrupt?
			No
	PC←$000C	Yes	A/D
	PC←$000C		interrupt?
			interrupt?
			No
	PC←$000E	(serial interrupt)
	PC←$000E

Figure 10 Interrupt Processing Flowchart

HD404358 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4.

Table 4 Interrupt Enable Flag (IE: $000, Bit 0)

IE	Interrupt Enabled/Disabled

0Disabled

1Enabled

External Interrupts (INT0, INT1): Two external interrupt signals.

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): IF0 and IF1 are set at the rising edge of signals input to INT0 and INT1, as listed in table 5.

Table 5 External Interrupt Request Flags (IF0: $000, Bit2; IF1: $001, Bit 0)

IF0, IF1

Interrupt Request

0No

1Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6.

Table 6 External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1)

IM0, IM1

Interrupt Request

0Enabled

1Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7.

Table 7 Timer A Interrupt Request Flag (IFTA: $001, Bit 2)

IFTA	Interrupt Request

0No

1Yes

Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8.

HD404358 Series

Table 8 Timer A Interrupt Mask (IMTA: $001, Bit 3)

IMTA	Interrupt Request

0Enabled

1Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 0): Set by overflow output from timer B, as listed in table 9.

Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 0)

IFTB	Interrupt Request

0No

1Yes

Timer B Interrupt Mask (IMTB: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer B interrupt request flag, as listed in table 10.

Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 1)

IMTB	Interrupt Request

0Enabled

1Disabled (masked)

Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 11.

Table 11 Timer C Interrupt Request Flag (IFTC: $002, Bit 2)

IFTC	Interrupt Request

0No

1Yes

Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 12.

Table 12 Timer C Interrupt Mask (IMTC: $002, Bit 3)

IMTC	Interrupt Request

0Enabled

1Disabled (masked)

HD404358 Series

Serial Interrupt Request Flag (IFS: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 13.

Table 13 Serial Interrupt Request Flag (IFS: $003, Bit 2)

IFS	Interrupt Request

0No

1Yes

Serial Interrupt Mask (IMS: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial interrupt request flag, as listed in table 14.

Table 14 Serial Interrupt Mask (IMS: $003, Bit 3)

Mask IMS Interrupt Request

0Enabled

1Disabled (masked)

A/D Interrupt Request Flag (IFAD: $003, Bit 0): Set at the completion of A/D conversion, as listed in table 15.

Table 15 A/D Interrupt Request Flag (IFAD: $003, Bit 0)

IFAD	Interrupt Request

0No

1Yes

A/D Interrupt Mask (IMAD: $003, Bit 1): Prevents (masks) an interrupt request caused by the A/D interrupt request flag, as listed in table 16.

Table 16 A/D Interrupt Mask (IMAD: $003, Bit 1)

IMAD	Interrupt Request

0Enabled

1Disabled (masked)

HD404358 Series

Operating Modes

The MCU has three operating modes as shown in table 17. The operations in each mode are listed in tables 18 and 19. Transitions between operating modes are shown in figure 11.

Table 17 Operating Modes and Clock Status

		Mode Name
		Active	Standby	Stop

Activation method		RESET cancellation,	SBY instruction	STOP instruction
		interrupt request, STOPC
		cancellation in stop mode

Status	System	OP	OP	Stopped
	oscillator

Cancellation		RESET input, STOP/ SBY	RESET input, interrupt	RESET input, STOPC
method		instruction	request	input in stop mode

Note: OP implies in operation

Table 18 Operations in Low-Power Dissipation Modes

Function	Stop Mode	Standby Mode
CPU	Reset	Retained

RAM	Retained	Retained

Timer A	Reset	OP

Timer B	Reset	OP

Timer C	Reset	OP

Serial	Reset	OP

A/D	Reset	OP

I/O	Reset	Retained

Note: OP implies in operation

Table 19 I/O Status in Low-Power Dissipation Modes

Output

Input

Standby Mode

Stop Mode

Active Mode

RA1

—

Input enabled

R0–D8, R0–R4,

Retained or output of

High impedance

Input enabled

R8,

peripheral functions

HD404358 Series

		Reset by
		RESET input or
		by watchdog timer
	RAME = 0		RAME = 1
		RESET 1	RESET 2
		Active		STOPC
		Active
Standby mode		mode
	SBY
fOSC: Oscillate	instruction	fOSC:	Oscillate	STOP
ø CPU: Stop		ø CPU:	fcyc	instruction
ø CPU: Stop	Interrupt	ø CPU:	fcyc
ø PER: fcyc	Interrupt	ø PER:	fcyc
ø PER: fcyc		ø PER:	fcyc

Stop mode

fOSC: Stop

ø CPU: Stop

ø PER: Stop

fOSC: Main oscillation frequency

fcyc: fOSC/4

øCPU: System clock

øPER: Clock for other peripheral

functions

Figure 11 MCU Status Transitions

Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC 1 and OSC2.

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. A flowchart of operation in standby mode is shown in figure 12.

HD404358 Series

Stop

Standby

Oscillator: Stop Peripheral clocks: Stop All other clocks: Stop

Oscillator: Active Peripheral clocks: Active All other clocks: Stop

No	RESET = 0?	No
RESET = 0?	RESET = 0?
Yes	Yes		No
No		IF0 • IMO = 1?
No
STOPC = 0?		Yes
		Yes	No
			IF1 • IM1 = 1?
Yes
			Yes		No
			IFTA • IMTA		No
			IFTA • IMTA
				= 1?
				Yes	IFTB •	No
					IMTB = 1?
RAME = 1	RAME = 0				Yes	IFTC •	No
					Yes	IFTC •	No
						IMTC = 1?
						Yes	IFAD •	No
							IMAD = 1?
							Yes	IFS •	No
								IFS •	No
								IMS = 1?
								Yes
	Restart		Restart
	processor clocks		processor clocks
				Execute
				next instruction
			No		IF = 1,	Yes
			No	IM = 0, and		Yes
				IM = 0, and
					IE = 1?
	Reset MCU		Execute			Accept interrupt
	Reset MCU	next instruction				Accept interrupt
		next instruction

Figure 12 MCU Operation Flowchart

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops.

Stop mode is terminated by a RESET input or a STOPC input as shown in figure 13. RESET or STOPC must be applied for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and serial data register cannot be guaranteed.

HD404358 Series

Stop mode

Oscillator

Internal clock

RESET

or STOPC

tres

STOP instruction execution

tres ³ tRC (stabilization period)

Figure 13 Timing of Stop Mode Cancellation

Stop Mode Cancellation by STOPC: The MCU enters active mode from stop mode by inputting STOPC as well as by RESET. In either case, the MCU starts instruction execution from the starting address (address 0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode; STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode has been cancelled by STOPC (for example, when the RAM contents before entering stop mode is used after transition to active mode), execute the TEST instruction to the RAM enable flag (RAME) at the beginning of the program.

MCU Operation Sequence: The MCU operates in the sequence shown in figure 15. It is reset by an asynchronous RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 16. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked.

	Power on
	RESET = 0	No
	RESET = 0	?
	Yes
	RAME = 0	MCU
	RAME = 0	operation
		operation
		cycle
	Reset MCU

Figure 14 MCU Operating Sequence (Power On)

HD404358 Series

	MCU operation
	cycle
	IF = 1?	Yes
	IF = 1?
	No	No	IM = 0 and
			IE = 1?
	Instruction		Yes
	execution
			IE ← 0
Yes	SBY/STOP		Stack ← (PC),
	instruction?		(CA),
			(ST)
	No
Low-power mode	PC ← Next		PC ← Vector
operation cycle	location		address

IF: Interrupt request flag

IM: Interrupt mask

IE: Interrupt enable flag

PC: Program counter

CA: Carry flag

ST: Status flag

Figure 15 MCU Operating Sequence (MCU Operation Cycle)

HD404358 Series

Low-power mode operation cycle

IF = 1 and	No
IM = 0?
Yes
		Standby mode		Stop mode
	No	IF = 1 and	No	STOPC = 0?
		IM = 0?		STOPC = 0?
		IM = 0?
		Yes		Yes
Hardware NOP		Hardware NOP		RAME = 1
execution		execution		RAME = 1
execution		execution

PC ← Next

Iocation

MCU operation

cycle

PC ← Next

Iocation

Instruction

execution

Reset MCU

For IF and IM operation, refer to figure 12.

Figure 16 MCU Operating Sequence (Low-Power Mode Operation)

HD404358 Series

Internal Oscillator Circuit

A block diagram of the clock generation circuit is shown in figure 17. As shown in table 20, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2. The system oscillator can also be operated by an external clock. See figure 18 for the layout of crystal and ceramic oscillator.

OSC2	System	fOSC	1/4	fcyc	Timing	ø CPU	CPU with ROM,
OSC2	System	fOSC	1/4	fcyc	Timing	ø CPU	RAM, registers,
	oscillator		division		generator		RAM, registers,
	oscillator		division	tcyc	generator		flags, and I/O
			circuit	tcyc	circuit		flags, and I/O
			circuit		circuit
OSC1



						ø PER	Peripheral
						ø PER	Peripheral
							function
							function
							interrupt

Figure 17 Clock Generation Circuit

TEST

RESET

OSC1

OSC2

GND

AVSS

Figure 18 Typical Layout of Crystal and Ceramic Oscillator

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