HITACHI HD155101BF User Manual

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RF Single-chip Linear IC for GSM and EGSM Systems

Description

The HD155101BF was developed for GSM and EGSM cellular systems, and integrates most of the
functions of a transceiver. The HD155101BF incorporates the bias circuit for a RF LNA, a 1st mixer, 1st­IF amplifier, 2nd mixer, AGC amplifier and an IQ quadrature demodulator for the receiver, and an IQ
quadrature modulator and offset PLL for the transmitter. Also, on chip are the dividers for the 1st & 2nd
local oscillator signals and 90˚ phase splitter. Moreover the HD155101BF includes control circuits to
implement power saving modes. These functions can operate down to 2.7 V and are housed in a 48-pin
LQFP SMD package.

HD155101BF

ADE-207-256A (Z)

2nd Edition

September 1998

Hence the HD155101BF can form a small size transceiver handset for GSM and EGSM by adding a PLL
frequency synthesizer IC, a power amplifier and some external components. See page 7 “Configuration”.

The HD155101BF is fabricated using a 0.6 µm double-polysilicon Bi-CMOS process.

Functions

Receiver (RX)

• Low Noise Amplifier (LNA) bias circuit

• 1st mixer

• IF amplifier

• 2nd mixer

• Automatic gain control amplifier (AGC)

• IQ demodulator with 90° phase splitter

Transmitter (TX)

• IQ modulator with 90° phase splitter

• Offset PLL
 Down converter
 Phase comparator
 TX VCO driver

HD155101BF

Others

• IF dividers

• Power saving circuit

• IFVCO

Features

• Highly integrated RF processing for hand-portables

• Wide operating frequency

RX:

 RF: 925 to 960 MHz
 1st IF: 130 to 300 MHz
 2nd IF: 26 to 60 MHz

TX:

 RF: 880 to 915 MHz
 IF: 156 to 360 MHz

• Offset PLL architecture reduces TX spurious

• Low current consumption (Vcc = 3 V)

RX mode: 42.5 mA Typ (including IFVCO current (2.5 mA Typ)) + LNA transistor current (5.6 mA
Typ)

TX mode: 38.0 mA Typ (including IFVCO current (2.5 mA Typ))
Idle mode: 1 µA Typ

• Operating supply voltage:
 Phase comparator and TX VCO driver circuits: 2.7 to 5.25 V
 Other blocks: 2.7 to 3.6 V

• Operating temperature range: –20 to +85°C

• 48 pin SMD Low Profile Quad Flat Package (LQFP): FP-48

2

HD155101BF

Pin Arrangement

The HD155101BF is housed in a 48-pin LQFP SMD package to which is suitable for applications where
space is limited. “Pin Functions” shows the arrangement and roles assigned for each pin of the
HD155101BF.

MIX1IN

MIX1INB

GNDMIX1

VCCMIX1

RFLOIN

MIX1OUTB

MIX1OUT

VCCIF

GNDIF

IFIN

IFINB

MIX2O

373839404142434445464748

POONRX1

1

36

MIX2OB

POONRX2

RFOUT

VCCLNA

GNDLNA

RFIN

POONTX

VCCPLL

GNDPLL

VCOIN

VCCCOMP

PLLOUT

2

3

4

5

6

7

8

9

10

11

12

QINB

ICURAD

QIN

IINB

181716151413

IIN

MODB

(Top View)

MOD

VCCIQ

IFLO

GNDIQ

35

34

33

32

31

30

29

28

27

26

25

242322212019

IFVCOI

IFVCOO

GNDAGC

VCCAGC

AGCOUT

AGCOUTB

VCCDIV

GNDDIV

VCONT

IOUT

IOUTB

QOUT

QOUTB

3

HD155101BF

Pin Functions

Pin
No. Symbol

1 POONRX1 Input PO wer ON for RX1 If ‘H’, LNA and MIX1 are active.

2 POONRX2 Input PO wer ON for RX2 LNA and MIX1 don’t care.

3 RFOUT Output RF signal OUT put Open collector type output of LNA.

4 VCCLNA Vcc VCC of LNA block Power supply of LNA
5 GNDLNA Gnd GND of LNA block Ground of LNA
6 RFIN Input RF signal IN put Input of LNA.

7 POONTX Input PO wer ON for TX If ‘H’, the blocks for transmitter are active.

8 VCCPLL Vcc VCC of O PLL block Power supply for offset PLL except phase

9 GNDPLL Gnd GND of O PLL block Ground of offset PLL
10 VCOIN Input VCO signal IN put Input of Tx. VCO signal
11 VCCCOMP Vcc VCC of phase

12 PLLOUT Output O PLL OUT put Current output to control and modulate Tx. VCO

13 ICURAD Input I CUR rent AD just This pin should be connected an external R to

14 QINB Input Q signal IN put B ar Q negative signal input of IQ quadrature modulator
15 QIN Input Q signal IN put Q positive signal input of IQ quadrature modulator
16 IINB Input I signal IN put B ar I negative signal input of IQ quadrature modulator
17 IIN Input I signal IN put I positive signal input of IQ quadrature modulator
18 MODB Output MOD ulator output B ar Negative output of IQ quadrature modulator
19 MOD Output MOD ulator output Positive output of IQ quadrature modulator
20 VCCIQ Vcc VCC of IQ block Power supply of IQ block
21 IFLO Input/

22 GNDIQ Gnd GND of IQ block Ground of IQ block
23 IFVCOO Output IFVCO O utput Emitter of IFVCO transistor
24 IFVCOI Input IFVCO I nput Base of IFVCO transistor

Input/
Output Meaning of symbol Function

Other receiver blocks don’t care.

If ‘H’, Other receiver blocks are active.

The collector of LNA transistor.

The base of LNA transistor

The reciver blocks don’t care.

comparator

Power supply for just phase comparator of offset

Output

COMP arator

IF LO cal signal
input/output

PLL

This pin should be connected external loop filter.

determine charge pump current of phase
comparator

IF local signal input to be fed to divider

4

Pin Function (cont)

HD155101BF

Pin
No. Symbol

25 QOUTB Output Q signal OUT put B ar Q negative signal output of IQ quadrature

26 QOUT Output Q signal OUT put Q positive signal output of IQ quadrature

27 IOUTB Output I signal OUT put B ar I negative signal output of IQ quadrature

28 IOUT Output I signal OUT put I positive signal output of IQ quadrature

29 VCONT Input V oltage of AGC

30 GNDDIV Gnd GND of DIV ider block Ground of divider to make IF local signals
31 VCCDIV Vcc VCC of DIV ider block Power supply of divider to make IF local signals
32 AGCOUTB Output AGC OUT put B ar AGC negative signal output to be fed to IQ

33 AGCOUT Output AGC OUT put AGC positive signal output to be fed to IQ

34 VCCAGC Vcc VCC of AGC block Power supply of AGC
35 GNDAGC Gnd GND of AGC block Ground of AGC
36 MIX2OB Output MIX2 O utput B ar 2nd mixer (MIX2) negative signal output to be fed

37 MIX2O Output MIX2 O utput 2nd mixer (MIX2) positive signal output to be fed to

38 IFINB Input 1st IF signal IN put B ar IFAMP negative signal input for 1st IF signal
39 IFIN Input 1st IF signal IN put IFAMP positive signal input for 1st IF signal
40 GNDIF Gnd GND of IF MIX2 block Ground of IFAMP and 2nd mixer (MIX2)
41 VCCIF Vcc VCC of IF MIX2 block Power supply of IFAMP and 2nd mixer (MIX2)
42 MIX1OUT Output MIX1 O utput 1st mixer (MIX1) positive signal output
43 MIX1OUTB Output MIX1 O utput B ar 1st mixer (MIX1) negative signal output
44 RFLOIN Input RF LO cal signal IN put RF 1st local signal input to be fed to 1st mixer

45 VCCMIX1 Vcc VCC of MIX1 block Power supply of 1st mixer (MIX1)
46 GNDMIX1 Gnd GND of MIX1 block Ground of 1st mixer (MIX1)
47 MIX1INB Input MIX1 I nput B ar 1st mixer (MIX1) negative signal input
48 MIX1IN Input MIX1 I nput 1st mixer (MIX1) positive signal input

Input/
Output Meaning of symbol Function

demodulator

demodulator

demodulator

demodulator
The DC voltage input to control the power gain of

CONT rol

AGC

quadrature demodulator

quadrature demodulator

to AGC

AGC

(MIX1) and the down converter of offset PLL

5

HD155101BF

Block Diagram

225 MHz

MIX2OB

45 MHz

MIX2O

IFINB

IFIN

GNDIF

VCCIF

MIX1OUT

MIX1OUTB

1172 MHz

RFLOIN

VCCMIX1

GNDMIX1

36

Vref

Vref

GNDAGC

VCCAGC

35

)
Mix2

(

(IF)

*2

Vref

(Mix1)

45 MHz

AGOUT

34

33

270 MHz

1172 MHz

VCCDIV

AGCOUTB

32

31

Linearizer

45 MHz

)
AGC

Vref

(

Bias generator

*2

1172 MHz

GNDDIV

30

)

Vref

Div, Rx

(

÷2÷2

÷3

÷2

÷2

(90 deg)

)

Vref

Div, Tx

(

÷2(90 deg)

100 kHz
to

VCONT

IOUT 0 to 100 kHz

29

IOUTB 0

28

÷2, ÷12

(90 deg)

)

Vref

Demod

(

270 MHz

)
Mod

Vref

(

270 MHz

27

100 kHz

100 kHz

to

to

QOUT 0

QOUTB 0

26

IFVCO

Bias

Circuit

540 MHz

25

23

IFVCOI

IFVCOO

GNDIQ

IFLO

VCCIQ

MOD

MODB

Vtune

IFLO

To Synth.

0 to 100 kHz IIN

0 to 100 kHz IINB

0 to 100 kHz QIN

Notes: 1. H = Active, L = Off

0 to 100 kHz QINB

All biases are H active

When Bias generator is off, all circuits will be off.

2. When POONRX1 = ‘H’ and POONRX2 = ‘L’, bias generator will be off.

Vref

LNA

Bias

1

2

*1

POONRX2

POONRX1

(LNA)

Circuit

RFOUT

3

4

VCCLNA

GNDLNA

Vref

(PLL)

5

6

7

902 MHz

8

RFIN

GNDPLL

VCCPLL

POONTX

9

Phase

10

VCOIN

detector

11

12

PLLOUT

VCCCOMP

ICURAD

13 14 15 16 17 18 19 20 21 22 24

947 MHz

947 MHz

MIX1INB

48 47 46 45 44 43 42 41 40 39 38 37

MIX1IN

*1

*1

902 MHz

947 MHz

Tx.VCO

6

Configuration

HD155101BF

B.B.

I

Q

Block

I

Q

I & Q

AGC

LC

45 MHz

IF

SAW

225 MHz

RF

SAW

Demo.

filter

filter

filter

90 deg

45 MHz

270 MHz

÷2

Shift

HD155101BF

÷2

IFVCO

RF VCO

Dual

1150 to

1185 MHz

÷6

PLL2PLL1

synth.

Shift

90 deg

540 MHz

÷2

270 MHz

270 MHz

270 MHz

Mod

I & Q

Phase

Detector

filter

Loop

880 to

buffer

915 MHz

bias

RF

circuit

filter

LNA

925 to 960 MHz

TCXO

13 MHz

HD155017T

HPA Module

LPF

7

HD155101BF

A GSM Application Example

225 MHz

947 MHz

45 MHz

MIX2O

IFINB

IFIN

GNDIF

VCCIF

1172 MHz

RFLOIN

VCCMIX1

GNDMIX1

MIX1INB

MIX1IN

947 MHz

MIX2OB

36

38

39 37

40

41

42

MIX1OUT

MIX1OUTB

44

48 47 46 45 43

1

POONRX1

DAC

10 bit

GNDAGC

VCCAGC

35

Vref

(Mix2)
(IF)

Vref

Vref

(Mix1)

Vref

(LNA)

LNA

Bias

Circuit

2

RFOUT

POONRX2

DAC

10 bit

45 MHz

AGOUT

34

270 MHz

1172 MHz

3

VCCLNA

Base Band

System

Controller

Base Band

ADC

12 bit

AGCOUTB

33

32

45 MHz

Vref

(AGC)

*2

Bias generator

4

5

GNDLNA

&

Physical

Layer

Interface

Processing

VCCDIV

31

Linearizer

1172 MHz

Vref

6

RFIN

947 MHz

Processor

DAC

10 bit

GNDDIV

30

Vref

÷2÷2
÷3

÷2

(90 deg)

Vref

(Div, Tx)

÷2(90 deg)

(PLL)

7

POONTX

ADC

12 bit

VCONT

29

÷2, ÷12

(Div, Rx)

÷2

(90 deg)

270 MHz

8

VCCPLL

DAC

IOUT

28

Vref

(Demod)

270 MHz

Vref

902 MHz

9

GNDPLL

PA

10 bit

IOUTB

27

(Mod)

10

VCOIN

ALC

13 MHz

QOUT

QOUTB

26

540 MHz

Phase

detector

11

PLLOUT

VCCCOMP

902 MHz

Tx.VCO

Dual PLL synth.

VHF(IF)

PLL Synth.

UHF(RF)

PLL Synth.

25

12

IFVCOI

IFVCOO

GNDIQ

IFLO

VCCIQ

MOD

MODB

IIN

IINB

QIN

QINB

ICURAD

13 14 15 16 17 18 19 20 21 22 23 24

8

HD155101BF

Functional Operation

The HD155101BF has been designed from system stand point and incorporated a large number of the
circuit blocks necessary in the design of a digital cellular handset.

Receiver Operation

The HD155101BF incorporates a LNA bias circuit for an external RF transistor, whose NF and power gain
can be better selected.

This circuit amplifies the RF signal after selection by the antenna filter before the signal enters the first
mixer section. The RF signal is combined with a high side local oscillator (LO) signal to generate a wanted
first IF signal in the 130 to 300 MHz range. The 1st mixer circuit uses a double-balanced Gilbert cell
architecture, which has open collector differential outputs. If, at 225 MHz, a 800 Ω LC load is connected
to the mixer’s outputs then a SSB NF of 9.0 dB with a gain of 7.0 dB is realizable. The corresponding
input compression point is –11 dBm, which allows the device to be used within a GSM and EGSM system.

A filter is used after the 1st mixer to provide image rejection and the conditioned signal is then passed
through an intermediate amplifier, before being down converted to a second IF in the range of 26 to 60
MHz.

The second mixer can generate a 45 MHz 2nd IF, if a 270 MHz 2nd LO signal is used. The 2nd LO is
obtained by dividing the IFLO signal by 2. The 2nd mixer also uses the Gilbert cell architecture, but with
internal resistive differential outputs of 300 Ω. IF amplifier and second mixer has a SSB NF of 5.6 dB, a
power gain of 12 dB and an input compression point of –25 dBm. In order to improve the blocking
characteristics of the device an external LC resonator across the differential outputs of the second mixer is
recommended.

The signal is then passed to the AGC circuit, which has a dynamic range of more than 80 dB (–42 dB to
+55 dB Typ) and is controlled by a DC voltage, which is generated by the microprocessor. This DC
control range is from 0.15 V to 2.3 V. The AGC, which is designed for the GSM system, provides a
linearity of ±1.0 dB in any 20 dB window. The outputs of the AGC are 2 kΩ differential and are connected
the external supply via inductors.

The signal is then down converted by a demodulator to I and Q. Internal divider circuits convert the IFLO
signal to the same frequency as the 2nd IF before passing this local signal through a phase splitter / shifter
in order to generate the in phase and quadrature IQ components. The phase accuracy of the IQ
demodulator is < ±1° and the amplitude mismatch is < ±0.5 dB. In order to accommodate different
baseband interfaces the HD155101BF IQ differential outputs have a voltage swing of 2.4 Vp-p and a DC
offset of < ±60 mV. Within each output stage a 2nd order Butterworth filter (fc = 210 kHz), is used to
improve the blocking performance of the device.

In order to allow flexibility in circuit implementation the HD155101BF can configured to use either a
single-ended or balanced external circuitry and components.

9

HD155101BF

LNA

Vref

LNA

bias

circuit

Pinput

Poutput

RFOUT

3

VCCLNA

4Vcc

GNDLNA

5

RFIN

6

Figure 1 LNA Bias Circuit

Transmitter Operation

The transmitter chain converts differential IQ baseband signals to a suitable format for transmission by a
power amplifier.

The common mode DC voltage range of the modulator inputs is 0.8 to 1.2 V and they have 2.4 Vp-p Max
differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The LO
signals are generated by dividing the IFLO signal by 2 and then passing them through a phase splitter /
shifter. The IF signals generated are then summed and produce a single modulated IF signal which is
amplified and fed into the offset PLL block. Carrier suppression due to the mixer circuit is better than 31
dBc. However, if the common mode DC voltage of the I and Q inputs is adjusted, carrier suppression can
be improved better than 40 dBc easily. In addition, upper side-band suppression is better than 35 dBc.

Within the offset PLL block there is a down converter, a phase comparator and a VCO driver. The down
converter mixes the 1st LO signal and the TX VCO to create a reference LO signal for use in the offset
PLL circuit. The phase comparator and the VCO driver generate an error current, which is proportional to
the phase difference between the reference IF and the modulated IF signals. This current is used in a 2nd
order loop filter to generate a voltage, which in turn modulates the TX VCO. In order to optimize the PLL
loop gain, the error current value can be modified by changing the value of an external resistor - ICURAD.
In order to accommodate a range of TX VCO, the offset PLL circuit has been designed to operate with a
supply voltage of up to 5.25 V.

Operating Modes

The HD155101BF has the necessary control circuitry to implement the necessary states within the GSM
system. Also provided is a power save mode which reduces the current consumption of the device by
powering down unnecessary function blocks. Three pins are assigned for mode control, POONRX1,
POONRX2 and POONTX. Table 1 shows the relationship between the pins and the required operating
mode. Control of these pins are by the system controller.

As per GSM requirements the TX and RX sections are not on at the same time. For the receiver there is a
calibration mode for which the LNA bias circuit and 1st mixer are switched off. During this period the
gain of the AGC can be adjusted. Also the DC offsets of the IQ demodulator are measured and
subsequently canceled.

In order to change between the RX and TX modes a state called “warm-up” is used to ensure that the LO
signals are not unduly affected. This method of switching between TX and RX ensures that lock is
achieved first time.

10

HD155101BF

Power saving is implemented through use of the idle mode. All function blocks of the HD155101BF are
switched off until such time as the system controller commends the device to power up again.

Table 1 Operating Modes with Power Saving

Receive
(Rx)

Calibrate
(Cal)

Warm-up
(Lo-ON)

Transmit
(Tx)

Idle
(PS)

Mode POONRX1 (pin 1) H L L L H
switch POONRX2 (pin 2) H H L L L

POONTX (pin 7) L L L H Don’t care
HD155101BF LNA bias ON OFF OFF OFF OFF
circuit status 1st mixer ON OFF OFF OFF OFF

IF AMP ON ON OFF OFF OFF

2nd mixer ON ON OFF OFF OFF

AGC ON ON OFF OFF OFF

IO demodulator ON ON OFF OFF OFF

Divider (Rx.) ON ON OFF OFF OFF

Divider (Tx.) OFF OFF OFF ON OFF

IO modulator OFF OFF OFF ON OFF

Offset PLL OFF OFF OFF ON OFF

RF 1st local buffer ON ON ON ON OFF

IF local buffer ON ON ON ON OFF

IFVCO ON ON ON ON OFF

Total current 42.5 mA Typ 32 mA Typ 10.5 mA Typ 38 mA Typ 1 µA Typ

The slots of
GSM system

Operating modes
of the HD155101BF

POONRX1(pin 1)
POONRX2(pin 2)

POONTX (pin 7)
Power Amplifier ON
UHF PLL synth. ON

UHF PLL synth. load
VCO control voltage

of UHF PLL synth.

4.615ms

7012345670123456701

Rx RxTx Tx

Cal Cal Cal Cal

Rx Rx Rx Rx

Tx Tx

Lo-ON Lo-ON

Mon Mon

Lo­ON

Lo­ON

4.615ms

Lo-

ON

Lo­ON

Idle(PS) mode don’t care

Figure 2 Control Diagram for Operating Mode Selection

PS

11

HD155101BF

IFVCO Operation

The HD155101BF incorporates an IFVCO circuit. The IFVCO circuit consists of an IFVCO transistor and
a bias circuit for it, whose current are 2.0 mA and 0.5 mA respectively. If an internal IFVCO is used, treat
pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) as shown figure 3-(a).

Using an external IFVCO, pin 23 (IFVCOO) and pin 24 (IFVCOI) cannot be connected any pattern and
component, and any component to feed direct current must be also removed from pin 21 (IFLO).

If pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) are treated as shown figure 3-(b), current
consumption will decrease 2.0 mA.

IFVCO
bias circuit

23

21 24

IFLO

IFVCOO

Vcc

(a) using an internal IFVCO (b) using an external IFVCO

HD155101BF

IFVCOI

Vtune

IFLO

PLL
synth.

23

21 24

IFLO

IFVCOO
External

IFVCO

Figure 3 Control Diagram for Operating Mode Selection

IFVCO
bias circuit

HD155101BF

IFVCOI

Vtune

IFLO

PLL
synth.

12

HD155101BF

Absolute Maximum Ratings

Any stresses in excess of the absolute maximum ratings can cause permanent damage to the HD155101BF.

Item Symbol Rating Unit

Power supply voltage (VCC) VCC –0.3 to +4.0 V
Power supply voltage (VCCCOMP) VCCCOMP VCC to +5.5 V
Pin voltage V
Maximum power dissipation P
Operating temperature Topr –20 to +85 °C
Storage temperature Tstg –55 to +125 °C

T

T

–0.3 to VCC + 0.3 (6.0 Max) V
400 mW

13

HD155101BF

Oco

C

C

Electrical Characteristics (Ta = 25°C)

Specifications

Item Symbol Min Typ Max Unit Test Conditions

Power supply voltage (1) V

Power supply voltage (2) V
Power supply current (Rx.) I

Power supply current (Tx.) I

Power supply current

CC

CCCOMP

CC(Rx.)

CC(Tx.)

I

CC(Lo-ON)

(Lo-ON)
Power saving mode supply

I

CC(PS)

current
Power up time (Rx.) t up

Power up time (Tx.) t up

Power on control voltage
range (Rx1, Rx2, Tx)

Vthon
Vthon
Vthon

Power off control voltage
range (RX1, Rx2, Tx)

Vthoff
Vthoff
Vthoff

I/Q common-mode output
voltage

I/Q differential output swing V

I/Q output offset voltage V

I/Q common-mode input
voltage

I/Q differential input swing V

V

I

V

QOcom

IOsw

V

QOsw

IOoffset

V

QOoffset

V

IIcom

V

QIcom

IIsw

V

QIsw

Note: ( ) : These data are actual spread, not guaranteed.

2.7 3.0 3.6 V 4, 8, 20, 31,

2.7 3.0 5.25 V 11
— 42.5 60.0 mA VCC = 3.0V

V

= 3.0V

CCCOMP

— 38.0 55.0 mA VCC = 3.0V

V

= 3.0V

CCCOMP

— 10.5 15.0 mA VCC = 3.0V

V

= 3.0V

CCCOMP

— 1.0 10.0 µAVCC = 3.0V

V

= 3.0V

CCCOMP

— 1.5 (5.0) µsec VCC = 3.0V

(Rx.)

— 0.2 (0.5) µsec VCC = 3.0V

(Tx.)

2.3 — — V VCC = 3.0V 1

RX1
RX2
TX

— — 0.8 V VCC = 3.0V 1

RX1
RX2
TX

/

1.1 1.3 1.5 V VCC = 3.0V 25, 26

m

/

2.4 3.0 — Vp-p VCC = 3.0V

/

–60 0 +60 mV VCC = 3.0V

/

(0.8) 1.0 (1.2) V VCC = 3.0V 14, 15

/

— 2.0 (2.4) Vp-p VCC = 3.0V

V

CCCOMP

V

CCCOMP

V

IOUT

V

QOUT

V

IOUTD

V

QOUTDC

V

IIN

V

QIN

– V

– V

– V

= 3.0V

= 3.0V

– V

– V

– V

IINB

QINB

IOUTB

QOUTB

IOUTBD

QOUTBDC

Applicable
pins Note

34, 41, 45

4, 8, 20, 31,
34, 41, 45, 11

4, 8, 20, 31,
34, 41, 45, 11

4, 8, 20, 31,
34, 41, 45, 11

4, 8, 20, 31,
34, 41, 45, 11

from PS
mode

from PS
mode

2
7

2
7

27, 28
25, 26

27, 28

25, 26
27, 28

16, 17
14, 15

16, 17

14

HD155101BF

Block Specifications

• Specifications of LNA

Item Min Typ Max Unit Test Conditions

Frequency (RF) 925 940 960 MHz
Power gain — 18.0 — dB RF = 940MHz , Pin = –50dBm
Noise figure — 1.75 — dB RF = 940MHz
i/p IP3 — –1.0 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz
o/p IP3 — 16 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz
i/p CP — –11.5 — dBm RF = 940MHz
o/p CP — 5.5 — dBm RF = 940MHz
Load Z — 50 — Ω 50Ω Typ
i/p Z — 50 — Ω 50Ω Typ
i/p VSWR — 1.5 — RF = 940MHz, 50Ω
o/p VSWR — 1.5 — RF = 940MHz, 50Ω
ICC @LNA Trs. 4.7 5.6 6.8 mA Only Trs. current

Note: These AC characteristics are shown for reference only and do not form part of the HD155101BF

component specification.

• Specifications of Mixer 1 (Output Load = 400Ω + 400Ω balanced)

Item Min Typ Max Unit Test Conditions

Frequency (RF) 925 940 960 MHz
Frequency (LO) 1055 1165 1260 MHz
Frequency (IF) (130) 225 (300) MHz
Conversion gain 4.5 7.0 9.0 dB RF = 940MHz/Pin = –50dBm,

LO = 1165MHz/Pin = –10dBm, IF = 225MHz

Noise figure (6.0) 9.0 (12.0) dB RF = 940MHz,

LO = 1165MHz/Pin = –10dBm, IF = 225MHz

i/p IP3 — –1.0 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz,

LO = 1165MHz/Pin = –10dBm

o/p IP3 — 6.0 — dBm RF1 = 940.8MHz, RF2 = 941.6MHz,

LO = 1165MHz/Pin = –10dBm

i/p CP –13.5 –11.0 (–8.0) dBm RF = 940MHz,

LO = 1165MHz/Pin = –10dBm, IF = 225MHz

o/p CP (–9.5) –5.0 (–0.5) dBm RF = 940MHz,

LO = 1165MHz/Pin = –10dBm, IF = 225MHz
RF i/p VSWR — 1.5 (2.0) RF = 940MHz, 50Ω
LO i/p VSWR — 1.5 (2.0) RF = 1165MHz, 50Ω
IF o/p VSWR — 1.5 (2.0) RF = 225MHz, 800Ω (400Ω + 400Ω Balanced)

Note: ( ) : These data are actual spread, not guaranteed.

15

HD155101BF

• Specifications of IFAmp + Mixer 2

Item Min Typ Max Unit Test Conditions

Input frequency (IF1) (130) 225 (300) MHz
Frequency (LO2) (156) 270 (360) MHz LO2 = IFLO/2
Output frequency (IF2) (26) 45 (60) MHz
Conversion gain 9.0 12.0 14.5 dB IF1 = 225MHz/Pin = –40dBm,

IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz

Noise figure (4.5) 5.6 (7.0) dB IF1 = 225MHz,

IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz

i/p IP3 — –16.0 — dBm IF11 = 225.8MHz, IF2 = 226.6MHz,

IFLO = 540MHz/Pin = –10dBm

o/p IP3 — –4.0 — dBm IF11 = 225.8MHz, IF2 = 226.6MHz,

IFLO = 540MHz/Pin = –10dBm

i/p CP –27.5 –25.0 (–23.0) dBm IF1 = 225MHz,

IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz

o/p CP (–18.0) –14.0 (–11.0) dBm IF1 = 225MHz,

IFLO = 540MHz/Pin = –10dBm, IF2 = 45MHz

Isolation (55) 60 — dB Between mixer 1 outputs and IFAmp inputs
Note: ( ) : These data are actual spread, not guaranteed.

• Specifications of AGC

Item Min Typ Max Unit Test Conditions

Input frequency (26) 45 (60) MHz
Control voltage range 0.15 — 2.3 V
Gain range 89 98 107 dB Gain 1 – Gain 3
Gain linearity (–1.0) — (1.0) dB in any 20dB window
Gain 1 45 55 65 dB Vcont = 2.3V
Gain 2 13 23 33 dB Vcont = 1.5V
Gain 3 –55 –40 –35 dB Vcont = 0.15V
i/p CP 1 (–64) –59 — dBm Gain = 50dB
i/p CP 2 (–34) –29 — dBm Gain = 10dB
i/p CP 3 (–22) –17 — dBm Gain = –30dB

Note: ( ) : These data are actual spread, not guaranteed.

16

HD155101BF

• Specifications of IQ Demodulator

Item Min Typ Max Unit Test Conditions

Power gain –0.5 1.4 3.5 dB IF2 = 45MHz, Pin = –25dBm, Rout = 10kΩ,

IFLO = 540MHz, Pin = –10dBm

i/p CP (–17.5) –16.0 (–14.0) dBm IF2 = 45MHz, Baseband = 67.7kHz,

IFLO = 540MHz, Pin = –10dBm

o/p CP (–19.0) –15.6 (–12.0) dBm IF2 = 45MHz, Baseband = 67.7kHz,

IFLO = 540MHz, Pin = –10dBm
IQ phase accuracy –1.0 0 1.0 deg. Baseband = 67.7kHz
IQ amplitude mismatch (–0.5) 0.1 (0.5) dB Baseband = 67.7kHz
Output DC offset voltage –60 0 60 mV |IOUT – IOUTB| and |QOUT – QOUTB|
IQ differential output

swing
I/Q common mode

output voltage
Note: ( ) : These data are actual spread, not guaranteed.

2.4 3.0 — Vp-p Baseband = 67.7kHz
|IOUT – IOUTB| and |QOUT – QOUTB|

1.1 1.3 1.5 V VCC = 3.0V

17

HD155101BF

• Specifications of IQ Modulator and Offset PLL

(RFLO and IFLO signals are supplied by Signal Generator)

Item Min Typ Max Unit Test Conditions (Loop bandwidth = 1.4MHz)
Frequency (RF) 880 902 915 MHz
Frequency (LO) 1055 1172 1260 MHz
Frequency (IF) (120) 135 (180) MHz
Power up time — 0.3 (0.5) µsec from PS mode
Lock up time — 20 (80) µsec from PS mode to 915MHz
Carrier suppression ratio 31 40 — dBc All ‘1’ GMSK (Baseband = 67.7kHz)
Upper side-band

suppression ratio
Phase accuracy — 0.94 (2.5) deg. rms 200kHz Bandwidth
(PN9, GMSK) — 2.27 (6.0) deg. peak 200kHz Bandwidth
Modulation spurious — –36.5 (–33.0) dBc 200kHz offset / 30kHz Bandwidth
(PN9, GMSK) — –70.0 (–63.0) dBc 400kHz offset / 30kHz Bandwidth

Tx noise in RX band — –157 (–151) dBc/Hz 925MHz to 935MHz (10MHz up from Tx band)
(Tx power = 0dBc = 30dBm) — –165 (–163) dBc/Hz 935MHz to 960MHz (20MHz up from Tx band)
Isolation of the 1st local

input to TXVCO input
IQ differential input swing — 2.0 (2.4) Vp-p |IIN – IINB| and |QIN – QINB|
I/Q common mode input

voltage

Note: ( ) : These data are actual spread, not guaranteed.

35 45 — dBc I/Q differential input swing = 2.0Vp-p

I/Q common mode input voltage = 1.0V

— –74.0 (–63.0) dBc 600kHz to 1.8MHz offset / 30kHz Bandwidth
— –77.0 (–66.0) dBc 1.8MHz to 3MHz offset / 100kHz Bandwidth
— –80.5 (–68.0) dBc 3MHz to 6MHz offset / 100kHz Bandwidth
— –82.0 (–74.0) dBc 6MHz upwards offset / 100kHz Bandwidth

(40) 43 — dB

(0.8) 1.0 (1.2) V

18

Test Circuit

HD155101BF

R701

SMA

J702 (MIX2RF)

C805

SMA

J801 (MIX1IF)

C807

VCCJ803 (MIX1RF)

SMA

J802 (MIX1LO)

SMA

0

1000p

5

4

1000p

T801

617PT-1206

16

1

2

2

34

3

C808

C809

C811

2.5p

C813

4p

C706

C803

100p

1000p

7p

1000p

L802

L801

3.3n

J701 (MIX2IF/AGCIN)

SMA

C703

C704

3300p

4

T701

34216

321

617DB-1018

C701

C702

1000p

6p

C705

100n

L701

3p

100n

C801

C810

1000p

3p

C812

10n

L803

5

VCC

J601 (AGCOUT)

SMA

C610

3300p

C608

C609

3300p

3300p

4

5

T601

34216

321

617DB-1018

1000p

3635343332313029282726

MIX2OB

MIX2O

VCCAGC

GNDAGC

37

IFINB

38

IFIN

39

GNDIF

40

VCCIF

41

MIX1OUT

42

MIX1OUTB

43

RFLOIN

44

VCCMIX1

45

GNDMIX1

46

MIX1INB

47

MIX1IN

48

POONRX1

POONRX2

RFOUT

123456789

C202

10p

10n

L201

Q201

BPF420

C203

27p

VCC

C606

3300p

C607

3300p

VCCDIV

AGCOUT

AGCOUTB

IC001

HD155101BF

VCCLNA

GNDLNA

RFIN

C205

10p

4.7k

R201

C206

0.5p

10n

L202

C207

0.5p

VCONT

47p

VCONT

GNDDIV

POONTX

VCCPLL

IOUT

IOUT

GNDPLL

C301

47p

IOUTB

QOUT

QOUT

IOUTB

VCOIN

VCCCOMP

101112

QOUTB

25

QOUTB

PLLOUT

C302

120p

C601

1000p

IFVCOI
IFVCOO
GNDIQ
IFLO
VCCIQ
MOD
MODB
IIN
IINB
QIN
QINB
CURAD

VTUNE

C508

2.7k

R502

C507

L502

HVU355

VARICAP1

C506

6p

C505

C503

24
23
22
21
20
19
18
17
16
15
14
13

8.2k

R307

VCC

C909

C908

C907

1000p

8p

8.2n

3p

6p

C303

VCCCOMP

100000n

C906

100n

C905

27p

C904

C504

3p

100

R501

C304

R304

R301

100p

VCCVCOEXT

100000n

C903

100n

C902

27p

C901

L501

0.75p

18

R303

0

R302

100000n

100n

27p

C502

1000p

15n

8p

C405

0

VCO1

0

C305

VTUNE
POONRX1

POONRX2

POONTX
QINB
QIN
IINB

IIN
VCONT

QOUTB

QOUT
IOUT
IOUTB

120p

C501

C406

1000p

18n

L402

18n

L401

1000p

R305

321

OUT VCC

456

Kv=11MHz/V

MQE601-902

MQE502-902 or

GND

26

VCC

25

VCCCOMP

24

POONRX

23

VCCVCOEXT

22

SLEEP

21

VTUNE

20

POONRX1

19

GND

18

POONRX2

17

GND

16

POONTX

15

QINB

14

QIN

13

IINB

12

GND

11

GND

10

IIN

9

VCONT

8

GND

7

QOUTB

6

GND

5

GND

4

QOUT

3

IOUT

2

IOUTB

1

SMA

J501 (IFLO)

VCC

IIN

IINB

QIN

QINB

C308

3300p

R306

130

C307

220p

220

GND GND

MOD CON

POONTX

POONRX1

POONRX2

3p

C201

SMA

VCC

J201 (LNAOUT)

C204

1000p

SMA

J202 (LNAIN)

VCC

VCCCOMP

SMA

J301 (VCOOUT)

VCCVCOEXT

19

HD155101BF

Measurement Results

LNA Measurement Results (for reference only)

Conditions:

Vcc = 3.0 V
POONRX1 (pin 1) = 3.0 V
POONRX2 (pin 2) = 3.0 V
POONTX (pin 7) = 0 V

50 Ω

Output(RF)

1000 p

Input(RF)
940 MHz,

−50 dBm

50 Ω

20

15

Vcc=3.0V

10

Pin=−50dBm

5

3.0 V
1000 p

132 4 8 11 20 31 34 41 45

10 p

Rbias

100

Ic

6

5 7 9 22 30 35 40 46

TRS:
Siemens BFP420

3 p

10 n

10 n

0.5 p0.5 p

4.7 k

10 p

Figure 4 Evaluation Circuit for LNA

Vbias

0.56 V

Gain [dB]
ICP [dBm]

NF [dB]

Active bias circuit

HD155101BF

3.5

3

2.5

2

20

0

−5

Gain [dB], ICP [dBm]

−10

−15

880 900 920 940 960 980 1000 1020

Frequency [MHz]

Figure 5 Gain, NF, ICP vs. Frequency

1.5

1

0.5

0

NF [dB]

HD155101BF

40

Vcc=3.0V

20

Freq.=940MHz

0

−20

−40

Pout [dBm]

Interfere(1)=940.8MHz

−60

Interfere(2)=941.6MHz

−80

−100

−120

−60 −50 −40 −30 −20 −10 0 10

Pin [dBm]

Pout [dBm]
IM3 [dBm]

Gain [dB]

Figure 6 Gain, Pout vs. Pin

20

Freq.=940MHz

19.5
Pin=-50dBm

19

20

19

18

17

16

15

14
13

12

Gain [dB]

18.5

18

17.5

Gain [dB]

17

16.5

16

15.5

15

2 2.5 3 3.5 4 4.5

Vcc [V]

Figure 7 Gain vs. Supply Voltage

−40

−20

27
80

100

21

HD155101BF

NF [dB]

3

Freq.=940MHz

2.5

2

1.5

1

0.5

0

2 2.5 3 3.5 4 4.5

Vcc [V]

−40

−20

27
80

100

Figure 8 NF vs. Supply Voltage

−7
Freq.=940MHz

−8

−9

−10

−11

−12

ICP [dBm]

−13

−14

−15

−16

−17

2 2.5 3 3.5 4 4.5

Vcc [V]

Figure 9 ICP vs. Supply Voltage

−40

−20

27
80

100

22

HD155101BF

8

7.5
7

6.5
6

5.5

Icc@TRS [mA]

5

4.5
4

2 2.5 3 3.5 4 4.5

Vcc [V]

Figure 10 LNA Transistor Current vs. Supply Voltage

−40

−20

27
80

100

23

HD155101BF

1st Mixer Measurement Results

Conditions:

Vcc = 3.0 V
POONRX1 (pin 1) = 3.0 V
POONRX2 (pin 2) = 3.0 V
POONTX (pin 7) = 0 V

1165 MHz, −10 dBm

Input (LO)

Input (RF)

940 MHz, −50 dBm

50 Ω

50 Ω

10

5

0

Load: 400 ohm Balanced
TOKO: 617PT-1206
800 Ω: 50 Ω
Insertion loss: 1.5 dB@225 MHz

Gilbert
Cell Mix

2.5 p

4 p

3.0 V
1000 p

1000 p

3.3 n

10 n

3 p

1

2 4 8 11 20 31 34 41 45

Lo Buff2

44

Lo Buff

47

48

5 7 9 22 30 35 40 46

Figure 11 Evaluation Circuit for 1st Mixer

C.G. [dB]
ICP [dBm]

NF SSB [dB]

Vcc=3.0V
Pin=−50dBm
Pin(LO)=−10dBm
Freq.IF=225MHz

43

42

Vcc

100 n

3 p

Output (IF)

1000 p

1000 p

225 MHz

50 Ω

16

14

12

24

−5

C.G. [dB], ICP [dBm]

−10

−15

880 900 920 940 960 980 1000 1020

Frequency [MHz]

Figure 12 Gain, NF, ICP vs. Frequency

10

8

6

NF SSB [dB]

HD155101BF

10

Pout[dBm]

0

−10

−20

Pout [dBm]

−30

−40

−50

−60 −50 −40 −30 −20 −10 0 10

C.Gain[dB]

Vcc=3.0V
Freq.RF=940MHz
Freq.LO=1165MHz
Pin(LO)=−10dBm
Freq.IF=225MHz

Pin[dBm]

Figure 13 Input-Output Characteristics

10

20

15

10

5

C.Gain [dB]

0

−5

−10

25

5

NF SSB[dB]

0

−5

C.Gain [dB]

Freq.RF=940MHz

−10

−15

−60 −50 −40 −30 −20 −10 0 10

Freq.LO=1165MHz
Freq.IF=225MHz
Pin(RF)=−50dBm

Plo [dBm]

C.Gain[dB]

Figure 14 CG, NF vs. Local Input Power

20

15

10

5

0

NF SSB [dB]

25

HD155101BF

12

10

C.Gain [dB]

−2

C.Gain[dB]

8

6

4

2

0

150 200 250 300

Vcc=3.0V
Freq.LO=1165MHz
Pin(LO)=−10dBm
Pin(RF)=−50dBm

Frequency [MHz]

Figure 15 Output Frequency Characteristics

10

9
8

7
6
5

4

C.Gain [dB]

3
2

1
0

2 2.5 3 3.5 4 4.5

Vcc [V]

Figure 16 Gain vs. Supply Voltage

−40

−20

27
80
100

26

15

HD155101BF

14
13

12
11
10

9

SSB NF [dB]

8
7

6
5

2 2.5 3 3.5 4 4.5

Vcc [V]

Figure 17 NF(SSB) vs. Supply Voltage

−7

−8

−9

−40

−20

27
80
100

−10

−11

−12

ICP [dBm]

−13

−14

−15

−16

−17

2 2.5 3 3.5 4 4.5

Vcc [V]

Figure 18 ICP vs. Supply Voltage

−40

−20

27
80
100

27

HD155101BF

IF AMP + 2nd Mixer Measurement Results

Conditions:

Vcc = 3.0 V
POONRX1 (pin 1) = 3.0 V
POONRX2 (pin 2) = 3.0 V
POONTX (pin 7) = 0 V

Input (1st IF)

225 MHz, −40 dBm

Input (IFLO)

540 MHz, −10 dBm

50 Ω

50 Ω

20

15

10

3.0 V
1000 p

7 p

0.01 µ

100 n

6 p

1

2 4 8 11 20 31 34 41 45

IF AMP

39

38

21

270 MHz

Divider

1/2

5 7 9 22 30 35 40 46

150

Mixer2

150

300

AGC

37

36

Output test-circuit
for IF AMP + Mixer2
evaluation only

1000 p

1000 p

200 Ω: 50 Ω

TOKO
617DB-1018
Insertion loss = 3.6 dB

Figure 19 Evaluation Circuit for IF AMP + 2nd Mixer

C.Gain
Pout_2IF

1dB

Output (MIX2)

1000 p

1000 p

0

−10

−20

45 MHz

28

5

C.Gain [dB]

0

ICP: −25dBm

−5

−70 −60 −50 −40 −30 −20 −10 0 10

Pin_RF [dBm]

Figure 20 Input-Output Characteristics, 1dB-Compression Point

−30
Pout_2IF [dBm]

−40

−50

20.0

HD155101BF

0.0

−20.0

−40.0

Pout [dBm]

−60.0

−80.0

−100.0

−60 −50 −40 −30 −20 −10 0

IP3out: −4.0dBm

Pout_IM3
Pout_2IF

IF11=225.8MHz
IF12=226.6MHz

IP3in: −16.0dBm

Pin_RF [dBm]

Figure 21 Intermodulation 3rd Characteristics

20

10

0

−10

2.5V 27°C

2.7V 27°C

3.0V 27°C

4.0V 27°C

−20

C.Gain [dB]

−30

−40

−50

−50 −40 −30 −20 −10 0 10

Local in [dBm]

IF1=225MHz/Pin=−30dBm,
IFLO=540MHz,IF2=45MHz

Figure 22 C.Gain vs. Local in Power

29

HD155101BF

20

10

0

−10

C.Gain [dB]

−20

−30

2 2.5 3 3.5 4 4.5

C.Gain

Ta=−30°C
Ta=25°C

Ta=80°C

2.7V to 3.6V

NF SSB

Vcc [V]

Figure 23 C.Gain, NF SSB vs. Supply Voltage

−20
Vcc=4.0V

Vcc=3.0V
Vcc=2.7V

25

20

15

10

5

0

NF SSB [dB]

30

−25

IF1=225MHz,

ICP(Input Compresion Point) [dBm]

−30

−40 −20 0 20 40 60 80 100

IFLO=540MHz/Pin=−10dBm, IF2=45MHz

Temperature [deg]

Figure 24 ICP vs. Temperature

AGC Measurement Results

3.0 V
1000 p

45 MHz

50 Ω

1000 p

50 Ω: 200 Ω

1000 p

TOKO
617DB-1018
insertion loss = 3.6 dB

37
36

Figure 25 Evaluation Circuit for the AGC & Power On Control Blocks

1

2 4 8 11 20 31 34 41 45

150

300

POONRX1

POONRX2

control

5 7 9 22 30 35 40 46

Mixer2 output R

150

ATT AGC AMP

LinearizerPower on/off

IQ Demodulator
IF AMP + Mixer2
IF VCO
Divider
LNA & Mixer 1
Transmitter block

2 k

IQ Demo

2 k

33

32

29

HD155101BF

Output test-circuit
for AGC block
evaluation only

Output (MIX2)

200 Ω: 50 Ω

3300 p

Vcont

0.15 to 2.3 V

Conditions:

Vcc = 3.0 V
POONRX1 (pin 1) = 3.0 V
POONRX2 (pin 2) = 3.0 V
POONTX (pin 7) = 0 V

45 MHz

3300 p

3300 p

TOKO
617DB-1018
insertion loss = 6.1 dB

80

60

40

20

Gp [dB]

−20

−40

−60

Ta=−40°C
Ta= 27°C
Ta= 90°C

0

Vcc=3.0V,
Freq=45MHz,
Zin=300Ω

0 0.5 1 1.5 2 2.5

Vcont [V]

Figure 26 Power Gain vs. Vcont Voltage

31

HD155101BF

60

55

50

45

Gp [dB]

40

35

30

60

Ta=−40°C
Ta= 27°C
Ta= 90°C

Vcc=3.0V,
Vcont=2.3V,
Freq=45MHz,
Pin=−100dBm,
Zin=300Ω

10 100

20 50

Frequency [MHz]

Figure 27 Power Gain vs. Frequency

50

VCC=3V, freq.=45MHz

40

30

NF [dB]

20

10

0

−40 −200 20406080

Ta=−40°C
Ta=27°C

Ta=90°C

Gp [dB]

Figure 28 Noise Figure(NF) vs. Power Gain(Gp)

32

10

HD155101BF

0

−10

−20

−30

ICP [dBm]

−40

−50

−60

−70

−40 −200 204060

Gp [dB]

Vcc=3V, freq.=45MHz

Ta=−40°C
Ta=27°C
Ta=90°C

Figure 29 Input Compression Point(ICP) vs. Power Gain(Gp)

60

40

20

Gp [dB]

−20

Ta=−40@Vcont=2.3
Ta=27@Vcont=2.3
Ta=90@Vcont=2.3

0

Ta=−40@Vcont=0.15
Ta=27@Vcont=0.15
Ta=90@Vcont=0.15

Freq=45MHz,
Zin=300Ω

−40

−60

−80

1.5 2 2.5 3 3.5 4 4.5
Vcc [V]

Figure 30 Power Gain(Gp) vs. Supply Voltage(Vcc)

33

HD155101BF

IQ Demodulator Measurement Results

3.0 V
1000 p

1

2 4 8 11 20 31 34 41 45

45 MHz

50 Ω

3300 p

3300 p

Input (IFLO)

540 MHz, −10 dBm

TOKO
617DB-1018

50 Ω: 200 Ω

3300 p

50 Ω

33
32

21

0.01 µ

Figure 31 Evaluation Circuit for the I&Q Demodulator Block

AGC

2 k

divider

÷6

2 k

90 MHz

(90° phase shifter)

5 7 9 22 30 35 40 46

45 MHz

÷2

2nd order
Butterworth filter

2nd order
Butterworth filter

10 k

10 k

Conditions:

Vcc = 3.0 V
POONRX1 (pin 1) = 3.0 V
POONRX2 (pin 2) = 3.0 V
POONTX (pin 7) = 0 V

IOUT

28

IOUTB

27

QOUT

26
25

QOUTB

Single ended 1kΩ input impedance
Single ended 10kΩ load impedance

V

V

10 k

10 k

10 k

10 k

34

HD155101BF

−10

Output[dBm] Vcc=3.0V
Output[dBm] Vcc=2.7V

−15

−20

Output[dBm] Vcc=3.6V

OCP: −15.0dBm

Ta = 25°C

1dB

−25

Gp[dB] Vcc=3.0V

−30

Output [dBm] (Single ended)

Gp[dB] Vcc=2.7V
Gp[dB] Vcc=3.6V

ICP: −15.5dBm

−35

−35 −30 −25 −20 −15 −10 −50

Input [dBm] (Single ended)

Figure 32 Input-Output Characteristics

−10

Output[dBm] Ta=25°C

−15

Output[dBm] Ta=−20°C
Output[dBm] Ta=80°C

30

20

10

0

−10

−20

30

20

Gp [dB]

−20
Vcc = 3V

−25

−30

Output [dBm] (Single ended)

Gp[dB] Ta=25°C
Gp[dB] Ta=−20°C
Gp[dB] Ta=80°C

−35

−35 −30 −25 −20 −15 −10 −50

Input [dBm] (Single ended)

Figure 33 Input-Output Characteristics

10

0

−10

−20

Gp [dB]

35

HD155101BF

f1: 45.8MHz

f2: 46.6MHz

0

OIP3: −0.2dBm

−10

−20

−30

GMSK

modulated signal

(All 1 GMSK)

+

DIV

DEM

(45MHz)

(67.7kHz)

−40

Output [dBm] (Single ended)

−50

−35 −30 −25 −20 −15 −10 −50

Output [dBm]
IM3 [dBm]

IIP3: −2.7dBm

Input [dBm] (Single ended)

Figure 34 Inter Modulation 3rd Characteristics

Rejection
@200k
@400k
@600k
@800k
@1600k
@3000k
@20000k

20

0

−20

−40

spec.(Min)

−0.3dB

−4.0dB

−9.4dB

−14.0dB

−25.9dB

−36.8dB

−50.0dB

fc: 210kHz

Iout

−2.6dB

−11.5dB

−21.3dB

−29.0dB

−43.3dB

−42.2dB

−54.7dB

Qout

−2.4dB

−11.2dB

−21.1dB

−28.7dB

−43.0dB

−42.0dB

−56.1dB

spec.1
spec.2

Iout
Qout

36

Rejection level [dB]

−60

−80

10 100 1000 10

Frequency [kHz]

4

Figure 35 Internal LPF Frequency Characteristics

10

5

0.09[degree] 0.1[dB]

b) I&Q Amplitude Mismatcha) I&Q Phase Accuracy

HD155101BF

1.38[V] 3.00[Vp-p]

c) Common Mode Voltage

d) Differential Output Swing

Figure 36 Demodulator Output Waveforms (67.7 kHz) at Vcc = 3.0 V, Ta = 25°C

37

HD155101BF

Transmitter Measurement Results

Input(LO),−10dBm

1150 to 1185MHz

Spectrum

analyzer

50 Ω

GMSK RF
TX. signal
890 to 915MHz

MURATA MQE502-902
or MQE601-902
Kv=11MHz/V,C3=100pF
loop band width=1.5MHz

50 Ω

1000p

Conditions:

Vcc = 3.0 V
POONRX1 (pin 1) = 0 V
POONRX2 (pin 2) = 0 V
POONTX (pin 7) = 3.0 V

VCO

3300p

5.0V
R3

220

C2

18

ICURAD

R

R2
130

8.2k

51 p3 p

RFLOIN

3.9n

VCOIN

0.75 p

VCCCOMP

1000p

PLLOUT

ICURAD

C1
220p

14

10

11

12

13

3.0 V
1000 p

1 2 4 8 20 31 34 41 45

LO buffer

VCO buffer

on

off

SW1

Power save control

POONTX=H, SW1=Off

5

7 9 22 30 35 40 46 16 17 2115141918

Low pass

I1I3

I2

Charge Pump

(Current mode driver)

Vcc

filter

Phase detector

1st. local signal
1150 to 1185 MHz

Down-converter
(offset mixer)

270 MHz

GMSK modulated IF
270 MHz

Low
pass

filter

MODB

18n

fo=270MHz

I&Q baseband

signal generator

I&Q modulator block

÷2

(90° phase shifter)

QIN

MOD

QINB

8p

18n

Q baseband signal

100 kHz

I baseband signal

100 kHz

IIN

IINB

0.01µ

50Ω

IFLO

Input(IFLO)
540MHz,

−10dBm

Figure 37 Evaluation Circuit for the Upconverter (I&Q Modulator and Offset PLL Block)

5

4

3

2

I1 peak, I2 peak, I3 [mA]

1

0

2 4 6 8 10 20

R

Figure 38 I1 Peak, I2 Peak, I3 vs. R

ICURAD

[kΩ]

Characteristics

ICURAD

I1 peak
I2 peak
I3

30

38

HD155101BF

Phase accuracy and lock up time characteristics depend on the OPLL loop bandwidth. The following table
shows measurement result of each characteristic, when the OPLL loop bandwidth is changed.

Table 2 Measurement Results of Transmitter Characteristics vs. OPLL Loop Bandwidth

Dependence (R

Item Condition1 Condition 2 Condition 3 Condition 4 Condition 5 Unit

VCO & Phase detector VCO: MURATA MQE502-902 or MQE601-902,

Loop bandwidth (measured) 0.8 1.1 1.3 1.5 1.6 MHz
C1 680 390 300 220 180 pF
C2 10.0 6.8 4.7 3.3 2.7 nF
C3 100 100 100 100 100 pF
R2 68 100 110 130 130 Ω
R3 390 330 270 220 200 Ω

Item Spec. Measured1 Measured2 Measured3 Measured4 Measured5 Unit

200 kHz offset ≤ –33 –37.23 –37.09 –37.60 –37.70 –37.86 dBc
400 kHz offset ≤ –63 –67.41 –67.95 –68.49 –68.94 –69.23 dBc
600 kHz to 1.8 MHz offset ≤ –63 –72.86 –72.85 –73.09 –73.48 –73.26 dBc

1.8 MHz to 3 MHz offset ≤ –66 –79.65 –76.96 –76.45 –75.70 –74.96 dBc
3 MHz to 6 MHz offset ≤ –68 –82.11 –81.11 –80.83 –79.18 –79.58 dBc
6 MHz upwards offset ≤ –74 –82.77 –82.67 –82.59 –81.98 –82.38 dBc
Carrier suppression ≥ 31 47.35 48.44 47.54 46.71 48.36 dBc
Side band suppression ≥ 35 39.10 39.47 39.89 39.89 40.33 dBc
Phase accuracy PN9 ≤ 2.5 1.53 1.16 1.02 0.89 0.84 deg. rms

PN9 ≤ 6.0 3.30 2.90 2.81 2.72 2.64 deg. peak
All ‘1’ ≤ 2.5 0.99 0.95 0.93 0.93 0.89 deg. rms

All ‘1’ ≤ 6.0 2.26 2.33 2.33 2.31 2.04 deg. peak
Lock up time ≤ 80 58.1 41.1 29.4 19.1 17.2 µsec
Tx noise in 925 MHz –163.3 –158.6 –157.0 –155.1 –154.9 dBc/Hz
Rx band 935 MHz –166.4 –165.6 –165.4 –164.1 –163.3 dBc/Hz
VCO noise only 925 MHz –165.2 (0 dBc = –0.5 dBm, noise –165.7 dBm/Hz) dBc/Hz

935 MHz –166.4 (0 dBc = –0.5 dBm, noise –166.9 dBm/Hz) dBc/Hz

= 8.2 kΩ, IFLO generated by signal generator)

ICURAD

Conditions

C3 = 100 pF in VCO, R
kvr = 2π × 11 × 106 (rad/Vsec), kdr = ( 2.83 × 10–3) / π (A/rad)

ICURAD

= 8.2 kΩ,

39

HD155101BF

3.0

2.5

2.0

1.5

1.0

Phase accuracy [deg. rms]

0.5

0

0.6 0.8 1.0
OPLL Loop Bandwidth [MHz]

1.2 1.4 1.6 1.8

Figure 39 Phase Accuracy vs. OPLL Loop Bandwidth

Mod: PN9

60

50

40

30

20

Lock Up Time [µsec]

10

0

0.6 0.8

PS mode to 915MHz

1.0 1.2 1.4 1.6 1.8

OPLL Loop Bandwidth [MHz]

Figure 40 Lock Up Time vs. OPLL Loop Bandwidth

40

−150

−155

−160

HD155101BF

925MHz

−165

Tx Noise in Rx Band [dBc/Hz]

−170

0.6 0.8

Figure 41 Tx Noise in Rx Band vs. OPLL Loop Bandwidth

935MHz

1.0 1.2 1.4 1.6 1.8

OPLL Loop Bandwidth [MHz]

41

HD155101BF

Transmitter Measurement Results (1) (R

50Ω

VCO

MURATA

MQE502-902

18

220

VCC

VCCCOMP

Spectrum

Analyzer

VCCVCO

4.7V

Input(LO)

−10dBm
1160 to 1185MHz

+

0.01µ

33µ

3V

+

0.01µ

33µ

5V

50Ω

+

0.01µ33µ

= 8.2 kΩ and IFLO generated by signal generator)

ICURAD

VCC

2.5p 1000p

3.3n

1
2
3
4
5
6
7
8

9
10
11
12

0.75p100p

130
3300p

4847464544434241403938

POONRX1
POONRX2
RFOUT
VCCLNA
GNDLNA
RFIN
POONTX
VCCPLL
GNDPLL
VCOIN
VCCCOMP
PLLOUT

CURAD

1314151617181920212223

R

ICURAD

8.2k

I&Q baseband
Signal Generator

220p

0.01µ

MIX1IN

MIX1INB

VCCMIX1

GNDMIX1

HD155101BF

QINB

QIN

IINB

VCC

00

RFLOIN

IIN

MIX1OUT

MIX1OUTB

MODB

MOD

8p

0.01µ

0.01µ

VCCIF

VCCIQ

18n18n

GNDIF

IFLO

IFIN

GNDIQ

37

IFINB

MIX2O

MIX2OB

GNDAGC

VCCAGC
AGCOUT

AGCOUTB

VCCDIV

GNDDIV

VCONT

QOUTB

IFVCOO

IFVCOI

24

0.01µ

IOUT
IOUTB
QOUT

36
35
34
33
32
31
30
29
28
27
26
25

50Ω

0.01µ
0

0

0.01µ

Input(IFLO)

−10dBm
540MHz

VCC

Figure 42 Evaluation Circuit Using Signal Generator for the I&Q Modulator and Offset PLL

Table 3 Measurement Results Using SG (R

Item Spec. Measured1 Measured2 Measured3 Unit

Measured frequency 890 902 915 MHz
200 kHz offset ≤ –33 –36.36 –36.16 –36.60 dBc
400 kHz offset ≤ –63 –68.22 –67.30 –67.02 dBc
600 kHz to 1.8 MHz offset ≤ –63 –74.84 –74.88 –74.69 dBc

1.8 MHz to 3 MHz offset ≤ –66 –77.48 –77.30 –77.10 dBc
3 MHz to 6 MHz offset ≤ –68 –79.73 –79.47 –79.16 dBc
6 MHz upwards offset ≤ –74 –81.63 –80.67 –80.94 dBc
Carrier suppression ≥ 31 46.24 46.11 45.98 dBc
Side band suppression ≥ 35 38.81 38.86 38.84 dBc
Phase accuracy PN9 ≤ 2.5 1.05 1.05 1.05 deg. rms

PN9 ≤ 6.0 2.76 2.61 2.59 deg. peak
All ‘1’ ≤ 2.5 1.00 1.02 1.01 deg. rms
All ‘1’ ≤ 6.0 2.19 2.33 2.13 deg. peak

= 8.2 kΩ, IFLO generated by signal generator)

ICURAD

42

HD155101BF

a-1. Spectrum1 (890MHz, PN9) a-2. Spectrum2 (890MHz, PN9)

b-1. Spectrum1 (902MHz, PN9) b-2. Spectrum2 (902MHz, PN9)

c-1. Spectrum1 (915MHz, PN9) c-2. Spectrum2 (915MHz, PN9)

Figure 43 GMSK Modulated Transmitter Output Spectrum (890 MHz, 902 MHz, 915 MHz)

43

HD155101BF

T=–40°C 902MHz, PN9 T=–40°C 902MHz, PN9

T=27°C 902MHz, PN9 T=27°C 902MHz, PN9

T=100°C 902MHz, PN9 T=100°C 902MHz, PN9

Figure 44 GMSK Modulated Transmitter Output Spectrum vs. Temperature

44

HD155101BF

The Acquisition response of OPLL using 8.2 kΩ icurad is shown below. The control voltage of the VCO
was observed by the digital storage oscilloscope.

0.5V/div

0.5V/div

12.8µs
5µs/div

a. from PS mode to 902MHz lock b. from PS mode to 915MHz lock

19.95µs

Figure 45 Acquisition Time (Lock Up Time)

5µs/div

45

HD155101BF

Transmitter Measurement Results (2) (R

50Ω

1.5p 18p

18

0.75p100p

220

130
3300p

4.7n

10
11
12

VCC

VCCCOMP

Spectrum

Analyzer

VCCVCO

4.7V

Input(LO)

−10dBm
1160 to 1185MHz

+

0.01µ

33µ

3V

+

0.01µ

33µ

5V

50Ω

VCO

+

0.01µ

33µ

MURATA

MQE502-902

= 8.2 kΩ and IFLO using an internal IFVCO)

ICURAD

VCC

00

0.01µ

4847464544434241403938

MIX1IN

1
2
3
4
5
6
7
8
9

220p

MIX1INB

POONRX1
POONRX2
RFOUT
VCCLNA
GNDLNA
RFIN
POONTX
VCCPLL
GNDPLL
VCOIN
VCCCOMP
PLLOUT

8.2k

VCCMIX1

GNDMIX1

HD155101BF

CURAD

QINB

QIN

IINB

1314151617181920212223

I&Q baseband
Signal Generator

18n

0.01µ

VCC

11p

RFLOIN

IIN

MIX1OUT

MIX1OUTB

MODB

MOD

18n

10 10

0.01µ

VCCIF

VCCIQ

GNDIF

IFLO

100

8.2n

0.01µ

37

IFIN

IFINB

MIX2O
MIX2OB

GNDAGC

VCCAGC
AGCOUT

AGCOUTB

VCCDIV
GNDDIV

VCONT

IOUT

IOUTB

QOUT

QOUTB

GNDIQ

IFVCOO

IFVCOI

27p 6p 0

24
10p

8.2n

27

10p

27p

VCCPLL

36
35
34
33
32
31
30
29
28
27
26
25

HVU355

3V

VCC

0.01µ
0

0

0.01µ

12k

+

Vtune

0

330p

4700p

18k

201918171615141312

LMX2336 (PLL syn)

123456789

0.1µ33µ

100p0.1µ

11

10

Figure 46 Evaluation Circuit Using Internal IFVCO for the I&Q Modulator and Offset PLL

Table 4 Measurement Results Using an Internal IFVCO (R

Item Spec. (GSM Spec.) Measured1 Measured2 Measured3 Unit

Measured frequency 890 902 915 MHz
200 kHz offset ≤ –33 (–30) –35.64 –36.24 –36.93 dBc
400 kHz offset ≤ –63 (–60) –63.63 –64.09 –64.09 dBc
600 kHz to 1.8 MHz offset ≤ –63 (–60) –69.85 –69.95 –70.47 dBc

1.8 MHz to 3 MHz offset ≤ –66 (–63) –76.89 –76.50 –76.04 dBc
3 MHz to 6 MHz offset ≤ –68 (–65) –81.06 –80.67 –80.38 dBc
6 MHz upwards offset ≤ –74 (–71) –82.67 –82.40 –82.34 dBc
Carrier suppression ≥ 31 41.87 42.50 42.42 dBc
Side band suppression ≥ 35 43.59 44.35 43.25 dBc
Phase accuracy PN9 ≤ 2.5 (5) 2.43 2.09 2.01 deg. rms

PN9 ≤ 6.0 (20) 6.56 6.06 6.41 deg. peak
All ‘1’ ≤ 2.5 0.95 0.93 0.96 deg. rms
All ‘1’ ≤ 6.0 2.67 2.67 2.61 deg. peak

ICURAD

= 8.2 kΩ)

46

HD155101BF

a-1. Spectrum1 (890MHz, PN9) a-2. Spectrum2 (890MHz, PN9)

b-1. Spectrum1 (902MHz, PN9) b-2. Spectrum2 (902MHz, PN9)

c-1. Spectrum1 (915MHz, PN9) c-2. Spectrum2 (915MHz, PN9)

Figure 47 GMSK Modulated Transmitter Output Spectrum Using an Iternal IFVCO

47

HD155101BF

Frequency [MHz]

570

Vcc=3.0V

560

550

540

530

520

0 0.5 1 1.5 2 2.5 3

Vtune [V]

Figure 48 IFVCO Oscillation Frequency vs. Vtune Voltage

48

0.2V/div

278µs

100µs/div

Figure 49 IFVCO Lock Up Time (from PS mode to 540 MHz)

Package Dimesions

9.0 ± 0.2

0.21 ± 0.05

0.19 ± 0.04

9.0 ± 0.2

7.0

36 25

37

48

24

13

0.5

112

M

0.08

0.75 0.75

1.70 Max

1.40

0.17 ± 0.05

0.15 ± 0.04

HD155101BF

Unit: mm

1.00

0° − 8°

0.10

Dimension including the plating thickness

Base material dimension

0.10 ± 0.07

0.50 ± 0.10

Hitachi Code
JEDEC
EIAJ
Weight

(reference value)

FP-48



Conforms

0.2 g

49

HD155101BF

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail­safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.

Hitachi, Ltd.

Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo [phone] Fax: [phone]

URL NorthAmerica : http:semiconductor.hitachi.com/

For further information write to:

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(America) Inc.
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Tel: <1> [phone]
Fax: <1> [phone]

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Electronic components Group
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Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00

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Electronic Components Group.
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Tel: <44> (1628) 585000
Fax: <44> (1628) 778322

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Hitachi Tower
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Tel: [phone]
Fax: [phone]

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Taipei Branch Office
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Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180

Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.

50

Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX