HITACHI 2SJ278 User Manual

2SJ278

2SJ278

Silicon P-Channel MOS FET

Application

High speed power switching

Features

•Low on-resistance

•High speed switching

•Low drive current

•4 V gate drive device can be driven from 5 V source

•Suitable for switching regulator, DC-DC converter

Outline

	UPAK
	2	1
	3
			4
	D
	G	1.	Gate
		2.	Drain
		3.	Source
		4.	Drain

S

2SJ278

Absolute Maximum Ratings (Ta = 25°C)

Item	Symbol	Ratings	Unit
Drain to source voltage	VDSS	–60	V
Gate to source voltage	VGSS	±20	V
Drain current	ID	–1	A
Drain peak current	ID(pulse)*1	–4	A
Body to drain diode reverse drain current	IDR	–1	A
Channel dissipation	Pch*2	1	W
Channel temperature	Tch	150	°C
Storage temperature	Tstg	–55 to +150	°C
Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1%

2.Value on the alumina ceramic board (12.5×20×0.7 mm)

3.Marking is “MY”.

Electrical Characteristics (Ta = 25°C)

Item

Symbol

Min

Typ

Max

Unit

Test conditions

Drain to source breakdown

V(BR)DSS

–60

—

—

V

I

D = –10 mA, VGS = 0

voltage

Gate to source breakdown

V(BR)GSS

±20

—

—

V

I

G = ±100 µA, VDS = 0

voltage

Gate to source leak current

IGSS

—

—

±5

µA

VGS = ±16 V, VDS = 0

Zero gate voltage drain current

IDSS

—

—

–10

µA

VDS = –50 V, VGS = 0

Gate to source cutoff voltage

VGS(off)

–1.0

—

–2.25

V

I D = –1 mA, VDS = –10 V

Static drain to source on state

RDS(on)

—

0.7

0.83

Ω

ID = –0.5 A, VGS = –10 V*1

resistance

—

0.9

1.2

Ω

ID = –0.5 A, VGS = –4 V*1

Forward transfer admittance

|y

fs

|

0.6

1.0

—

S

I

D

= –0.5 A, V

= –10 V*1

DS

Input capacitance

Ciss

—

160

—

pF

V

DS = –10 V, VGS = 0,

Output capacitance

Coss

—

80

—

pF

f = 1 MHz

Reverse transfer capacitance

Crss

—

28

—

pF

Turn-on delay time

td(on)

—

7

—

ns

I

D = –0.5 A, VGS = –10 V,

Rise time

tr

—

8

—

ns

R

L = 60 Ω

Turn-off delay time

td(off)

—

30

—

ns

Fall time

tf

—

25

—

ns

Body to drain diode forward

VDF

—

–1.1

—

V

I

F = –1 A, VGS = 0

voltage

Body to drain diode reverse

trr

—

90

—

ns

I

F = –1 A, VGS

= 0,

recovery time

diF/dt = 50 A/µs

2

2SJ278

Power vs. Temperature Derating

Maximum Safe Operation Area

2.0

–5

Channel Dissipation Pch (W)

(on the aluminam ceramic board)

–3

10

(A)

PW

100

µs

1.5

–1

1

µs

=

D

ms

10

I

DC

ms

–0.3

(1shot)

1.0

Operation in

Current

–0.1

this area is

Operation

limited by RDS(on)

Drain–0.03

0.5

–0.01

Ta = 25 °C

0

50

100

150

200

–0.005

–0.1

–0.3

–1

–3

–10

–30

–100

Ambient Temperature

Ta

(°C)

Drain to Source Voltage

V DS (V)

Typical Output Characteristics

	–2.0		–10 V					–1.0
					Pulse Test
			–6 V
(A)	–1.6		–4 V				(A)	–0.8
				–3 V
D							D
I	–1.2							–0.6
							I
Drain Current
	–0.8			–2.5 V			Drain Current	–0.4
	–0.4							–0.2
				VGS = –2 V
	0	–2	–4	–6	–8	–10		0
		Drain to Source Voltage			VDS (V)

Typical Transfer Characteristics

V DS = –10 V

Pulse Test

75 °C

Tc = –25 °C

25 °C

–1	–2	–3	–4	–5
Gate to Source		Voltage	V GS (V)

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