HIT HM658512ALFP-10, HM658512ALFP-10V, HM658512ALFP-7V, HM658512ALFP-8, HM658512ALFP-8V Datasheet
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HM658512A Series
4 M PSRAM (512-kword × 8-bit)
2 k Refresh
ADE-203-218C(Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher
density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process
technology.
It offers low power data retention by self refresh mode. It also offers easy non multiplexed address
interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery
back-up systems.
The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8 × 20 mm TSOP with thickness
of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also
available.
Features
• Single 5 V (±10%)
• High speed
Access time
CE access time: 70/80/100 ns (max)
Cycle time
Random read/write cycle time:
115/130/160 ns (min)
• Low power
Active: 250 mW (typ)
Standby: 200 µW (typ)
• Directly TTL compatible
All inputs and outputs
• Simple address configuration
Non multiplexed address
• Refresh cycle
2048 refresh cycles: 32 ms
HM658512A Series
2
• Easy refresh functions
Address refresh
Automatic refresh
Self refresh
Ordering Information
Type No. Access time Package
HM658512ALP-7
HM658512ALP-8
HM658512ALP-10
70 ns
80 ns
100 ns
600-mil 32-pin plastic DIP (DP-32)
HM658512ALP-7V
HM658512ALP-8V
HM658512ALP-10V
70 ns
80 ns
100 ns
HM658512ALFP-7
HM658512ALFP-8
HM658512ALFP-10
70 ns
80 ns
100 ns
525-mil 32-pin plastic SOP (FP-32D)
HM658512ALFP-7V
HM658512ALFP-8V
HM658512ALFP-10V
70 ns
80 ns
100 ns
HM658512ALTT-7
HM658512ALTT-8
HM658512ALTT-10
70 ns
80 ns
100 ns
400-mil 32-pin plastic TSOP (TTP-32D)
HM658512ALTT-7V
HM658512ALTT-8V
HM658512ALTT-10V
70 ns
80 ns
100 ns
HM658512ALRR-7
HM658512ALRR-8
HM658512ALRR-10
70 ns
80 ns
100 ns
400-mil 32-pin plastic TSOP (TTP-32DR)
HM658512ALRR-7V
HM658512ALRR-8V
HM658512ALRR-10V
70 ns
80 ns
100 ns
HM658512A Series
3
Pin Arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
V
A15
A17
WE
A13
A8
A9
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
CC
HM658512ALP/ALFP Series
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SS
V
A15
A17
WE
A13
A8
A9
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
CC
HM658512ALTT Series
(Top view)
HM658512A Series
4
Pin Arrangement (cont.)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SS
V
A15
A17
WE
A13
A8
A9
A11
OE/RFSH
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
CC
HM658512ALRR Series
(Top view)
Pin Description
Pin name Function
A0 to A18 Address
I/O0 to I/O7 Input/Output
CE Chip enable
OE/RFSH Output enable/Refresh
WE Write enable
V
CC
Power supply
V
SS
Ground
HM658512A Series
5
Block Diagram
Refresh
Control
Timing Pulse Gen.
Read Write Control
Address Latch Control
Column Decoder
Column I/O
Memory Matrix
Row
Decoder
Address
Latch
Control
Input
Data
Control
CE
WE
I/O 7
I/O 0
A0
A10
A11 A18
OE/RFSH
(2048 × 256) × 8
HM658512A Series
6
Pin Functions
CE: Chip Enable (Input)
CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high.
A0 to A18: Address Inputs (Input)
A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18
are fetched into RAM by the falling edge of CE.
OE/RFSH: Output Enable/Refresh (Input)
This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high
(in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while
OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the
refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes
low.
I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins.
WE: Write Enable (Input)
RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into
RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells.
Refresh
There are three refresh modes : address refresh, automatic refresh and self refresh.
(1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one
method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at
least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins
remain at high impedance, but the refresh is done within RAM.
(2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic
refresh mode if OE/RFSH falls while CE is high and it remains low for at least t
FAP
. One automatic
refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the refresh
address from outside since it is generated internally by an on-chip address counter. 2048 automatic
refresh cycles must be done every 32 ms.
(3) Self refresh: Self refresh mode is suitable for data retention by battery. In standby mode, a self refresh
starts automatically when OE/RFSH stays low for more than 8 µs. Refresh addresses are automatically
specified by the on-chip address counter, and the refresh period is determined by the on-chip timer.
Automatic refresh and self refresh are distinguished from each other by the width of the OE/RFSH low
pulse in standby mode. If the OE/RFSH low pulse is wider than 8 µs, RAM becomes into self refresh
mode; if the OE/RFSH low pulse is less than 8 µs, it is recognized as an automatic refresh instruction.
HM658512A Series
7
At the end of self refresh, refresh reset time (t
RFS
) is required to reset the internal self refresh operation of
the RAM. During t
RFS
, CE and OE/RFSH must be kept high. If auto refresh follows self refresh, low
transition of OE/RFSH at the beginning of automatic refresh must not occur during t
RFS
period.
Notes on Using the HM658512A
Since pseudo static RAM consists of dynamic circuits like DRAM, its clock pins are more noise-sensitive
than conventional SRAM’s.
(1) If a short CE pulse of a width less than tCE min is applied to RAM, an incomplete read occurs and
stored data may be destroyed. Make sure that CE low pulses of less than tCE min are inhibited. Note
that a 10 ns CE low pulse may sometimes occur owing to the gate delay on the board if the CE signal is
generated by the decoding of higher address signals on the board. Avoid these short pulses.
(2) OE/RFSH works as refresh control in standby mode. A short OE/RFSH low pulse may cause an
incomplete refresh that will destroy data. Make sure that OE/RFSH low pulse of less than t
FAP
min are
also inhibited.
(3) t
OHC
and t
OCD
are the timing specs which distinguish the OE function of OE/RFSH from the RFSH
function. The t
OHC
and t
OCD
specs must be strictly maintained.
(4) Start the HM658512A operating by executing at least eight initial cycles (dummy cycles) at least 100
µs after the power voltage reaches 4.5 V-5.5 V after power-on.
Function Table
CE OE/RFSH WE I/O pin Mode
L L H Dout Read
L X L High-Z Write
L H H High-Z —
H L X High-Z Refresh
H H X High-Z Standby
Note: X means H or L.
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