HIT HM62W16255HCJP-10, HM62W16255HCLJP-10, HM62W16255HCLTT-10, HM62W16255HCTT-10 Datasheet
HM62W16255HC Series
4M High Speed SRAM (256-kword × 16-bit)
ADE-203-1200 (Z)
Preliminary
Rev. 0.0
Sep. 1, 2000
Description
The HM62W16255HC is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. The HM62W16255HC is
packaged in 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface mounting.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 10 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 145 mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current: 5 mA (max)
: 1 mA (max) (L-version)
• Data retention current: 0.6 mA (max) (L-version)
• Data retention voltage: 2.0 V (min) (L-version)
• Center VCC and VSS type pinout
Preliminary: The specification of this device are subject to change without notice. Please contact your nearest
Hitachi’s Sales Dept. regarding specification.
HM62W16255HC Series
Ordering Information
Type No. Access time Package
HM62W16255HCJP-10 10 ns 400-mil 44-pin plastic SOJ (CP-44D)
HM62W16255HCLJP-10 10 ns
HM62W16255HCTT-10 10 ns 400-mil 44-pin plastic TSOPII (TTP-44DE)
HM62W16255HCLTT-10 10 ns
2
Pin Arrangement
HM62W16255HC Series
I/O1
I/O2
I/O3
I/O4
V
V
I/O5
I/O6
I/O7
I/O8
WE
Pin Description
A0
A1
A2
A3
A4
CS
CC
SS
A5
A6
A7
A8
A9
44-pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
I/O1
I/O2
I/O3
I/O4
V
V
I/O5
I/O6
I/O7
I/O8
WE
A0
A1
A2
A3
A4
CS
CC
SS
A5
A6
A7
A8
A9
44-pin TSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top View)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE
UB
LB
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
Pin name Function
A0 to A17 Address input
I/O1 to I/O16 Data input/output
CS Chip select
OE Output enable
WE Write enable
UB Upper byte select
LB Lower byte select
V
CC
V
SS
Power supply
Ground
NC No connection
3
HM62W16255HC Series
Block Diagram
(LSB)
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(MSB)
I/O1
.
.
.
I/O8
I/O9
.
.
.
I/O16
WE
CS
LB
Row
decoder
CS
Input
data
control
Memory matrix
1024 rows × 32 columns ×
8 blocks × 16 bit
(4,194,304 bits)
Column I/O
Column decoder
A8 A9 A17 A15 A16 A0 A2 A4
(LSB)
(MSB)
CS
V
CC
V
SS
UB
OE
CS
4
HM62W16255HC Series
Operation Table
CS OE WE LB UB Mode VCC current I/O1–I/O8 I/O9–I/O16 Ref. cycle
H ××××Standby I
LHH××Output disable I
L L H L L Read I
L L H L H Lower byte read I
L L H H L Upper byte read I
L LHHH— I
L × L L L Write I
L × L L H Lower byte write I
L × L H L Upper byte write I
L × L HH— I
, I
SB
CC
CC
CC
CC
CC
CC
CC
CC
CC
Note: ×: H or L
Absolute Maximum Ratings
SB1
High-Z High-Z —
High-Z High-Z —
Output Output Read cycle
Output High-Z Read cycle
High-Z Output Read cycle
High-Z High-Z —
Input Input Write cycle
Input High-Z Write cycle
High-Z Input Write cycle
High-Z High-Z —
Parameter Symbol Value Unit
Supply voltage relative to V
Voltage on any pin relative to V
SS
SS
Power dissipation P
V
CC
V
T
T
–0.5 to +4.6 V
–0.5*1 to VCC + 0.5*
2
V
1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Notes: 1. VT (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns
2. V
(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
T
5
HM62W16255HC Series
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
3
Supply voltage V
Input voltage V
CC
VSS*
IH
V
IL
*
4
Notes: 1. VIL (min) = –2.0 V for pulse width (under shoot) ≤ 6 ns
2. V
(max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns
IH
3. The supply voltage with all V
4. The supply voltage with all V
pins must be on the same level.
CC
pins must be on the same level.
SS
DC Characteristics (Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
3.0 3.3 3.6 V
000V
2.0 — VCC + 0.5*2V
1
–0.5*
— 0.8 V
Parameter Symbol Min Typ*
Input leakage current |I
|——2 µA Vin = VSS to V
LI
1
Max Unit Test conditions
Output leakage current |ILO|——2 µA Vin = VSS to V
Operating power supply current I
CC
— — 145 mA Min cycle
CS = V
IL
, Iout = 0 mA
Other inputs = V
Standby power supply current I
SB
— — 40 mA Min cycle, CS = VIH,
Other inputs = V
I
SB1
— TBD 5 mA f = 0 MHz
V
≥ CS ≥ VCC – 0.2 V,
CC
(1) 0 V ≤ Vin ≤ 0.2 V or
Output voltage V
(2) V
2
—*
OL
V
OH
— — 0.4 V IOL = 8 mA
2.4 — — V IOH = –4 mA
TBD*21.0*
2
≥ Vin ≥ VCC – 0.2 V
CC
Notes: 1. Typical values are at VCC = 3.3 V, Ta = +25°C and not guaranteed.
2. This characteristics is guaranteed only for L-version.
CC
CC
IH/VIL
IH/VIL
6
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