HIT HM62V16256CLTT-5, HM62V16256CLTT-5SL, HM62V16256CLTT-7, HM62V16256CLTT-7SL Datasheet
HM62V16256C Series
4 M SRAM (256-kword × 16-bit)
ADE-203-1099D (Z)
Rev. 1.0
Jan. 31, 2001
Description
The Hitachi HM62V16256C Series is 4-Mbit static RAM organized 262,144-word × 16-bit. HM62V16256C
Series has realized higher density, higher performance and low power consumption by employing CMOS
process technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is
suitable for battery backup systems. It is packaged in standard 44-pin plastic TSOPII.
Features
• Single 2.5 V and 3.0 V supply: 2.2 V to 3.6 V
• Fast access time: 55 ns/70 ns (max)
• Power dissipation:
Active: 5.0 mW/MHz (typ)(VCC = 2.5 V)
: 6.0 mW/MHz (typ) (VCC = 3.0 V)
Standby: 2 µW (typ) (VCC = 2.5 V)
: 2.4 µW (typ) (VCC = 3.0 V)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
Three state output
• Battery backup operation.
2 chip selection for battery backup
HM62V16256C Series
Ordering Information
Type No. Access time Package
HM62V16256CLTT-5
HM62V16256CLTT-7
HM62V16256CLTT-5SL
HM62V16256CLTT-7SL
55 ns
70 ns
55 ns
70 ns
400-mil 44-pin plastic TSOPII (normal-bend type) (TTP-44DB)
2
Pin Arrangement
HM62V16256C Series
44-pin TSOP
A4
A3
A2
A1
A0
CS1
I/O0
I/O1
I/O2
I/O3
V
CC
V
SS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
(Top view)
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
V
SS
V
CC
I/O11
I/O10
I/O9
I/O8
CS2
A8
A9
A10
A11
A12
Pin Description
Pin name Function
A0 to A17 Address input
I/O0 to I/O15 Data input/output
CS1 Chip select 1
CS2 Chip select 2
WE Write enable
OE Output enable
LB Lower byte select
UB Upper byte select
V
CC
V
SS
Power supply
Ground
3
HM62V16256C Series
Block Diagram
LSB
MSB
A12
A11
A10
A9
A8
A13
A14
A15
A16
A17
A7
I/O0
I/O15
Row
decoder
Input
data
control
V
CC
V
SS
•
•
•
•
•
•
•
Memory matrix
2,048 x 2,048
Column I/O
•
•
Column decoder
CS2
CS1
LB
UB
WE
OE
Control logic
LSB
A4
•
•
A3
A2
A1
A5
A6
A0
MSB
4
HM62V16256C Series
Operation Table
CS1 CS2 WE OE UB LB I/O0 to I/O7 I/O8 to I/O15 Operation
H ЧЧЧЧЧHigh-Z High-Z Standby
× L ××××High-Z High-Z Standby
××××H H High-Z High-Z Standby
L H H L L L Dout Dout Read
L H H L H L Dout High-Z Lower byte read
L H H L L H High-Z Dout Upper byte read
LHL×L L Din Din Write
LHL×H L Din High-Z Lower byte write
LHL×L H High-Z Din Upper byte write
LHHH××High-Z High-Z Output disable
Note: H: VIH, L: VIL, ×: VIH or V
Absolute Maximum Ratings
IL
Parameter Symbol Value Unit
Power supply voltage relative to V
Terminal voltage on any pin relative to V
SS
SS
Power dissipation P
V
CC
V
T
T
–0.5 to + 4.6 V
–0.5*1 to VCC + 0.3*
2
V
1.0 W
Storage temperature range Tstg –55 to +125 °C
Storage temperature range under bias Tbias –20 to +85 °C
Notes: 1. VT min: –3.0 V for pulse half-width ≤ 30 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit Note
Supply voltage V
Input high voltage VCC = 2.2 V to 2.7 V V
VCC = 2.7 V to 3.6 V V
Input low voltage VCC = 2.2 V to 2.7 V V
VCC = 2.7 V to 3.6 V V
CC
V
SS
IH
IH
IL
IL
Ambient temperature range Ta –20 — 70 °C
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 30 ns.
2.2 2.5/3.0 3.6 V
000V
2.0 — VCC + 0.3 V
2.0 — VCC + 0.3 V
–0.2 — 0.4 V 1
–0.3 — 0.6 V 1
5
HM62V16256C Series
DC Characteristics
Parameter Symbol Min Typ*1Max Unit Test conditions
Input leakage current |I
Output leakage current |ILO|— —1 µACS1 = VIH or CS2 = VIL or
Operating current I
Average
HM62V16256C-5 I
operating
current
HM62V16256C-7 I
Standby current I
Standby current I
Output high
VCC =2.2 V to 2.7 V V
voltage
VCC =2.7 V to 3.6 V V
VCC =2.2 V to 3.6 V V
Output low
VCC =2.2 V to 2.7 V V
voltage
VCC =2.7 V to 3.6 V V
VCC =2.2 V to 3.6 V V
Notes: 1. Typical values are at VCC = 2.5 V/3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L-version.
3. This characteristic is guaranteed only for L-SL version.
|——1 µA Vin = VSS to V
LI
OE = V
L B = UB = V
CC
— 5 20 mA CS1 = VIL, CS2 = VIH,
Others = V
CC1
— 18 35 mA Min. cycle, duty = 100%,
I
= 0 mA, CS1 = VIL, CS2 = VIH,
I/O
Others = V
CC1
I
CC2
— 1530mA
— 2 5 mA Cycle time = 1 µs, duty = 100%,
I
= 0 mA, CS1 ≤ 0.2 V,
I/O
CS2 ≥ V
V
≥ VCC – 0.2 V, VIL ≤ 0.2 V
IH
SB
SB1
— 0.01 0.3 mA CS2 = V
2
*
— 0.8 20 µA 0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1 ≥ V
CS2 ≥ V
(3) LB = UB ≥ V
CS2 ≥ V
CS1 ≤ 0.2 V
3
I
*
SB1
OH
OH
OH
OL
OL
OL
— 0.8 10 µA
2.0 — — V IOH = –0.5 mA
2.4 — — V IOH = –1 mA
VCC – 0.2— — V IOH = –100 µA
— — 0.4 V IOL = 0.5 mA
— — 0.4 V IOL = 2 mA
— — 0.2 V IOL = 100 µA
CC
or WE = VIL or
IH
, V
IH
I/O
, I
IH/VIL
I/O
IH/VIL
– 0.2 V
CC
IL
– 0.2 V,
CC
– 0.2 V or
CC
– 0.2 V
CC
– 0.2 V
CC
= VSS to V
= 0 mA
CC
6
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