HIT HM62G36256BP-4, HM62G36256BP-5 Datasheet

HM62G36256 Series

8M Synchronous Fast Static RAM

(256k-word × 36-bit)

ADE-203-1139 (Z)

Preliminary

Rev. 0.0

Jan. 10, 2000

Description

The HM62G36256 is a synchronous fast static RAM organized as 256-kword × 36-bit. It has realized high
speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119­bump BGA.

Note: All power supply and ground pins must be connected for proper operation of the device.

Features

• Power supply: 3.3 V +10%, –5%

• Clock frequency: 200 MHz to 250 MHz

• Internal self-timed late write

• Byte write control (4 byte write selects, one for each 9-bit)

• Optional ×18 configuration

• HSTL compatible I/O

• Programmable impedance output drivers

• User selective input trip-point

• Differential, HSTL clock inputs

• Asynchronous G output control

• Asynchronous sleep mode

• Limited set of boundary scan JTAG IEEE 1149.1 compatible

• Protocol: Single clock register-register mode

Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.

HM62G36256 Series

Ordering Information

Type No. Access time Cycle time Package

HM62G36256BP-4
HM62G36256BP-5

Pin Arrangement

2.1 ns

2.5 ns

4.0 ns

5.0 ns

119-bumps BGA

1234567

A

VDDQ SA0 SA6 NC SA4 SA2 VDDQ

B

NC NC SA7 NC SA8 SA9 NC

C

NC SA14 SA3 VDD SA5 SA1 NC

D

DQc1 DQc0 VSS ZQ VSS DQb0 DQb1

E

DQc2 DQc3 VSS SS VSS DQb3 DQb2

F

VDDQ DQc4 VSS G VSS DQb4 VDDQ

G

DQc6 DQc5 SWEc NC DQb5 DQb6

H

DQc7 DQc8 VSS NC VSS DQb8 DQb7

J

VDDQ VDD VREF VDD VREF VDD VDDQ

K

DQd7 DQd8 VSS K VSS DQa8 DQa7

L

DQd6 DQd5 K SWEa DQa5 DQa6

M

VDDQ DQd4 VSS SWE VSS DQa4 VDDQ

N

DQd2 DQd3 VSS SA17 VSS DQa3 DQa2

P

DQd1 DQd0 VSS SA16 VSS DQa0 DQa1

R

NC SA10 M1 VDD M2 SA11 NC

T

NC NC SA12 SA15 SA13 NC ZZ

U

VDDQ TMS TDI TCK TDO NC VDDQ

SWEd

SWEb

119-bump 1. 27 mm
14 mm × 22 mm BGA (BP-119A)

(Top view)

2

HM62G36256 Series

Pin Description

Name I/O type Descriptions Notes

V

DD

V

SS

V

DDQ

V

REF

K Input Clock input. Active high.

K Input Clock input. Active low.
SS Input Synchronous chip select
SWE Input Synchronous write enable

SAn Input Synchronous address input n = 0, 1, 2...17

SWEx Input Synchronous byte write enables x = a, b, c, d
G Input Asynchronous output enable

ZZ Input Power down mode select
ZQ Input Output impedance control 1
DQxn I/O Synchronous data input/output x = a, b, c, d

M1, M2 Input Output protocol mode select
TMS Input Boundary scan test mode select
TCK Input Boundary scan test clock
TDI Input Boundary scan test data input
TDO Output Boundary scan test data output
NC — No connection

Supply Core power supply
Supply Ground
Supply Output power supply
Supply Input reference: provides input reference voltage

n = 0, 1, 2...8

M1 M2 Protocol Notes

V

SS

V

DD

Synchronous register to register operation 2

Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 150 Ω ≤ RQ ≤ 300 Ω, if ZQ = V

open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120 Ω between ZQ and V

2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either V

.

SS

DD

respectively. The state of the Mode control inputs must be set before power-up and must not
change during device operation. Mode control inputs are not standard inputs and may not meet
V

or VIL specification. This SRAM is tested only in the synchronous register to register

IH

operation.

DDQ

or V

or

SS

3

HM62G36256 Series

Block Diagram

A0 to A17

SS

SWE

SWEx

ZZ

V

REF

ZQ

18

JTAG
register

JTAG
register

JTAG
register

4

JTAG
register

G

K

K

JTAG
register

JTAG
register

JTAG
register

JTAG
register

JTAG
register

R-Add
register

SS
register

SWE
register

SWEx
register

CLK

control

18

W-Add
register

4

Impedance
contorol logic

18

MUX

1

WRC

Match

DOC

D-in
register

Memory

cell array

(256k × 36)

Row decoder

Column decoder

WA

Multiplex

D-out
register

OB

36

SA

DQa0-8
DQb0-8
DQc0-8
DQd0-8

TDI

TCK

TMS

JTAG tap
controller

TDO

4

HM62G36256 Series

Operation Table

ZZ SS G SWE SWEa SWEb SWEc SWEd K K Operation DQ (n) DQ (n + 1)

H ××ЧЧЧЧЧЧ×sleep mode High-Z High-Z
LH×ЧЧЧЧЧL-H H-L Dead

(not selected)

L × H ЧЧЧЧЧЧ×Dead

(Dummy read)

LLLH ××××L-H H-L Read × Dout

LL× LLLLLL-HH-LWrite a, b, c, d

byte

LL× L H L L L L-H H-L Write b, c, d

byte

LL× L L H L L L-H H-L Write a, c, d

byte

LL× LLLHLL-HH-LWrite a, b, d

byte

LL× LLLLHL-HH-LWrite a, b, c

byte
LL× L H H L L L-H H-L Write c, d byte High-Z Din (c,d)0-8
LL× L L H H L L-H H-L Write a, d byte High-Z Din (a,d)0-8
LL× L L L H H L-H H-L Write a, b byte High-Z Din (a,b)0-8
LL× L H L L H L-H H-L Write b, c byte High-Z Din (b,c)0-8
LL× LHHHLL-HH-LWrite d byte High-Z Din (d)0-8
LL× L H H L H L-H H-L Write c byte High-Z Din (c)0-8
LL× L H L H H L-H H-L Write b byte High-Z Din (b)0-8
LL× L L H H H L-H H-L Write a byte High-Z Din (a)0-8

Notes: 1. × means don’t care for synchronous inputs, and H or L for asynchronous inputs.

2. SWE , SS, SWEa to SWEd, SA are sampled at the rising edge of K clock.

3. Although differential clock operation is implied, this SRAM will operate properly with one clock
phase (either K or K) tied to V
specified within this document will be met.

. Under such single-ended clock operation, all parameters

REF

× High-Z

High-Z High-Z

(a,b,c,d)0-8

High-Z Din (a,b,c,d)0-8

High-Z Din (b,c,d)0-8

High-Z Din (a,c,d)0-8

High-Z Din (a,b,d)0-8

High-Z Din (a,b,c)0-8

5

HM62G36256 Series

Absolute Maximum Ratings

Parameter Symbol Value Unit Notes

Input voltage on any pin V
Core supply voltage V
Output supply voltage V
Operating temperature T
Storage temperature T

IN

DD

DDQ

OPR

STG

–0.5 to V
–0.5 to 3.9 V 1
–0.5 to 2.2 V 1, 4
0 to 70 °C

–55 to 125 °C
Junction temperature Tj 110 °C
Output short–circuit current I
Latch up current I

OUT

LI

25 mA

200 mA
Package junction to case thermal resistance θJC 5 °C/W 5, 7
Package junction to ball thermal resistance θJB 8 °C/W 6, 7

Notes: 1. All voltage is referred to VSS.

2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be restricted the Operation Conditions. Exposure to higher than recommended
voltages for extended periods of time could affect device reliability.

3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown
in the tables after thermal equilibrium has been established.

4. The supply voltage application sequence need to be powered up in the following manner: V
V

, V

, V

DD

DDQ

then VIN. Remember, according to the Absolute Maximum Ratings table, V

REF

not to exceed 3.9 V, whatever the instantaneous value of V

5. θJC is measured at the center of mold surface in fluorocarbon (See Figure “Definition of
Measurement”).

6. θJB is measured on the center ball pad after removing the ball in fluorocarbon (See Figure
“Definition of Measurement”).

7. These thermal resistance values have error of ± 5°C/W.

+ 0.5 V 1, 4

DDQ

.

DDQ

DDQ

,

SS

is

θJC

θJB

T.C.

Fluorocarbon

T.C.

Fluorocarbon

Definition of Measurement

6

HM62G36256 Series

Note: The following the DC and AC specifications shown in the Tables, this device is tested under the

minimum transverse air flow exceeding 500 linear feet per minute.

DC Operating Conditions (Ta = 0 to 70°C [Tj max = 110°C])

Parameter Symbol Min Typ Max Unit Notes

Supply voltage (Core) V
Supply voltage (I/O) V
Supply voltage V
Input reference voltage (I/O) V
Input high voltage V
Input low voltage V
Clock differential voltage V
Clock common mode voltage V

DD

DDQ

SS

REF

IH

IL

DIF

CM

Notes: 1. Peak to peak AC component superimposed on V

2. Minimum differential input voltage required for differential input clock operation.

3. See following figure.

4. V

= 0.75 V (typ).

REF

3.135 3.30 3.63 V

1.4 1.5 1.6 V
000 V

0.65 0.75 0.90 V 1
V

+ 0.1 — V

REF

–0.5 — V

0.1 — V

+ 0.3 V 4

DDQ

– 0.1 V 4

REF

+ 0.3 V 2, 3

DDQ

0.55 — 0.90 V 3
may not exceed 5% of V

REF

REF

.

V

DDQ

V

SS

V

DIF

V

CM

Differential Voltage/Common Mode Voltage

7

HM62G36256 Series

DC Characteristics (Ta = 0 to 70°C, [Tj max = 110°C], VDD = 3.3 V +10%, –5%)

Parameter Symbol Min Typ Max Unit Notes

Input leakage current I
Output leakage current I
Standby current I
VDD operating current,

excluding output drivers
4 ns cycle

VDD operating current,
excluding output drivers
5 ns cycle

Quiescent active power
supply current

Output low voltage V
Output high voltage V
ZQ pin connect

resistance
Output low current I
Output high current I

Notes: 1. 0 ≤ Vin ≤ V

2. 0 ≤ Vout ≤ V

DDQ

DDQ

3. All inputs (except clock) are held at either V
guaranteed at 75°C junction temperature.

4. Iout = 0 mA, read 50%/write 50%, V

5

. Iout = 0 mA, read 50%/write 50%, V

6. Minimum impedance push pull output buffer mode, I

7. Measured at V

8. Measured at V

9. Output buffer impedance can be programmed by terminating the ZQ pin to V
precision resister (RQ). The value of RQ is five times the output impedance desired. The
allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between
150 Ω and 300 Ω. If the status of ZQ pin is open, output impedance is maximum. Maximum
impedance occurs with ZQ connected to V
occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch
the SRAM into and out of High-Z, therefore triggering an update. The user may choose to
invoke asynchronous G updates by providing a G setup and hold about the K clock to guarantee
the proper update. At power-up, the output impedance defaults to minimum impedance. It will
take 2048 cycles for the impedance to be completely updated if the programmed impedance is
much higher than minimum impedance.

LI

LO

SBZZ

I

DD4

I

DD5

I

DD2

RQ 150 250 300 Ω

OL

OH

for all input pins (except V

OL

OH

——2 µA1
——5 µA2
— — 100 mA 3
— — 700 mA 4

— — 650 mA 4

— — 200 mA 5

V

OL

OH

SS

V

– 0.4 — V

DDQ

(V

/2)/[(RQ/5)–15%] — (V

DDQ

(V

/2)/[(RQ/5–4)+15%] — (V

DDQ

REF

—VSS + 0.4 V 6

DDQ

/2)/[(RQ/5)+15%] mA 7, 9

DDQ

/2)/[(RQ/5–4)–15%] mA 8, 9

DDQ

, ZQ, M1, M2 pin).

, DQ in High-Z.

or VIL, ZZ is held at VIH, Iout = 0 mA, Spec is

IH

= VDD max, VIN = VIH or VIL, Frequency = minimum cycle.

DD

= VDD max, VIN = VIH or VIL, Frequency = 3 MHz.

DD

= –6 mA, IOL = 6 mA.

OH

= 1/2 V

= 1/2 V

DDQ

DDQ

.

.

. The impedance update of the output driver

DDQ

through a

SS

V6

8