HIT HM6264BLFP-10LT, HM6264BLFP-8LT, HM6264BLP-10L, HM6264BLP-8L, HM6264BLSP-10L Datasheet
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HM6264B Series
64 k SRAM (8-kword × 8-bit)
ADE-203-454B (Z)
Rev. 2.0
Nov. 1997
Description
The Hitachi HM6264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance
and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil
SOP (foot print pitch width), 600 mil plastic DIP, 300 mil plastic DIP, is available for high density
mounting.
Features
• High speed
Fast access time: 85/100 ns (max)
• Low power
Standby: 10 µW (typ)
Operation: 15 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Battery backup operation capability
HM6264B Series
Ordering Information
Type No. Access time Package
HM6264BLP-8L
HM6264BLP-10L
HM6264BLSP-8L
HM6264BLSP-10L
HM6264BLFP-8LT
HM6264BLFP-10LT
Pin Arrangement
85 ns
100 ns
85 ns
100 ns
85 ns
100 ns
600-mil, 28-pin plastic DIP (DP-28)
300-mil, 28-pin plastic DIP(DP-28N)
450-mil, 28-pin plastic SOP(FP-28DA)
HM6264BLP/BLSP/BLFP Series
1
NC
A12
A7
A6
A4
A0
I/O1
I/O2
I/O3
V
SS
2
3
4
5A5
6
7A3
8A2
9A1
10
11
12
13
14
28
27
24
23
22
21
20
19
18
V
CC
WE
CS226
A825
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O617
I/O516
I/O415
(Top view)
Pin Description
Pin name Function Pin name Function
A0 to A12 Address input WE Write enable
I/O1 to I/O8 Data input/output OE Output enable
CS1 Chip select 1 NC No connection
CS2 Chip select 2 V
CC
V
SS
Power supply
Ground
Block Diagram
A11
A8
A9
A7
A12
A5
A6
A4
Row
decoder
Memory array
256 × 256
HM6264B Series
V
CC
V
SS
I/O1
I/O8
CS2
CS1
WE
OE
Column I/O
Input
data
control
Timing pulse generator
Read, Write control
Column decoder
A1 A3
A2 A0 A10
HM6264B Series
Function Table
WE CS1 CS2 OE Mode VCC current I/O pin Ref. cycle
× H ××Not selected (power down) I
××L × Not selected (power down) ISB, I
H L H H Output disable I
H L H L Read I
L L H H Write I
L L H L Write I
, I
SB
SB1
SB1
CC
CC
CC
CC
Note: ×: H or L
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage
Terminal voltage
*1
*1
Power dissipation P
Operating temperature Topr 0 to + 70 °C
Storage temperature Tstg –55 to +125 °C
Storage temperature under bias Tbias –10 to +85 °C
Notes: 1. Relative to V
SS
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 7.0 V
V
CC
V
T
T
–0.5 to +7.0 V
–0.5*2 to VCC + 0.3*3V
1.0 W
High-Z —
High-Z —
High-Z —
Dout Read cycle (1)–(3)
Din Write cycle (1)
Din Write cycle (2)
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage V
Input high voltage V
Input low voltage V
CC
V
SS
IH
IL
Note: 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns
4.5 5.0 5.5 V
000V
2.2 — VCC + 0.3 V
*1
–0.3
— 0.8 V
HM6264B Series
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V)
Parameter Symbol Min Typ*1Max Unit Test conditions
Input leakage current |I
Output leakage current |ILO| ——2 µA CS1 = VIH or CS2 = VIL or OE = VIH or
Operating power supply
current
Average operating power
supply current
Standby power supply
current
Output low voltage V
Output high voltage V
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
| ——2 µA Vin = VSS to V
LI
WE = V
I
CCDC
— 7 15 mA CS1 = VIL, CS2 = VIH, I
others = V
I
CC1
— 30 45 mA Min cycle, duty = 100%,
CS1 = V
others = V
I
CC2
— 3 5 mA Cycle time = 1 µs, duty = 100%, I
CS1 ≤ 0.2 V, CS2 ≥ V
V
≥ VCC – 0.2 V, VIL ≤ 0.2 V
IH
I
SB
I
SB1
—13mACS1 = VIH, CS2 = V
—2 50µA CS1 ≥ VCC – 0.2 V, CS2 ≥ VCC – 0.2 V or
0 V ≤ CS2 ≤ 0.2 V, 0 V ≤ Vin
OL
OH
— — 0.4 V IOL = 2.1 mA
2.4 — — V IOH = –1.0 mA
CC
, V
= V
IL
I/O
IH/VIL
, CS2 = VIH, I
IL
IH/VIL
SS
to V
CC
IL
CC
= 0 mA
I/O
= 0 mA
I/O
– 0.2 V,
= 0 mA
I/O
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions
Input capacitance
Input/output capacitance
*1
*1
Note: 1. This parameter is sampled and not 100% tested.
Cin — — 5 pF Vin = 0 V
C
I/O
——7 pFV
= 0 V
I/O
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