HIT HM5212325FBPC-B60 Datasheet
HM5212325FBPC-B60
128M LVTTL interface SDRAM
100 MHz
1-Mword × 32-bit × 4-bank
PC/100 SDRAM
ADE-203-1122C (Z)
Rev. 1.0
May. 12 , 2000
Description
The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All
inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine
pitch BGA.
Features
• Single chip wide bit solution (× 32)
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Extremely small foot print: 0.8 mm pitch
Package: FBGA (BP-90)
• 4 banks can operate simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 4/8/full page
• 2 variations of burst sequence
Sequential (BL = 4/8/full page)
Interleave (BL = 4/8)
• Programmable CAS latency: 2/3
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
HM5212325FBPC-B60
• 2 variations of refresh
Auto refresh
Self refresh
• Full page burst length capability
Sequential burst
Burst stop capability
Ordering Information
Type No. Frequency CAS latency Package
HM5212325FBPC-B60* 100 MHz 3 10 mm × 13 mm 90 bump FBGA (BP-90)
Note: 66 MHz operation at CAS latency = 2.
2
Pin Arrangement
HM5212325FBPC-B60
90-bump FBGA
1 2 3
V
A
B
C
D
E
F
G
H
J
K
L
DQ15
SS
DQ13
DQ14
DQ11
DQ12
DQ9
DQ10
NC
DQ8
DQ
Open
MB1
NC CLK
CKE
A9
A6
DQ
A3
MB3
NC
DQ31
6 7 8
V
SS
V
CC
V
SS
V
CC
V
SS
NC
A8A11
A7A5
A4
V
SS
V
CC
V
SS
V
CC
V
SS
V
CC
NC
A12
A13 A10
A1 A2
V
CC
V
DQ0
DQ2 DQ1
NC
WECAS
CS RAS
NC
NC
CC
DQ3DQ4
DQ5DQ6
DQ7
DQ
MB0
NC
A0
DQ
MB2
DQ16
M
N
P
Q
DQ27
DQ25
V
SS
DQ28
DQ26
DQ24
CC
V
SS
V
CC
V
SS
V
DQ30
DQ29
V
SS
V
CC
V
SS
V
CC
DQ17 DQ18
DQ20
DQ19
DQ22DQ21
V
DQ23
CC
(Top view)
3
HM5212325FBPC-B60
Pin Description
Pin name Function
A0 to A13 Address input
Row address A0 to A11
Column address A0 to A7
Bank select address A12/A13 (BS)
DQ0 to DQ31 Data-input/output
CS Chip select
RAS Row address strobe command
CAS Column address strobe command
WE Write enable
DQMB0 to DQMB3 Byte data mask*
CLK Clock input
CKE Clock enable
V
CC
V
SS
Open Open*
Power supply
Ground
2
Note: 1. DQMB0: DQ0 to DQ7
DQMB1: DQ8 to DQ15
DQMB2: DQ16 to DQ23
DQMB3: DQ24 to DQ31
2. Don’t connect. Internally connected with die.
1
4
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