HIT HD74LV595A Datasheet
HD74LV595A
8-bit Shift Registers with 3-state Outputs
ADE-205-281 (Z)
1st Edition
April 1999
Description
This device each contains an 8-bit serial-in, parallel-out shift registers that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift
register anf the storage register. The shift register has a direct-overriding clear, serial input, and serial
output pins for cascading.
Both the shift register anf the storage register clocks are positive-edge triggered. If the user wishes to
connect both clocks together, the shift register state will always be one clock pulse ahead of the storage
register. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
HD74LV595A
Function Table
Inputs
SER SRCLK SRCLR RCLK G Function
X XXXHForce outputs into high-impedance state
X XXXLEnable paralle output
X X L X X Reset shift register
L ↑ H X X Shift data into shift register
H ↑ H X X Shift data into shift register
X ↓ H X X Shift register remains unchanged
XXX↑ X Transfer shift register contents to latch
register
XXX↓ X Latch register remains unchanged
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
2
Pin Arrangement
HD74LV595A
V
1
Q
B
16
CC
Q
Q
Q
Q
Q
Q
GND
2
C
3
D
4
E
5
F
6
G
7
H
8
15
14
13
12
11
10
9
Q
A
SER
G
RCLK
SRCLK
SRCLR
Q
H'
(Top view)
3
HD74LV595A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 Output: Z or VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
CC
±70 mA
785 mW SOP
500 TSSOP
4
HD74LV595A
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV H or L
0 5.5 High impedance state
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
5
HD74LV595A
Logic Diagram
(13)
G
(12)
RCLK
SER
(10)
(11)
(14)
SRCLR
SRCLK
1D
R
C1
3R
3S
C3
(15)
Q
A
2S
2R
R
2S
2R
R
2S
2R
R
2S
2R
R
2S
2R
R
2S
2R
R
C2
C2
C2
C2
C2
C2
3R
3S
3R
3S
3R
3S
3R
3S
3R
3S
3R
3S
C3
C3
C3
C3
C3
C3
(1)
(2)
(3)
(4)
(5)
(6)
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
2S
2R
R
C2
3R
3S
C3
(7)
(9)
Q
H
Q
'
H
6
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