HIT HD74LV4040A Datasheet
HD74LV4040A
12-stage Binary Counter
ADE-205-282 (Z)
1st Edition
April 1999
Description
The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative
transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset
input. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
Function Table
Inputs Output
CLK CLR Q
↑ L Remains unchanged
↓ L Changed
X H All outputs low
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
n
HD74LV4040A
Pin Arrangement
V
1
Q
12
16
CC
Q
6
Q
5
Q
7
Q
4
Q
3
Q
2
GND
2
3
4
5
6
7
8
15
14
13
12
11
10
Q
11
Q
10
Q
8
Q
9
CLR
CLK
9
Q
1
(Top view)
2
HD74LV4040A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
±50 mA
785 mW SOP
500 TSSOP
CC
3
HD74LV4040A
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV H or L
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
4
Logic Diagram
(11)
CLR
(10)
CLK
HD74LV4040A
R
T
R
T
R
T
R
T
R
T
(9)
(7)
(6)
(5)
(3)
Q
1
Q
2
Q
3
Q
4
Q
5
R
T
R
T
R
T
R
T
R
T
(4)
(13)
(12)
(14)
(15)
Q
7
Q
8
Q
9
Q
10
Q
11
R
T
(2)
Q
6
R
T
(1)
Q
12
5
HD74LV4040A
Timing Diagram
CLK
CLR
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
CLEAR
1
23481632641282565121024 2048 4096
COUNT
CLEAR
6
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