HIT HD74LV165A Datasheet

HD74LV165A

Parallel-Load 8-bit Shift Register

ADE-205-267 (Z)

1st Edition

March 1999

Description

The HD74LV165A is 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to
each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a
complementary output from the eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a clock inhibit
function. Holding either of the clock inputs high inhibits clocking, and high enables the other clock input.
Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the
Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register
independent of the state of the clock.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.

Features

• VCC = 2.0 V to 5.5 V operation

• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)

• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)

• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)

HD74LV165A

Function Table

Inputs Internal Outputs Output
SH/LD CLK INH CLK SER A ... H QA QB QH

L X X X a ... h a b h
HL ↑ HX HQAnQ
HL ↑ LXLQAnQ
HHXXXQA0Q
HXHXXQA0Q

B0

B0

H ↑ LHXHQAnQ
H ↑ LLXLQAnQ

Note: H: High level

L: Low level
↑: Low to high transition
X: Immaterial
a ... h: Parallel data
Q

... QH0: Outputs remain unchanged.

A0

Q

... QGn: Data shifted from the previous stage on a positive edge at the clock input.

An

Gn

Gn

Q

H0

Q

H0

Gn

Gn

Pin Arrangement

SH/LD

CLK

Q

GND

V

1
2
3

E

4

F

5

G

6

H

7

H

8

16
15
14
13
12
11
10

9

CC

CLK INH
D
C
B
A
SER
Q

H

(Top view)

2

HD74LV165A

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage range V
Input voltage range*
Output voltage range*

1

1, 2

Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through

V

or GND

CC

Maximum power dissipation
at Ta = 25°C (in still air)*

3

CC

V

I

V

O

IK

OK

O

or I

I

CC

GND

P

T

Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,

no two of which may be realized at the same time.

1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The maximum package power dissipation was calculated using a junction temperature of 150°C.

–0.5 to 7.0 V
–0.5 to 7.0 V
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0

±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V

CC

±50 mA

785 mW SOP

500 TSSOP

CC

3

HD74LV165A

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage range V
Input voltage range V
Output voltage range V
Output current I

CC

I

O

OH

I

OL

Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V

Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.

2.0 5.5 V
0 5.5 V
0VCCV H or L
— –50 µAV
—–2 mAV
—–6 V

= 2.0 V

CC

= 2.3 to 2.7 V

CC

= 3.0 to 3.6 V

CC

— –12 VCC = 4.5 to 5.5 V
—50 µAV

= 2.0 V

CC

— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V

= 3.0 to 3.6 V

CC

= 4.5 to 5.5 V

CC

0 100 VCC = 3.0 to 3.6 V
020 V

= 4.5 to 5.5 V

CC

4

Logic Diagram

HD74LV165A

1

SH/LD

15

CLK INH

2

CLK

10

SER

Timing Diagram

CLK INH

SH/LD

CLK

SER

A

11

B

12

S

C1
1D
R

C

13

S

C1
1D
R

D

14

S

C1
1D
R

E

3

S

C1
1D
R

F

4

S

C1
1D
R

G

5

S

C1
1D
R

H

6

S

C1
1D
R

S

9

C1
1D
R

Q

H

7

Q

H

L

A

H

Data

Inputs

B
C
D

E
F

G
H

Q

H

Q

H

L

H

L

H

L

H
H

LLL

HHHH

H

HHH

LLLLL

Inhibit Serial Shift

Load

5

HD74LV165A

DC Electrical Characteristics

• Ta = –40 to 85°C

Item Symbol VCC (V)* Min Typ Max Unit Test Conditions

Input voltage V

Output voltage V

Input current I
Quiescent

IH

V

IL

OH

V

OL

IN

I

CC

supply current
Output leakage

I

OFF

current
Input

C

IN

capacitance

Note: For conditions shown as Min or Max, use the appropriate values under recommended operating

conditions.

2.0 1.5 — — V

2.3 to 2.7 VCC × 0.7 — —

3.0 to 3.6 VCC × 0.7 — —

4.5 to 5.5 VCC × 0.7 — —

2.0 — — 0.5

2.3 to 2.7 — — VCC × 0.3

3.0 to 3.6 — — VCC × 0.3

4.5 to 5.5 — — VCC × 0.3
Min to

VCC – 0.1 — — V IOL = –50 µA

Max

2.3 2.0 — — IOL = –2 mA

3.0 2.48 — — IOL = –6 mA

4.5 3.8 — — IOL = –12 mA
Min to

— — 0.1 IOL = 50 µA

Max

2.3 — — 0.4 IOL = 2 mA

3.0 — — 0.44 IOL = 6 mA

4.5 — — 0.55 IOL = 12 mA
0 to 5.5 — — ±1 µAVI = 5.5 V or GND

5.5 — — 20 µAVI = VCC or GND, IO = 0

0——5 µAVI or VO = 0 V to 5.5 V

3.3 — 1.7 — pF VI = VCC or GND

6