HIT HD74LV161A Datasheet
HD74LV161A
Synchronous 4-bit Binary Counter (Direct Clear)
ADE-205-264A (Z)
2nd Edition
June 1999
Description
The HD74LV161A is 4-bit binary counters. All flip flops are clocked simultaneously on the low to high to
transition (positive edge) of the clock input waveform. These counters may be preset using the load input.
Presetting of all four flip flops is synchronous to the rising edge of clock. When load is held low counting
is disabled and tha data on the A, B, C and D inputs is loaded into the counter on the rising edge clock. If
the load input is taken high before the positive edge of clock the count operation will be unaffected.
Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook
computers), and the low-power consumption extends the battery life.
Features
• VCC = 2.0 V to 5.5 V operation
• All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V)
• All outputs VO (Max.) = 5.5 V (@VCC = 0 V)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C)
• Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V)
HD74LV161A
Function Table
Inputs Outputs
CLR LOAD ENP ENT CLK QA QB QC QD
LXXXXLLLL
HLX X↑ ABCD
HHXL ↑ No change
HHL X↑ No change
HHHH↑ Count up
HXX X↓ No change
Note: H: High level
L: Low level
X: Immaterial
↑: Low to high transition
↓: High to low transition
A, B, C, D: Data input
Carry = ENT • QA • QB • QC • QD
Pin Arrangement
CLR
CK
ENP
GND
V
1
2
3
A
4
B
5
C
6
D
7
8
(Top view)
16
15
14
13
12
11
10
9
CC
CARRY
OUTPUT
QA
QB
QC
QD
ENT
LOAD
2
HD74LV161A
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage range V
Input voltage range*
Output voltage range*
1
1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Continuous current through
V
or GND
CC
Maximum power dissipation
at Ta = 25°C (in still air)*
3
CC
V
I
V
O
IK
OK
O
or I
I
CC
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: The absolute maximum ratings are values which must not individually be exceeded, and furthermore,
no two of which may be realized at the same time.
1. The input and output voltage ratings may be exceeded if the input and output clamp-current
ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The maximum package power dissipation was calculated using a junction temperature of 150°C.
–0.5 to 7.0 V
–0.5 to 7.0 V H or L
–0.5 to VCC + 0.5 V Output: H or L
–0.5 to 7.0 VCC: OFF
–20 mA VI < 0
±50 mA VO < 0 or VO > V
±25 mA VO = 0 to V
CC
±50 mA
785 mW SOP
500 TSSOP
CC
3
HD74LV161A
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage range V
Input voltage range V
Output voltage range V
Output current I
CC
I
O
OH
I
OL
Input transition rise or fall rate ∆t /∆v 0 200 ns/V VCC = 2.3 to 2.7 V
Operating free-air temperature Ta –40 85 °C
Note: Unused or floating inputs must be held high or low.
2.0 5.5 V
0 5.5 V
0VCCV
— –50 µAV
—–2 mAV
—–6 V
= 2.0 V
CC
= 2.3 to 2.7 V
CC
= 3.0 to 3.6 V
CC
— –12 VCC = 4.5 to 5.5 V
—50 µAV
= 2.0 V
CC
— 2 mA VCC = 2.3 to 2.7 V
—6 V
—12 V
= 3.0 to 3.6 V
CC
= 4.5 to 5.5 V
CC
0 100 VCC = 3.0 to 3.6 V
020 V
= 4.5 to 5.5 V
CC
4
Logic Diagram
CLK
CLR
HD74LV161A
Output
DCKQ
Q
A
LOAD
Enable
Data
Inputs
Q
CLR
P
T
A
B
DCKQ
CLR
Q
Output
Q
B
Output
DCKQ
Q
CLR
C
Q
C
Output
DCKQ
Q
CLR
D
Q
D
Carry
Output
5
HD74LV161A
Timing Diagram
CLR
LOAD
A
Data
Inputs
Out
puts
CLK
ENP
ENT
Q
Q
Q
Q
Carry
B
C
D
A
B
C
D
Clear
12 13 14 15 0
Count
Preset
12
Inhibit
(Load)
6
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