HIT HD74HCT574, HD74HCT564 Datasheet
HD74HCT564/HD74HCT574
Octal D-type Flip-Flops (with 3-state outputs)
Description
These devices are positive edge triggered flip-flops. The difference between HD74HCT564 and
HD74HCT574 is only that the former has inverting outputs and the latter has non-inverting outputs.
Data at the D inputs, meeting the set-up and hold time requirements, are transferred to the Q or Q outputs
on positive going transitions of the clock (CK) input. When a high logic level is applied to the output
control (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the
other inputs and the state of the storage elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (D to Q, Q) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Outputs
Output Control Clock Data HD74HCT564 HD74HCT574
L HLH
L LHL
LL X Q
HX X Z Z
0
Q
0
HD74HCT564/HD74HCT574
Pin Arrangement
HD74HCT564
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
10
V
OE
OE
OE
OE
20
CC
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Clock
QD
QD
QD
QD
1
2
OE
3
QD
4
OE
5
QD
6
OE
7
QD
8
OE
9
QD
(Top view)
2
HD74HCT574
HD74HCT564/HD74HCT574
Output
Control
1D
2D
3D
4D
5D
6D
7D
8D
GND
10
V
OE
OE
OE
OE
20
CC
19
18
17
16
15
14
13
12
11
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Clock
QD
QD
QD
QD
1
2
OE
3
QD
4
OE
5
QD
6
OE
7
QD
8
OE
9
QD
(Top view)
3
HD74HCT564/HD74HCT574
Block Diagram
HD74HCT564
CLK
OC
1D
2D
3D
4D
5D
6D
7D
8D
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
D
CQ
C
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
4
Loading...