HIT HD74HCT534, HD74HCT374 Datasheet
HD74HCT374/HD74HCT534
Octal D-type Flip-Flops (with 3-state outputs)/
Octal D-type Flip-Flops (with inverted 3-state outputs)
Description
These device are positive edge triggered flip-flops. The difference between HD74HCT374 and
HD74HCT534 is only that the former is a true outputs and the latter is a false outputs. Data at the D inputs,
meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions
of the clock (CK) input. When a high logic level is applied to the output control (OC) input, all outputs go
to a high impedance state, regardless of what signals are present at the other inputs and the state of the
storage elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
HD74HCT374
Output Control Clock D
L
L LLH
L L X No change No change
HX X Z Z
X : Irrelevant
Z : Off (high-impedance) state of a 3-state output.
HHL
Q
HD74HCT534
Q
HD74HCT374/HD74HCT534
Pin Arrangement
HD74HCT374
HD74HCT534
Output
Control
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
Output
Control
10
V
1
2
3
4
5
6
7
8
9
(Top view)
1
20
19
18
17
16
15
14
13
12
11
20
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
Clock
V
CC
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
4Q
9
GND
10
(Top view)
2
19
18
17
16
15
14
13
12
11
8Q
8D
7D
7Q
6Q
6D
5D
5Q
Clock
Block Diagram
HD74HCT374
HD74HCT374/HD74HCT534
Clock
Output
Control
HD74HCT534
Clock
1D
1D
2D
DQ
C
Q
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
2D
DQ
C
Q
DQ
C
DQ
C
Q
Q
3D
3D
DQ
C
Q
DQ
C
Q
4D
4D
DQ
C
Q
DQ
C
Q
5D
5D
DQ
C
Q
DQ
C
Q
6D
6D
DQ
C
Q
DQ
C
Q
7D
7D
DQ
C
Q
DQ
C
Q
8D
8D
DQ
C
Q
DQ
C
Q
Output
Control
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
3
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