HIT HD74HCT533, HD74HCT373 Datasheet
HD74HCT373/HD74HCT533
Octal D-type Transparent Latches (with 3-state outputs)/
Octal D-type Transparent Latches (with inverted 3-state outputs)
Description
When the latch enable input is high, the Q outputs of HD74HCT373 will follow the D inputs and the Q
outputs of HD74HCT533 will follow the inversion of the D inputs. When the latch enable goes low, data at
the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is
applied to the output control input, all outputs go to a high impedance state, regardless of what signals
present at the other inputs and the state of the storage elements.
Features
• LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility
• High Speed Operation: tpd (Data to Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 4.5 to 5.5 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Enable
Output Control
LH H H L
LH L L H
L L X No change No change
HX X Z Z
X : Irrelevant
Z : Off (high-impedance) state of a 3-state output.
GD
HD74HCT373
Q
HD74HCT533
Q
HD74HCT373/HD74HCT533
Pin Arrangement
HD74HCT373
HD74HCT533
Output
Control
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
Output
Control
10
V
1
2
3
4
5
6
7
8
9
(Top view)
1
20
19
18
17
16
15
14
13
12
11
20
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
Enable G
V
CC
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
4Q
9
GND
10
(Top view)
2
19
18
17
16
15
14
13
12
11
8Q
8D
7D
7Q
6Q
6D
5D
5Q
Enable G
Block Diagram
HD74HCT373
HD74HCT373/HD74HCT533
Enable G
Output
Control
HD74HCT533
Enable G
1D
1D
2D 3D 4D 5D 6D 7D 8D
D
G
D
G
D
Q
G
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
2D 3D 4D 5D 6D 7D 8D
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
G
D
Q
Q
Q
G
D
Q
G
D
Q
G
D
Q
G
Output
Control
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
3
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