HIT HD74HC93 Datasheet

HD74HC93

4-bit Binary Counter

Description

The HD74HC93 is a 4-bit ripple type counter consisting of four master/slave flip-flops that are internally
connected to provide separate divide-by-two and divide-by-eight sections. Each section has a separate
clock input which initiates state changes of the counter on the high-to-low clock transition. State changes
of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output
signals are subject to decoding spikes and should not be used as clocks or as strobes except when gated
with the clock of the HD74HC93. QA is the output of the divide-by-two section; QB, QC, and QD are the
binary outputs of the divide-by-eight section.

A gated AND asynchronous reset is provided which resets all the flip-flops.

Because the output from the divide-by-two section is not internally connected to the succeeding stages, the
devices may be operated in various counting modes:

1. A 4-bit rippl counter – The QA output must be externally connected to the clock B input. The input
count pulses are applied to the clock A inputl. Simultaneous divisions of 2, 4, 8 and 16 are performed at
the QA, QB, QC and QD outputs.

2. A 3-bit ripple counter – The input count pulses are applied to the clock B input. Simultaneous
frequency divisions of 2, 4 and 8 are available at the QB, QC and QD outputs. Independent use of the
first flip-flop is available if the reset function coincides with reset of the 3-bit ripple-through counter.

Features

• High Speed Operation: tpd (A to QA) = 13 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

HD74HC93

Function Table

Reset/Count Function Table

Reset Inputs Outputs
R

0(1)

R

0(2)

HHLLLL
L×Count
× L Count

BCD Count Sequence

Outputs

Count Q

0L L L L
1L L L H
2L L H L
3L L H H
4L H L L
5L H L H
6L H H L
7L H H H
8H L L L
9H L L H
10HL HL
11HL HH
12 H H L L
13 H H L H
14HHHL
15HHHH

Notes: Output QA is connected to input B for BCD count.

D

Q

D

Q

C

Q

C

Q

B

Q

B

Q

A

Q

A

2

Pin Arrangement

HD74HC93

B

0(1)

R

R0(2)

NC

Vcc

NC

NC

1

2

3

4

5

6

7

BA

R0(1)

QA

R0(2)

QD

QB

C

Q

(Top View)

14

13

12

11

10

A

NC

A

Q

QD

GND

B

Q

9

QC

8

3

HD74HC93

Block Diagram

Input A

Input B

C

Q

C

A

Q

R

C

Q

C

Q

R

C

Q

C

Q

R

Q

B

Q

C

Q

R0(1)
R0(2)

C

Q

C

D

Q

R

Q

4