HIT HD74HC590 Datasheet
HD74HC590
8-bit Binary Counter/Register (with 3-state outputs)
Description
This device each contains an 8-bit binary counter that feeds an 8-bit storage register. The storage register
has parallel outputs. Separate clocks are provided for both the binary counter and storage register. The
binary counter features a direct clear input CCLR and a count enable input C CKEN. For cascading a ripple
carry output R CO is provided. Expansion is easily accomplished by tying R CO of the first stage to CCKEN
of the second stage, etc.
Both the counter and register clocks are positive-edge triggered. If the user wishes to connect both clocks
together, the counter state will always be one count ahead of the register, Internal circuitry prevents
clocking from the clock enable.
Features
• High Speed Operation: tpd (RCK to Q) = 18.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
HD74HC590
Function Table
Inputs
G RCK CCLR CCKEN CCK Function
H X X X X Q output disabled
L X X X X Q output enabled
X X X X Contents of counter stored to register
X X X X No change in register
X X L X X Counter clear
XXHL Count up
XXHL No count
X X H H X No count
RCO = QA’•QB’•QC’•QD’•QE’•QF’•QG’•QH’• (CCKEN) (QA’ to QH’: Output of Internal Counter)
Pin Arrangement
1
Q
B VCC
2
C
Q
QD
3
QE
4
QF
5
QG
6
7
QH
GND
89
(Top view)
16
15
14
13
12
11
10
QA
C
RCK
CCKEN
CCK
CCLR
RCO
2
HD74HC590
Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage range V
Input voltage V
Output voltage V
Output current I
DC current drain per VCC, GND ICC, I
DC input diode current I
DC output diode current I
Power Dissipation per package P
CC
IN
OUT
OUT
GND
IK
OK
T
Storage temperature Tstg –65 to +150 °C
–0.5 to +7.0 V
–0.5 to VCC + 0.5 V
–0.5 to VCC + 0.5 V
±35 mA
±75 mA
±20 mA
±20 mA
500 mW
3
HD74HC590
Logic Diagram
T Q
CCK
CCLR
CCK
T Q
CCK
CCLR
CCK
T Q
CCK
CCLR
CCK
T Q
CCK
CCLR
CCK
T Q
CCK
CCLR
CCK
T Q
CCK
CCLR
CCK
T Q
CCK
CCLR
CCK
T Q
CCK
CCLR
CCK
REC Q
RCK
RCK
G
REC QBOut
RCK
RCK
G
REC QCOut
RCK
RCK
G
REC Q
RCK
RCK
G
REC Q
RCK
RCK
G
REC Q
RCK
RCK
G
REC Q
RCK
RCK
REC Q
RCK
RCK
G
Out
G
AOut
DOut
EOut
FOut
GOut
H
CCKEN
RCO
CCK
CCLR
RCK
G
4
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