HIT HD74HC4040 Datasheet
HD74HC4040
12-stage Binary Counter
Description
The HD74HC4040 is a 12-stage counter. This device is incremented on the falling edge (negative
transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset
input.
Features
• High Speed Operation: tpd (Clock to Q1) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
C Reset Outputs State
L No change
L Advance to next stage
X H All outputs are low
X: Irrelevant
HD74HC4040
Pin Arrangement
Block Diagram
Q
Q
Q
Q
Q
Q
Q
GND
1
12
Q
12
Q
Reset
Clock
1
Q
11
Q
10
Q
8
Q
9
2
6
3
5
4
7
5
4
6
3
7
2
Q
6
Q
5
Q
7
Q
4
Q
3
Q
2
8
16
15
14
13
12
11
10
V
CC
Q
11
Q
10
Q
8
Q
9
R
C
Q
9
1
(Top view)
Q
1
Q
2
Q
3
Q
10
Q
11
Q
12
Reset
Clock
C
C Q
R
Q
CRQ
C Q
CRQ
C Q
CRQ
C Q
CRQ
C Q
CRQ
C
2
Timing Diagram
HD74HC4040
Clock
Reset
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
10
Q
11
Q
12
1 2 4 8 16 32 64 128 256 512 1,024 2,048 4,096
1
2
3
4
5
6
7
8
9
3
Loading...