HIT HD74HC4020 Datasheet
HD74HC4020
14-stage Binary Counter
Description
The HD74HC4020 is a 14 stage counter. This device is incremented on the falling edge (negative
transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset
input.
Features
• High Speed Operation: tpd (Clock to Q1) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Clock Reset Outputs State
L No change
L Advance to next state
X H All output are low
HD74HC4020
Pin Arrangement
Block Diagram
Q
Q
Q
Q
Q
Q
Q
GND
1
12
Q
12
2
13
3
14
4
6
5
5
6
7
7
4
Q
13
Q
14
Q
6
Q
5
Q
7
Q
4
Q
11
Q
10
Q
8
Q
9
R
C
Q
1
8
16
15
14
13
12
11
10
9
V
CC
Q
11
Q
10
Q
8
Q
9
Reset
Clock
Q
1
(Top view)
Q
1
Q
4
Q
5
Q
12
Q
13
Q
14
Reset
Clock
C
C Q
R
Q
CRQ
C Q
CRQ
C Q
CRQ
C Q
CRQ
C Q
CRQ
C Q
2
Timing Diagram
HD74HC4020
Clock
Reset
Q
Q
Q
Q
Q
Q
Q
Q
10
Q
11
Q
12
Q
13
Q
14
1 2 4 8 16 32 64 128 256 512 1,024 2,048 4,096 8,192 16,384
1
4
5
6
7
8
9
3
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