HIT HD74HC240 Datasheet
HD74HC240
Octal Buffers/Line Drivers/Line Receivers
(with inverted 3-state outputs)
Description
The HD74HC240 is an inverting buffer and has two active low enables (1G and 2G). Each enable
independently controls 4 buffers. This device does not have schmitt trigger inputs.
Features
• High Speed Operation: tpd = 10 ns typ (CL = 50 pF)
• High Output Current: Fanout of 15 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs Output
G AY
HX Z
LH L
LL H
H : high level
L : low level
X : irrelevant
Z : off (high-impedance) state of a 3-state output
HD74HC240
Pin Arrangement
1G
1
1
20
VCC
1A
2Y
1A
2Y
1A
2Y
1A
2Y
GND
2
1
3
4
4
2
5
3
6
3
7
2
8
4
9
1
10
19
18
17
16
15
14
13
12
11
2G
1Y
2A
1Y
2A
1Y
2A
1Y
2A
1
4
2
3
3
2
4
1
(Top view)
Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage range V
Input voltage V
Output voltage V
DC current drain per pin I
DC current drain per VCC, GND ICC, I
DC input diode current I
DC output diode current I
Power dissipation per package P
CC
IN
OUT
OUT
GND
IK
OK
T
Storage temperature Tstg –65 to +150 °C
–0.5 to +7.0 V
–0.5 to VCC + 0.5 V
–0.5 to VCC + 0.5 V
±35 mA
±75 mA
±20 mA
±20 mA
500 mW
2
Logic Diagram
Input A
Strobe G
To three other
7 inverters
HD74HC240
One of 8
inverters
V
CC
Y
3
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