HD74HC155
Dual 2-to-4-line Decoders/Demultiplexers
Description
This circuit features dual 1-line-to-4-line demultiplexer with individual strobes and common binary-address
input. When both sections are enabled by the strobes, the common binary-address inputs sequentially
select and route associated input data to the appropriate output of each section. The individual strobes
permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted
through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8line demultiplexer without external gating.
Features
• High Speed Operation: tpd (A or B to Y) = 15 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
2-line-to-4-line Decoder/1-line-to-4-line Demultiplexer
Inputs
Select Strobe Data Outputs
B A 1G 1C 1Y
XXHXHHHH
LLLHLHHH
LH L H H L H H
HL L HHHL H
HHL HHHHL
XXXL HHHH
0
1Y
1
1Y
2
1Y
3
HD74HC155
Inputs
Select Strobe Data Outputs
B A 2G 2C 2Y
0
XXHXHHHH
LLLLLHHH
LH L L H L H H
HL L L HHL H
HHL L HHHL
XXXHHHHH
3-line-to-8-line Decoder/1-line-to-8-line Demultiplexer
Inputs Outputs
Select Strobe Data 0 1 2 3 4 5 6 7
CBAG 2Y02Y
XXXH HHHHHHHH
LLLL L HHHHHHH
LLHL HL HHHHHH
LHLL HHLHHHHH
LHHL HHHLHHHH
HLLL HHHHL HHH
HLHL HHHHHLHH
HHLL HHHHHHL H
HHHL HHHHHHHL
Notes: 1. C: inputs 1C and 2C connected together
2. G: inputs 1G and 2G connected together
3. X: irrelevant
2Y
1
2
2Y
3
2Y
1
1Y
2Y
2
1Y
0
1
1Y
2Y
3
1Y
2
3
2