HIT HD74HC137 Datasheet
HD74HC137
3-to-8-line Decoder/Demultiplexer with Address Latch
Description
The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When
GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As
long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control
the state of the outputs independently of the select or latch-enable inputs.
All of the outputs are high unless G1 is high and G2 is low. The HD74HC137 is ideally suited for the
implementation of glitchfree decoders in stored-address applications in bus oriented systems.
Features
• High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 V to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
HD74HC137
Function Table
Inputs
Enable Select Outputs
GL G
XXHXXXHHHHHHHH
XLXXXXHHHHHHHH
LHLLLL LHHHHHHH
LHLLLHHLHHHHHH
LHLLHLHHLHHHHH
LHLLHHHHHLHHHH
LHLHLLHHHHLHHH
LHLHLHHHHHHLHH
LHLHHLHHHHHHLH
LHLHHHHHHHHHHL
H H L X X X Output Corresponding to stored address L; all Others. H
G
1
CBAY0Y1Y2Y3Y4Y5Y6Y
2
7
Pin Arrangement
GL
G
G1
Y7
GND
1
A
A
2
B
3
C
4
2
5
6
7
B
C
GL
G
G1
Y7
Y0
Y1
Y2
2
Y3
Y4
Y5
6
Y
8
16
15
14
13
12
11
10
V
CC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
9
(Top view)
2
Block Diagram
A
HD74HC137
Y
0
Y
1
GL
B
C
2
G
G
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
3
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