HIT HD74CDCF2510B Datasheet

HD74CDCF2510B

140 MHz, 0 to 85°C Operation

3.3-V Phase-lock Loop Clock Driver

ADE-205-225F (Z)

7th. Edition

January 2000

Description

The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
HD74CDCF2510B operates at 3.3 V VCC and is designed to drive up to five clock loads per output.

Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are
adjusted to 50 percent independent of the duty cycle at the input clock. Bank of outputs can be enabled or
disabled via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency
with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the HD74CDCF2510B does not require external RC networks.
The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, HD74CDCF2510B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.

Features

• Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”

• Phase-lock loop clock distribution for synchronous DRAM applications

• External feedback (FBIN) pin is used to synchronize the outputs to the clock input

• No external RC network required

• Support spread spectrum clock (SSC) synthesizers

• Supports frequencies up to 140 MHz

• 0 to 85°C operating range

HD74CDCF2510B

Function Table

Inputs Outputs
G CLK 1Y (0:9) FBOUT

XLLL
LHLH
HHHH

H : High level
L : Low level
X : Immaterial

Pin Arrangement

AGND

V

CC

1Y0
1Y1

1Y2
GND
GND

1Y3

1Y4

V

CC

FBOUT

1
2
3
4
5

6
7

8

9

10

G

11
12

(Top view)

24
23
22
21
20
19
18
17
16
15
14
13

CLK
AV

CC

V

CC

1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
V

CC

FBIN

2

HD74CDCF2510B

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage V
Input voltage
Output voltage

*1

*1, 2

Input clamp current I
Output clamp current I
Continuous output current I
Supply current ICC or I
Maximum power dissipation

at Ta = 55°C (in still air)

*3

Storage temperature T

CC

V

I

V

O

IK

OK

O

GND

P

T

stg

Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C and
a board trace length of 750 mils.

–0.5 to 4.6 V
–0.5 to 6.5 V
–0.5 to VCC +0.5 V
–50 mA VI < 0

±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V

CC

±100 mA

0.7 W

–65 to +150 °C

CC

Recommended Operating Conditions

Item Symbol Min Typ Max Unit Conditions

Supply voltage V
Input voltage V

Output current I

Operating temperature T

CC

IH

V

IL

V

I

OH

I

OL

a

Note: Unused inputs must be held high or low to prevent them from floating.

3.0 — 3.6 V

2.0 — — V
— — 0.8
0—V

CC

— — –12 mA
——12
0—85°C

3

HD74CDCF2510B

Logic Diagram

11

G

24

CLK

CC

13

23

FBIN

AV

PLL

3

4

5

8

9

15

16

17

20

21

12

1Y0
1Y1

1Y2

1Y3

1Y4

1Y5
1Y6

1Y7

1Y8

1Y9

FBOUT

4