HIT HD74CDC2509B Datasheet
HD74CDC2509B
3.3-V Phase-lock Loop Clock Driver
ADE-205-218F (Z)
7th. Edition
October 1999
Description
The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
HD74CDC2509B operates at 3.3 V VCC and is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input
clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the
G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the
outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDC2509B does not require external RC networks. The
loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDC2509B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• Phase-lock loop clock distribution for synchronous DRAM applications
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input
• No external RC network required
• Support spread spectrum clock (SSC) synthesizers
Note: Only by a change of a suffix (A to B) for standardization, there isn’t any change of the product.
HD74CDC2509B
Function Table
Inputs Outputs
1G 2G CLK 1Y (0:4) 2Y (0:3) FBOUT
XXLLLL
LLHLLH
LHHL HH
HLHHL H
HHHHHH
H : High level
L : Low level
X : Immaterial
Pin Arrangement
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
1G
FBOUT
10
11
12
1
2
3
4
5
6
7
8
9
(Top view)
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AV
CC
V
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V
CC
2G
FBIN
2
HD74CDC2509B
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
Supply voltage V
Input voltage
Output voltage
*1
*1, 2
Input clamp current I
Output clamp current I
Continuous output current I
Supply current ICC or I
Maximum power dissipation
at Ta = 55°C (in still air)
*3
Storage temperature T
CC
V
I
V
O
IK
OK
O
GND
P
T
stg
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
–0.5 to 4.6 V
–0.5 to 6.5 V
–0.5 to VCC +0.5 V
–50 mA VI < 0
±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V
CC
±100 mA
0.7 W
–65 to +150 °C
CC
Recommended Operating Conditions
Item Symbol Min Typ Max Unit Conditions
Supply voltage V
Input voltage V
Output current I
Operating temperature T
CC
IH
V
IL
V
I
OH
I
OL
a
Note: Unused inputs must be held high or low to prevent them from floating.
3.0 — 3.6 V
2.0 — — V
— — 0.8
0—V
CC
— — –12 mA
——12
0—85°C
3
HD74CDC2509B
Logic Diagram
11
1G
14
2G
24
CLK
CC
13
23
FBIN
AV
PLL
3
4
5
8
9
21
20
17
16
12
1Y0
1Y1
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
FBOUT
4
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