HIT HD74BC245A Datasheet
HD74BC245A
Octal Bus Transceivers With 3 State Outputs
ADE-205-008A (Z)
Rev. 1
March 1993
Description
The HD74BC245A provides high drivability and operation equal to or better than high speed bipolar
standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5
of high speed bipolar logic IC, when the frequency is 10 MHz. The device has ten buffers with three state
outputs in a 20 pin package. Each device has an active low enable input G and a direction control input
DiR. When DiR is high, data flows from the A inputs to the B outputs. When DiR is low, data flows from
the B inputs to the A outputs. When G is high, disables both A and B ports by placing then in a high
impedance.
Features
• Input/Output are at high impedance state when power supply is off.
• Built in input pull up circuit can make input pins be open, when not used.
• TTL level input
• Wide operating temperature range
Ta = –40 to + 85°C
Function Table
Control Inputs
G DiR Operation
L L B data to A bus
L H A data to B bus
HX Z
H : High level
L : Low level
Z : High impedance
HD74BC245A
Pin Arrangement
DiR
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
5
6
7
8
9
10
19
18
17
16
15
14
13
12
11
20
V
G
B1
B2
B3
B4
B5
B6
B7
B8
CC
(Top view)
Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage V
Input diode current I
Input voltage V
Output voltage V
Off state output voltage V
CC
IK
IN
OUT
OUT(off)
Storage temperature Tstg –65 to +150 °C
Note: 1. The absolute maximum ratings are values which must not individually be exceeded, and
furthermore, no two of which may be realized at the same time.
–0.5 to +7.0 V
±30 mA
–0.5 to +7.5 V
–0.5 to +7.5 V
–0.5 to +5.5 V
2
HD74BC245A
Recommended Operating Conditions
Item Symbol Min Typ Max Unit
Supply voltage V
Input voltage V
Output voltage V
CC
IN
OUT
Operating temperature Topr –40 — 85 °C
Input rise/fall time*
1
tr, t
f
Note: 1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Logic Diagram
DiR
A1 B1
4.5 5.0 5.5 V
0—VCCV
0—VCCV
0 — 8 ns/V
G
A2
A3
A4
A5
A6
A7
A8
B2
B3
B4
B5
B6
B7
B8
3
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