HIT HD74ALVCH16543 Datasheet

HD74ALVCH16543

16-bit Registered Transceivers with 3-state Outputs

ADE-205-169A (Z)

2nd. Edition

December 1999

Description

The HD74ALVCH16543 can be used as two 8-bit transceivers or one 16-bit transceiver. Separate latch
enable (LEAB or LEBA) and output enable (OEAB or OEBA) inputs are provided for each register to
permit independent control in either direction of data flow. The A to B enable (CEAB) input must be low
in order to enter data from A or to output data from B. If CEAB is low and LEAB is low, the A to B
latches are transparent; a subsequent low to high transition of LEAB puts the A latches in the storage mode.
With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present at the output
of the A latches. Data flow from B to A is similar but requires using CEBA, LEBA, and OEBA. Active
bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Features

• VCC = 2.3 V to 3.6 V

• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)

• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)

• High output current ±24 mA (@VCC = 3.0 V)

• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors

HD74ALVCH16543

Function Table

*1

Inputs Output B
CEAB LEAB OEAB A

HXXXZ
XXHXZ
LHLXB

*2

0

LLLLL
LLLHH

H : High level
L : Low level
X : Immaterial
Z : High impedance
Notes 1. A to B data flow is shown; B to A flow control is the same except that it uses CEBA, LEBA, and

OEBA.

2. Output level before the indicated steady state input conditions were established.

2

Pin Arrangement

HD74ALVCH16543

1OEAB

1LEAB

1CEAB

GND

1A1
1A2

V

CC

1A3
1A4

1A5

GND

1A6
1A7

1A8
2A1

2A2
2A3

GND

2A4
2A5
2A6
V

CC

2A7
2A8

GND

2CEAB

2LEAB

2OEAB

10
11

12
13
14

15
16

17
18

19

20
21
22
23
24
25
26
27
28

1OEBA

1
2

3
4
5

6
7

8

9

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1LEBA
1CEBA
GND
1B1
1B2

V

CC

1B3
1B4

1B5
GND

1B6
1B7

1B8
2B1
2B2

2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2CEBA
2LEBA
2OEBA

(Top view)

3

HD74ALVCH16543

Absolute Maximum Ratings

Item Symbol Ratings Unit Conditions

Supply voltage V
Input voltage

Output voltage

*1, 2

*1, 2

Input clamp current I
Output clamp current I
Continuous output current I

Maximum power dissipation
at Ta = 55°C (in still air)

*3

CC

V

I

V

O

IK

OK

O

P

T

Storage temperature Tstg –65 to 150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage

to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.

1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.

–0.5 to 4.6 V
–0.5 to 4.6 V Except I/O ports
–0.5 to VCC +0.5 I/O ports
–0.5 to VCC +0.5 V
–50 mA VI < 0

±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V

CC

±100
1 W TSSOP

CC

Recommended Operating Conditions

Item Symbol Min Max Unit Conditions

Supply voltage V
Input voltage V
Output voltage V
High level output current I

Low level output current I

CC

I

O

OH

OL

Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature Ta –40 85 °C

Note: Unused control inputs must be held high or low to prevent them from floating.

4

2.3 3.6 V
0VCCV
0VCCV
— –12 mA VCC = 2.3 V
— –12 VCC = 2.7 V
— –24 VCC = 3.0 V
—12mAV
—12 V
—24 V

= 2.3 V

CC

= 2.7 V

CC

= 3.0 V

CC