HIT HD74ALVCH162821 Datasheet
HD74ALVCH162821
3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs
ADE-205-186A (Z)
2nd. Edition
September 1997
Description
The HD74ALVCH162821 can be used as two 10-bit flip flops or one 20-bit flip flop. The 20 flip flops are
edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides
true data at the Q outputs. A buffered output enable (OE) input can be used to place the ten outputs in
either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the
outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive
provide the capability to drive bus line without need for interface or pullup components. The output enable
(OE) input does not affect the internal operations of the flip flops. Old data can be retained or new data can
be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold
unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 mA,
include 26 Ω resistors to reduce overshoot and undershoot.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
HD74ALVCH162821
Function Table
Inputs Output Q
OE CLK D
L ↑ HH
L↑ LL
L H or L X Q
HXXZ
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Note: 1. Output level before the indicated steady state input conditions were established.
*1
0
2
Pin Arrangement
HD74ALVCH162821
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1CLK
1
2
3
4
5
6
7
8
9
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2CLK
(Top view)
3
HD74ALVCH162821
Absolute Maximum Ratings
Item Symbol Ratings Unit Conditions
V
CC
Input voltage
Output voltage
Input clamp current I
Output clamp current I
Continuous output current I
VCC, GND current / pin ICC or I
Maximum power dissipation
at Ta = 55°C (in still air)
*1
*1, 2
*3
V
I
V
O
IK
OK
O
GND
P
T
Storage temperature Tstg –65 to 150 °C
Notes: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C
and a board trace length of 750 mils.
–0.5 to 4.6 V
–0.5 to 4.6 V
–0.5 to VCC +0.5 V
–50 mA VI < 0
±50 mA VO < 0 or VO > V
±50 mA VO = 0 to V
CC
±100 mA
1 W TSSOP
CC
Recommended Operating Conditions
Item Symbol Min Max Unit Conditions
Supply voltage V
Input voltage V
Output voltage V
High level output current I
Low level output current I
CC
I
O
OH
OL
Input transition rise or fall rate ∆t / ∆v 0 10 ns / V
Operating temperature Ta –40 85 °C
Note: Unused control inputs must be held high or low to prevent them from floating.
2.3 3.6 V
0VCCV
0VCCV
—–6mAV
—–8 V
= 2.3 V
CC
= 2.7 V
CC
— –12 VCC = 3.0 V
— 6 mA VCC = 2.3 V
—8 V
—12 V
= 2.7 V
CC
= 3.0 V
CC
4
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