HIT HD74ACT374, HD74AC374 Datasheet

HD74AC374/HD74ACT374

Octal D-Type Flip-Flops with 3-State Output

Description

The HD74AC374/HD74ACT374 is a high-speed, low-power octal D-type flip-flop featuring separate D­type inputs for each flip-flop and 3-state outputs for bus-oriented applications. A buffered Clock (CP) and
Output Enable (OE) are common to all flip-flops.

Features

• Buffered Positive Edge-Triggered Clock

• 3-State Outputs for Bus-Oriented Applications

• Outputs Source/Sink 24 mA

• See HD74AC273/HD74ACT273 for Reset Version

• See HD74AC373/HD74ACT373 for Transparent Latch Version

• See HD74AC574/HD74ACT574 for Broadside Pinout Version

• See HD74AC564/HD74ACT564 for Broadside

• Pinout Version with Inverted Outputs

• HD74ACT374 has TTL-Compatible Inputs

HD74AC374/HD74ACT374

Pin Arrangement

1

OE

20

V

CC

Logic Symbol

2

0

O

D0

3

D1

4

O1

5

O2

6

7

D2

D3

8

O3

9

10 11

Gnd

(Top view)

19

18

17

16

15

14

13

12

O7

D7

D6

O6

O5

D

D4

O4

CP

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Pin Names

D0 – D7Data Inputs
CP Clock Pulse Input
OE 3-State Output Enable Input
O0 – O73-State Outputs

2

D

0 D2

CP
OE

O0 O2

D1

O1

D3

D4 D6

O3

O4 O6

D5 D7

O5 O7

HD74AC374/HD74ACT374

Functional Description

The HD74AC374/HD74ACT374 consists of eight edge-triggered flip-flops with individual D-type inputs
and 3-state true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The
eight flip-flops will store the state of their individual D inputs that meet the setup and hold time
requirements on the Low-to-High Clock (CP) transition. With the Output Enable (OE) Low, the contents
of the eight flip-flops are available at the outputs. When the OE is High, the outputs go to the high
impedance state. Operation of the OE input does not affect the state of the flip-flops.

Truth Table

Inputs Outputs
D

n

H LH
L LL
XX H Z

H : High Voltage Level
L : Low Voltage Level
X : Immaterial
Z : High Impedance

: Low-to-High Transition

CP OE O

n

Logic Diagram

D6

CP

D

QQ

O6

CP

OE

D0

CP

D

QQ

O0

D1

CP

D

QQ

O1

D2

CP

D

QQ

O2

D3

CP

D

QQ

O3

D4

CP

D

QQ

O4

D5

CP

D

QQ

O5

Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.

D7

CP

D

QQ

O7

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HD74AC374/HD74ACT374

DC Characteristics (unless otherwise specified)

Item Symbol Max Unit Condition

Maximum quiescent supply current I

Maximum quiescent supply current I

Maximum ICC/input (HD74ACT374) I

CC

CC

CCT

AC Characteristics: HD74AC374

80 µAV

8.0 µAV

1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V,

= VCC or ground, VCC = 5.5 V,

IN

Ta = Worst case

= VCC or ground, VCC = 5.5 V,

IN

Ta = 25°C

Ta = Worst case

Item Symbol V

Maximum clock f

max

Ta = +25°C
C

= 50 pF

L

(V)*1Min Typ Max Min Max Unit

CC

3.3 60 110 — 60 — MHz

Ta = –40°C to +85°C
CL = 50 pF

frequency 5.0 100 155 — 100 —
Propagation delay t
CP to O

n

Propagation delay t
CP to O

n

Output enable time t

PLH

PHL

PZH

3.3 1.0 11.0 13.5 1.0 15.5 ns

5.0 1.0 8.0 9.5 1.0 10.5

3.3 1.0 10.0 12.5 1.0 14.0 ns

5.0 1.0 7.0 9.0 1.0 10.0

3.3 1.0 9.5 11.5 1.0 13.0 ns

5.0 1.0 7.0 8.5 1.0 9.5

Output enable time t

PZL

3.3 1.0 9.0 11.5 1.0 13.0 ns

5.0 1.0 6.5 8.5 1.0 9.5

Output disable time t

PHZ

3.3 1.0 10.5 12.5 1.0 14.5 ns

5.0 1.0 8.0 11.0 1.0 12.5

Output disable time t

PLZ

3.3 1.0 8.0 11.5 1.0 12.5 ns

5.0 1.0 6.5 8.5 1.0 10.0

Note: 1. Voltage Range 3.3 is 3.3 V ± 0.3 V

Voltage Range 5.0 is 5.0 V ± 0.5 V

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