HIT HD74ACT138, HD74AC138 Datasheet
HD74AC138/HD74ACT138
1-of-8 Decoder/Demultiplexer
Description
The HD74AC138/HD74ACT138 is a high-speed 1-of-8 decoder/demultiplexer. This device is ideally
suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow
parallel expansion to a 1-of-24 decoder using just three HD74AC138/HD74ACT138 devices or a 1-of-32
decoder using four HD74AC138/HD74ACT138 devices and one inverter.
Features
• Demultiplexing Capability
• Multiple Input Enable for Easy Expansion
• Active LOW Mutually Exclusive Outputs
• Outputs Source/Sink 24 mA
• HD74ACT138 has TTL-Compatible Inputs
HD74AC138/HD74ACT138
Pin Arrangement
Logic Symbol
1
0
A
A1
2
A2
3
E1
4
E2
5
E3
6
7
O7
GND
8
(Top view)
A0 A1 A2 E1
16
15
14
13
12
11
10
9
E2 E3
V
O0
O1
O2
O3
O4
O5
O6
CC
Pin Names
A0 to A2Address Inputs
E1 to E
E
3
O0 to O 7Outputs
2
Enable Inputs
2
Enable Input
O0 O1 O2 O3 O4 O5 O6 O7
HD74AC138/HD74ACT138
Functional Description
The HD74AC138/HD74ACT138 high-speed 1-of-8 decoder/demultiplexer accepts three binary weighted
inputs (A0, A1, A2) and, when enabled, provides eight mutually exclusive active-LOW outputs (O0 to O7).
The HD74AC138/HD74ACT138 features three Enable inputs, two active-Low (E1, E2) and one active-High
(E3). All outputs will be High unless E1 and E2 are Low and E3 is High. This multiple enabled function
allows easy parallel expansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four
HD74AC138/HD74ACT138 devices and one inverter (See Figure a). The HD74AC138/HD74ACT138
can be used as an 8-output demultiplexer by using one of the active Low Enable inputs as the data input
and the other Enable inputs as strobes. The Enables inputs which are not used must be permanently tied to
their appropriate active-High or active-Low state.
Truth Table
Inputs Outputs
E
E
1
HXXXXXHHHHHHHH
XHXXXXHHHHHHHH
XXL XXXHHHHHHHH
LLHLLL LHHHHHHH
LLHHLLHLHHHHHH
LLHLHLHHLHHHHH
LLHHHLHHHLHHHH
LLHLLHHHHHLHHH
LLHHLHHHHHHL HH
LLHLHHHHHHHHLH
LLHHHHHHHHHHHL
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
E
2
A
3
A
0
A
1
O
2
O
0
O
1
O
2
O
3
O
4
O
5
O
6
7
3
HD74AC138/HD74ACT138
Logic Diagram
A2 A1 A0 E1
E2 E3
O0O1O2O3O4O5O6O7
Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.
Figure a: Expansion of 1-of-32 Decoding
A0
A1
A2
A3
A4
A0 A1 A2 E
O0 O1 O2O3O4 O5O6 O7
O
0 O31
123
E
H
123
A0 A1 A2
O0 O1 O2O3O4 O5O6 O7
E
A0 A1 A2
O0 O1 O2O3O4 O5O6 O7
123
E
A0 A1 A2
O
0 O1 O2 O3O4 O5 O6O7
4
’04
123
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