HIT HD74AC74 Datasheet
HD74AC74
Dual D-Type Positive Edge-Triggered Flip-Flop
Description
The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q,
Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse.
Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time
of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input
is locked out and information present will not be transferred to the outputs until the next rising edge of the
Clock Pulse input.
Features
Asynchronous Inputs:
Low input to SD (Set) sets Q to High level
Low input to CD (Clear) sets Q to Low level
Clear and Set are independent of clock
Simultaneous Low on CD and SD makes both Q and Q High
• Outputs Source/Sink 24 mA
HD74AC74
Pin Arrangement
Logic Symbol
C
D1
D
CP
S
D1
Q
Q
GND
1
CP
D
1
2
1
3
1
1
S
D1
C
D1
Q
Q
1
1
4
D
CP
2
CD2S
Q
2
2
D2
Q
2
5
1
6
1
7
14
13
12
11
10
V
CC
C
D2
D
2
CP
2
S
D2
Q
9
2
Q
8
2
(Top view)
Pin Names
D1, D
2
CP1, CP
CD1, C
SD1, S
Q1, Q1, Q2, Q 2Outputs
2
D2
D2
D
1
CP
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
S
D1
Q
1
1
Q
1
C
D1
D
CP
S
D2
Q
2
2
2
Q
2
C
D2
2
HD74AC74
Truth Table (Each Half)
Inputs Outputs
S
D
C
D
LH X X H L
HL X X L H
LL X X H H
HH HHL
HH LLH
HHLXQ
H : High Voltage Level
L : Low Voltage Level
X : Immaterial
: Low-to-High Clock Transition
(Q0) : Previous Q (Q) before Low-to-High Transition of Clock
Q
0
Logic Diagram
CP D Q Q
0
Q
0
S
D
D Q
CP
C
D
Please note that this diagram is provised only for the understanding of logic operations and should not be
used to estimate propagation delays.
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
CC
CC
40 µAV
4.0 µAV
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Q
3
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