HIT HD74AC175 Datasheet

HD74AC175

Quad D-Type Flip-Flop

Description

The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements
where clock and clear inputs are common. The information on the D inputs is stored during the Low-to­High clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset
input resets all flip-flops, independent of the Clock or D inputs, when Low.

Features

• Edge-Triggered D-Type Inputs

• Buffered Positive Edge-Triggered Clock

• Asynchronous Common Reset

• True and Complement Output

• Outputs Source/Sink 24 mA

HD74AC175

Pin Arrangement

Logic Symbol

MR

Q

Q0

D0

D1

Q1

Q1

GND

1

0

2

3

4

5

6

7

8

(Top view)

0

D

CP

D1 D2 D3

16

15

14

13

12

11

10

CC

V

Q3

Q3

D3

D2

Q2

Q2

9

CP

Pin Names

D0 to D3Data Inputs
CP Clock Pulse Input
MR Master Reset Input
Q0 to Q3True Outputs

Q0 to Q 3Complement Outputs

2

MR

Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3

HD74AC175

Functional Description

The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q
outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their
individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and Q outputs to
follow. A Low input on the Master Reset (MR) will force all Q outputs Low and Q outputs High
independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a
common Master Reset and Clock are acceptable.

Truth Table

Inputs Outputs

, MR = H @ t

@ t

n

Dn Qn Qn
LL H
HH L

H : High Voltage Level
L : Low Voltage Level
t

: Bit Time before Clock Pulse

n

t

: Bit Time after Clock Pulse

n + 1

n+1

Logic Diagram

D3CPMR

D

Q

CP

Q

CD

Q3Q3

Please note that this diagram is provided only for the understanding of logic operations and should not be
used to estimate propagation delays.

D2

D

CP

Q

Q

CD

Q2Q2

D1

D

CP

Q

Q

CD

Q1Q1

D0

D

CP

Q

Q

CD

Q0Q0

3