HIT HD74ACT107, HD74AC107 Datasheet
HD74AC107/HD74ACT107
Dual JK Flip-Flop (with Separate Clear and Clock)
Description
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop.
Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the
coupling transistors which connect the master and slave sections. The sequence of operation is as follows:
1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs;
4) transfer information from master to slave.
Features
• Outputs Source/Sink 24 mA
• HD74ACT107 has TTL-Compatible Inputs
Pin Arrangement
J
Q1
Q1
K
Q
Q
GND
1
1
2
3
4
1
5
2
6
2
7
(Top view)
14
13
12
11
10
V
CC
C
D1
CP
1
K
2
C
D2
CP
9
2
J
8
2
HD74AC107/HD74ACT107
Logic Symbol
Q
1
Q
1
38
= Pin14
V
CC
9
112
J
2
CP
K
Q
2
Q
2
C
D2
6
2
5
2
12
1
J
1
CP
1
4
K
1
C
D1
13 10
GND = Pin7
Pin Names
J1, J2, K1, K
CP1, CP
CD1, C
2
D2
Q1, Q2, Q1, Q 2Outputs
Data Inputs
2
Clock Pulse Inputs (Active Falling Edge)
Direct Clear Inputs (Active Low)
Truth Table
Inputs Outputs
@ t
n
JK Q
LL Qn
LH L
HL H
HH Qn
H : High Voltage Level
L : Low Voltage Level
t
: Bit time before clock pulse.
n
t
: Bit time after clock pulse.
n + 1
@ t
n + 1
2
Logic Diagram
HD74AC107/HD74ACT107
C
D
J
#CP
#CP
K
CP
#CP
CP
CP
CP
CP
#CP
CP
CP
DC Characteristics (unless otherwise specified)
Item Symbol Max Unit Condition
Maximum quiescent supply current I
Maximum quiescent supply current I
Maximum additional ICC/input
(HD74ACT107)
CC
CC
I
CCT
80 µAV
8.0 µAV
1.5 mA VIN = VCC – 2.1 V, VCC = 5.5 V
= VCC or ground, VCC = 5.5 V,
IN
Ta = Worst case
= VCC or ground, VCC = 5.5 V,
IN
Ta = 25°C
Ta = Worst case
Q
Q
3
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