HIT HD155111F Datasheet

HD155111F

RF Single-chip Linear IC for PCN Cellular Systems

ADE-207-257 (Z)

1st Edition

August 1998

Description

The HD155111F was developed for PCN (DCS1800) cellular systems, and integrates most of the functions
of a transceiver. The HD155111F incorporates the bias circuit for a RF LNA, a 1st mixer, 1st-IF amplifier,
2nd mixer, AGC amplifier and an IQ quadrature demodulator for the receiver, and an IQ quadrature
modulator and offset PLL for the transmitter. Also, on chip are the dividers for the 1st & 2nd local
oscillator signals and 90˚ phase splitter. Moreover the HD155111F includes control circuits to implement
power saving modes. These functions can operate down to 2.7 V and are housed in a 48-pin LQFP SMD
package.

Hence the HD155111F can form a small size transceiver handset for PCN by adding a PLL frequency
synthesizer IC, a power amplifier and some external components. See page 7 “Configuration”.

The HD155111F is fabricated using a 0.6 µm double-polysilicon Bi-CMOS process.

Functions

Receiver (RX)

• Low Noise Amplifier (LNA) bias circuit

• 1st mixer

• IF amplifier

• 2nd mixer

• Automatic gain control amplifier (AGC)

• IQ demodulator with 90° phase splitter

Transmitter (TX)

• IQ modulator with 90° phase splitter

• Offset PLL
 Down converter
 Phase comparator
 TX VCO driver

HD155111F

Others

• IF dividers

• Power saving circuit

• IFVCO

Features

• Highly integrated RF processing for hand-portables

• Wide operating frequency

RX:

 RF: 1805 to 1880 MHz
 1st IF: 130 to 300 MHz
 2nd IF: 26 to 60 MHz

TX:

 RF: 1710 to 1785 MHz
 IF: 120 to 180 MHz

• Offset PLL architecture reduces TX spurious

• Low current consumption (Vcc = 3 V)

RX mode: 42.5 mA Typ (including IFVCO current (2.5 mA Typ)) + LNA transistor current (5.6 mA
Typ)

TX mode: 38.0 mA Typ (including IFVCO current (2.5 mA Typ))
Idle mode: 1 µA Typ

• Operating supply voltage:
 Phase comparator and TX VCO driver circuits: 2.7 to 5.25 V
 Other blocks: 2.7 to 3.6 V

• Operating temperature range: –20 to +75°C

• 48 pin SMD Low Profile Quad Flat Package (LQFP): FP-48

HD155111F

Pin Arrangement

The HD155111F is housed in a 48-pin LQFP SMD package to which is suitable for applications where
space is limited. “Pin Functions” shows the arrangement and roles assigned for each pin of the
HD155111F.

MIX1IN

MIX1INB

GNDMIX1

VCCMIX1

RFLOIN

MIX1OUTB

MIX1OUT

VCCIF

GNDIF

IFIN

IFINB

MIX2O

373839404142434445464748

POONRX1

1

36

MIX2OB

POONRX2

RFOUT

VCCLNA

GNDLNA

RFIN

POONTX

VCCPLL

GNDPLL

VCOIN

VCCCOMP

PLLOUT

2

3

4

5

6

7

8

9

10

11

12

QINB

ICURAD

QIN

IINB

181716151413

IIN

MODB

(Top View)

MOD

VCCIQ

IFLO

GNDIQ

35

34

33

32

31

30

29

28

27

26

25

242322212019

IFVCOI

IFVCOO

GNDAGC

VCCAGC

AGCOUT

AGCOUTB

VCCDIV

GNDDIV

VCONT

IOUT

IOUTB

QOUT

QOUTB

HD155111F

Pin Functions

Pin
No. Symbol

1 POONRX1 Input PO wer ON for RX1 If ‘H’, LNA and MIX1 are active.

2 POONRX2 Input PO wer ON for RX2 LNA and MIX1 don’t care.

3 RFOUT Output RF signal OUT put Open collector type output of LNA.

4 VCCLNA Vcc VCC of LNA block Power supply of LNA
5 GNDLNA Gnd GND of LNA block Ground of LNA
6 RFIN Input RF signal IN put Input of LNA.

7 POONTX Input PO wer ON for TX If ‘H’, the blocks for transmitter are active.

8 VCCPLL Vcc VCC of O PLL block Power supply for offset PLL except phase

9 GNDPLL Gnd GND of O PLL block Ground of offset PLL
10 VCOIN Input VCO signal IN put Input of Tx. VCO signal
11 VCCCOMP Vcc VCC of phase

12 PLLOUT Output O PLL OUT put Current output to control and modulate Tx. VCO

13 ICURAD Input I CUR rent AD just This pin should be connected an external R to

14 QINB Input Q signal IN put B ar Q negative signal input of IQ quadrature modulator
15 QIN Input Q signal IN put Q positive signal input of IQ quadrature modulator
16 IINB Input I signal IN put B ar I negative signal input of IQ quadrature modulator
17 IIN Input I signal IN put I positive signal input of IQ quadrature modulator
18 MODB Output MOD ulator output B ar Negative output of IQ quadrature modulator
19 MOD Output MOD ulator output Positive output of IQ quadrature modulator
20 VCCIQ Vcc VCC of IQ block Power supply of IQ block
21 IFLO Input/

22 GNDIQ Gnd GND of IQ block Ground of IQ block
23 IFVCOO Output IFVCO O utput Emitter of IFVCO transistor
24 IFVCOI Input IFVCO I nput Base of IFVCO transistor

Input/
Output Meaning of symbol Function

Other receiver blocks don’t care.

If ‘H’, Other receiver blocks are active.

The collector of LNA transistor.

The base of LNA transistor

The reciver blocks don’t care.

comparator

Power supply for just phase comparator of offset

Output

COMP arator

IF LO cal signal
input/output

PLL

This pin should be connected external loop filter.

determine charge pump current of phase
comparator

IF local signal input to be fed to divider

Pin Function (cont)

HD155111F

Pin
No. Symbol

25 QOUTB Output Q signal OUT put B ar Q negative signal output of IQ quadrature

26 QOUT Output Q signal OUT put Q positive signal output of IQ quadrature

27 IOUTB Output I signal OUT put B ar I negative signal output of IQ quadrature

28 IOUT Output I signal OUT put I positive signal output of IQ quadrature

29 VCONT Input V oltage of AGC

30 GNDDIV Gnd GND of DIV ider block Ground of divider to make IF local signals
31 VCCDIV Vcc VCC of DIV ider block Power supply of divider to make IF local signals
32 AGCOUTB Output AGC OUT put B ar AGC negative signal output to be fed to IQ

33 AGCOUT Output AGC OUT put AGC positive signal output to be fed to IQ

34 VCCAGC Vcc VCC of AGC block Power supply of AGC
35 GNDAGC Gnd GND of AGC block Ground of AGC
36 MIX2OB Output MIX2 O utput B ar 2nd mixer (MIX2) negative signal output to be fed

37 MIX2O Output MIX2 O utput 2nd mixer (MIX2) positive signal output to be fed to

38 IFINB Input 1st IF signal IN put B ar IFAMP negative signal input for 1st IF signal
39 IFIN Input 1st IF signal IN put IFAMP positive signal input for 1st IF signal
40 GNDIF Gnd GND of IF MIX2 block Ground of IFAMP and 2nd mixer (MIX2)
41 VCCIF Vcc VCC of IF MIX2 block Power supply of IFAMP and 2nd mixer (MIX2)
42 MIX1OUT Output MIX1 O utput 1st mixer (MIX1) positive signal output
43 MIX1OUTB Output MIX1 O utput B ar 1st mixer (MIX1) negative signal output
44 RFLOIN Input RF LO cal signal IN put RF 1st local signal input to be fed to 1st mixer

45 VCCMIX1 Vcc VCC of MIX1 block Power supply of 1st mixer (MIX1)
46 GNDMIX1 Gnd GND of MIX1 block Ground of 1st mixer (MIX1)
47 MIX1INB Input MIX1 I nput B ar 1st mixer (MIX1) negative signal input
48 MIX1IN Input MIX1 I nput 1st mixer (MIX1) positive signal input

Input/
Output Meaning of symbol Function

demodulator

demodulator

demodulator

demodulator
The DC voltage input to control the power gain of

CONT rol

AGC

quadrature demodulator

quadrature demodulator

to AGC

AGC

(MIX1) and the down converter of offset PLL

HD155111F

Block Diagram

225 MHz

MIX2OB

GNDAGC

36

45 MHz

MIX2O

IFINB

IFIN

GNDIF

Vref

VCCIF

Vref

MIX1OUT

MIX1OUTB
Rx. 1617 MHz
Tx. 1612 MHz

RFLOIN

VCCMIX1

GNDMIX1

35

)
Mix2

(

(IF)

Vref

*2

(Mix1)

45 MHz

VCCAGC

AGOUT

34

1617 MHz

AGCOUTB

33

32

45 MHz

)
AGC

Vref

(

Bias generator

*2

VCCDIV

GNDDIV

31

Linearizer

÷2÷2

÷3

Vref

1612 MHz

30

Vref

÷2

(90 deg)

)

Div, Tx

(

÷2(90 deg)

VCONT

IOUT 0 to 100 kHz

29

28

)

Div, Rx

(

÷2, ÷12

÷2

(90 deg)

)

Vref

Demod

(

135 MHz

Vref

135 MHz

100 kHz

100 kHz

to

to

QOUT 0

IOUTB 0

27

)
Mod

(

100 kHz
to

QOUTB 0

26

540 MHz

25

23

IFVCOI

IFVCOO

GNDIQ

IFLO

VCCIQ

MOD

MODB

Vtune

IFLO

To Synth.

0 to 100 kHz IIN

0 to 100 kHz IINB

0 to 100 kHz QIN

Notes: 1. H = Active, L = Off

0 to 100 kHz QINB

All biases are H active

When Bias generator is off, all circuits will be off.

2. When POONRX1 = ‘H’ and POONRX2 = ‘L’, bias generator will be off.

1842 MHz

1842 MHz

MIX1INB

48 47 46 45 44 43 42 41 40 39 38 37

MIX1IN

1

*1

POONRX1

Vref

(LNA)

LNA

Bias

2

*1

POONRX2

Circuit

3

RFOUT

4

VCCLNA

GNDLNA

Vref

(PLL)

5

6

7

1747 MHz

8

RFIN

GNDPLL

VCCPLL

POONTX

9

Phase

10

VCOIN

detector

11

12

PLLOUT

VCCCOMP

ICURAD

13 14 15 16 17 18 19 20 21 22 24

*1

Configuration

HD155111F

• Frequency Plan1

1805 to 1880 MHz

RF

filter

TCXO
13 MHz

LPF

HPA Module

• Frequency Plan2

1805 to 1880 MHz

RF

filter

TCXO
13 MHz

LPF

HPA Module

LNA

bias
circuit

Rx. 1580 to 1655 MHz
Tx. 1575 to 1650 MHz

HD155017T

LNA

bias
circuit

1580 to 1655 MHz

HD155017T

RF

SAW

filter

Dual
synth.

RF

SAW

filter

Dual
synth.

buffer

buffer

225 MHz

IF

SAW

filter

RF VCO

PLL2PLL1

1710 to 1785 MHz

225 MHz

IF

SAW

filter

RF VCO

PLL2PLL1

1710 to 1785 MHz

270 MHz

IFVCO

540 MHz

Loop
filter

Rx. 270 MHz

IFVCO

Rx. 540 MHz
Tx. 520 MHz

Loop
filter

÷2

135 MHz

Phase

Detector

÷2

130 MHz

Phase

Detector

45 MHz

LC

filter

135 MHz

45 MHz

LC

filter

130 MHz

AGC

HD155111F

÷6

AGC

HD155111F

÷6

Tx. 260 MHz

45 MHz

90 deg

Shift

135 MHz

45 MHz

90 deg

Shift

130 MHz

I & Q

I & Q

Demo.

90 deg

Shift

÷2

÷2

I & Q

Mod

I & Q

Demo.

90 deg

Shift

÷2

÷2

Mod

I

Q

B.B.

Block

I

Q

I

Q

B.B.

Block

I

Q

HD155111F

A GSM Application Example

225 MHz

Rx. 1617 MHz
Tx. 1612 MHz

1842 MHz

45 MHz

MIX2O

38

IFINB

39 37

IFIN

40

GNDIF

41

VCCIF

42

MIX1OUT

MIX1OUTB

44

RFLOIN

VCCMIX1

GNDMIX1

MIX1INB

48 47 46 45 43

MIX1IN

1842 MHz

MIX2OB

GNDAGC

36

Vref
Vref

Vref

Vref

LNA

1

POONRX2

POONRX1

DAC

35

(Mix2)
(IF)

(Mix1)

(LNA)

Bias

2

DAC

10 bit

VCCAGC

34

1617 MHz

Circuit

3

RFOUT

10 bit

Base Band

45 MHz

AGOUT

33

4

VCCLNA

System

Controller

&

Base Band

Interface

ADC

12 bit

AGCOUTB

VCCDIV

32

Linearizer

45 MHz

Vref

(AGC)

*2

Bias generator

5

RFIN

GNDLNA

1842 MHz

Physical

Layer

Processor

Processing

DAC

GNDDIV

31

÷2÷2
÷3

÷2

Vref

1612 MHz

Vref

(PLL)

6

POONTX

ADC

10 bit

VCONT

30

Vref

(Div, Rx)

÷2

(90 deg)

(Div, Tx)

÷2(90 deg)

7

VCCPLL

12 bit

IOUT

29

÷2, ÷12

(90 deg)

135 MHz

1747 MHz

8

GNDPLL

DAC

10 bit

IOUTB

28

Vref

(Demod)

135 MHz

Vref

(Mod)

9

VCOIN

PA

QOUT

27

Phase

detector

10

VCCCOMP

Tx.VCO

ALC

13 MHz

QOUTB

26

540 MHz

11

PLLOUT

1747 MHz

Dual PLL synth.

VHF(IF)

PLL Synth.

UHF(RF)

PLL Synth.

25

12

IFVCOI

IFVCOO

GNDIQ

IFLO

VCCIQ

MOD

MODB

IIN

IINB

QIN

QINB

ICURAD

13 14 15 16 17 18 19 20 21 22 23 24

HD155111F

Functional Operation

The HD155111F has been designed from system stand point and incorporated a large number of the circuit
blocks necessary in the design of a digital cellular handset.

Receiver Operation

The HD155111F incorporates a LNA bias circuit for an external RF transistor, whose NF and power gain
can be better selected.

This circuit amplifies the RF signal after selection by the antenna filter before the signal enters the first
mixer section. The RF signal is combined with a low side local oscillator (LO) signal to generate a wanted
first IF signal in the 130 to 300 MHz range. The 1st mixer circuit uses a double-balanced Gilbert cell
architecture, which has open collector differential outputs. If, at 225 MHz, a 800 Ω LC load is connected
to the mixer’s outputs then a SSB NF of 10 dB with a gain of 8.0 dB is realizable. The corresponding input
compression point is –13 dBm, which allows the device to be used within a PCN system.

A filter is used after the 1st mixer to provide image rejection and the conditioned signal is then passed
through an intermediate amplifier, before being down converted to a second IF in the range of 26 to 60
MHz.

The second mixer can generate a 45 MHz 2nd IF, if a 270 MHz 2nd LO signal is used. The 2nd LO is
obtained by dividing the IFLO signal by 2. The 2nd mixer also uses the Gilbert cell architecture, but with
internal resistive differential outputs of 300 Ω. IF amplifier and second mixer has a SSB NF of 5.6 dB, a
power gain of 12 dB and an input compression point of –25 dBm. In order to improve the blocking
characteristics of the device an external LC resonator across the differential outputs of the second mixer is
recommended.

The signal is then passed to the AGC circuit, which has a dynamic range of more than 80 dB (–42 dB to
+55 dB Typ) and is controlled by a DC voltage, which is generated by the microprocessor. This DC
control range is from 0.15 V to 2.3 V. The AGC, which is designed for the PCN system, provides a
linearity of ±1.0 dB in any 20 dB window. The outputs of the AGC are 2 kΩ differential and are connected
the external supply via inductors.

The signal is then down converted by a demodulator to I and Q. Internal divider circuits convert the IFLO
signal to the same frequency as the 2nd IF before passing this local signal through a phase splitter / shifter
in order to generate the in phase and quadrature IQ components. The phase accuracy of the IQ
demodulator is < ±1° and the amplitude mismatch is < ±0.5 dB. In order to accommodate different
baseband interfaces the HD155111F IQ differential outputs have a voltage swing of 2.4 Vp-p and a DC
offset of < 60 mV Max. Within each output stage a 2nd order Butterworth filter (fc = 210 kHz), is used to
improve the blocking performance of the device.

In order to allow flexibility in circuit implementation the HD155111F can configured to use either a single­ended or balanced external circuitry and components.

HD155111F

LNA

Vref

LNA

bias

circuit

Pinput

Poutput

RFOUT

3

VCCLNA

4Vcc

GNDLNA

5

RFIN

6

Figure 1 LNA Bias Circuit

Transmitter Operation

The transmitter chain converts differential IQ baseband signals to a suitable format for transmission by a
power amplifier.

The common mode DC voltage range of the modulator inputs is 0.8 to 1.2 V and they have 2.4 Vp-p Max
differential swing. The modulator circuit uses double-balanced mixers for the I and Q paths. The LO
signals are generated by dividing the IFLO signal by 2 and then passing them through a phase splitter /
shifter. The IF signals generated are then summed and produce a single modulated IF signal which is
amplified and fed into the offset PLL block. Carrier suppression due to the mixer circuit is better than 31
dBc. However, if the common mode DC voltage of the I and Q inputs is adjusted, carrier suppression can
be improved better than 40 dBc easily. In addition, upper side-band suppression is better than 35 dBc.

Within the offset PLL block there is a down converter, a phase comparator and a VCO driver. The down
converter mixes the 1st LO signal and the TX VCO to create a reference LO signal for use in the offset
PLL circuit. The phase comparator and the VCO driver generate an error current, which is proportional to
the phase difference between the reference IF and the modulated IF signals. This current is used in a 2nd
order loop filter to generate a voltage, which in turn modulates the TX VCO. In order to optimize the PLL
loop gain, the error current value can be modified by changing the value of an external resistor - ICURAD.
In order to accommodate a range of TX VCO, the offset PLL circuit has been designed to operate with a
supply voltage of up to 5.25 V.

Operating Modes

The HD155111F has the necessary control circuitry to implement the necessary states within the PCN
system. Also provided is a power save mode which reduces the current consumption of the device by
powering down unnecessary function blocks. Three pins are assigned for mode control, POONRX1,
POONRX2 and POONTX. Table 1 shows the relationship between the pins and the required operating
mode. Control of these pins are by the system controller.

As per PCN requirements the TX and RX sections are not on at the same time. For the receiver there is a
calibration mode for which the LNA bias circuit and 1st mixer are switched off. During this period the
gain of the AGC can be adjusted. Also the DC offsets of the IQ demodulator are measured and
subsequently canceled.

In order to change between the RX and TX modes a state called “warm-up” is used to ensure that the LO

HD155111F

Power saving is implemented through use of the idle mode. All function blocks of the HD155111F are
switched off until such time as the system controller commends the device to power up again.

Table 1 Operating Modes with Power Saving

Receive
(Rx)

Calibrate
(Cal)

Warm-up
(Lo-ON)

Transmit
(Tx)

Idle
(PS)

Mode POONRX1 (pin 1) H L L L H
switch POONRX2 (pin 2) H H L L L

POONTX (pin 7) L L L H Don’t care
HD155111F LNA bias ON OFF OFF OFF OFF
circuit status 1st mixer ON OFF OFF OFF OFF

IF AMP ON ON OFF OFF OFF

2nd mixer ON ON OFF OFF OFF

AGC ON ON OFF OFF OFF

IO demodulator ON ON OFF OFF OFF

Divider (Rx.) ON ON OFF OFF OFF

Divider (Tx.) OFF OFF OFF ON OFF

IO modulator OFF OFF OFF ON OFF

Offset PLL OFF OFF OFF ON OFF

RF 1st local buffer ON ON ON ON OFF

IF local buffer ON ON ON ON OFF

IFVCO ON ON ON ON OFF

Total current 42.5 mA Typ 32 mA Typ 10.5 mA Typ 38 mA Typ 1 µA Typ

The slots of
PCN system

Operating modes
of the HD155111F

POONRX1(pin 1)
POONRX2(pin 2)

POONTX (pin 7)
Power Amplifier ON
UHF PLL synth. ON

UHF PLL synth. load
VCO control voltage

of UHF PLL synth.

4.615ms

7012345670123456701

Rx RxTx Tx

Cal Cal Cal Cal

Rx Rx Rx Rx

Tx Tx

Lo-ON Lo-ON

Mon Mon

Lo­ON

Lo­ON

4.615ms

Lo­ON

Lo-

ON

Idle(PS) mode don't care

PS

HD155111F

IFVCO Operation

The HD155111F incorporates an IFVCO circuit. The IFVCO circuit consists of an IFVCO transistor and a
bias circuit for it, whose current are 2.0 mA and 0.5 mA respectively. If an internal IFVCO is used, treat
pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) as shown figure 3-(a).

Using an external IFVCO, pin 23 (IFVCOO) and pin 24 (IFVCOI) cannot be connected any pattern and
component, and any component to feed direct current must be also removed from pin 21 (IFLO).

If pin 23 (IFVCOO), pin 24 (IFVCOI) and pin 21 (IFLO) are treated as shown figure 3-(b), current
consumption will decrease 2.0 mA.

Moreover, there is the other external IFVCO solution using only an IFVCO bias circuit as shown figure 3­(c). The IFVCO bias circuit has an internal power save function. Therefore, if figure 3-(c) is adopted, an
internal power save function can be used as well as figure 3-(a).

IFVCO
bias circuit

IFVCO
bias circuit

IFVCOI

HD155111F

IFVCOI

Vtune

IFLO

HD155111F

PLL
synth.

Vtune

IFLO

PLL
synth.

23

21 24

IFLO

IFVCOO

External
IFVCO

23

21 24

IFLO

IFVCOO

Vcc

(a) using an internal IFVCO (b) using an external IFVCO

23

21 24

IFLO

IFVCOO

Vcc

(c) using only an IFVCO bias circuit

Figure 3 IFVCO Circuits

IFVCO
bias circuit

HD155111F

IFVCOI

Vtune

IFLO

PLL
synth.

HD155111F

Absolute Maximum Ratings

Any stresses in excess of the absolute maximum ratings can cause permanent damage to the HD155101BF.

Item Symbol Rating Unit

Power supply voltage (VCC) VCC –0.3 to +4.0 V
Power supply voltage (VCCCOMP) VCCCOMP –0.3 to +5.5 V
Pin voltage V
Maximum power dissipation P
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C

T

T

–0.3 to VCC + 0.3 (6.0 Max) V
400 mW

HD155111F

Oco

C

C

Electrical Characteristics (Ta = 25°C)

Specifications

Item Symbol Min Typ Max Unit Test Conditions

Power supply voltage (1) V

Power supply voltage (2) V
Power supply current (Rx.) I

Power supply current (Tx.) I

Power supply current

CC

CCCOMP

CC(Rx.)

CC(Tx.)

I

CC(Lo-ON)

(Lo-ON)
Power saving mode supply

I

CC(PS)

current
Power up time (Rx.) t up

Power up time (Tx.) t up

Power on control voltage
range (Rx1, Rx2, Tx)

Vthon
Vthon
Vthon

Power off control voltage
range (RX1, Rx2, Tx)

Vthoff
Vthoff
Vthoff

I/Q common-mode output
voltage

I/Q differential output swing V

I/Q output offset voltage V

I/Q common-mode input
voltage

I/Q differential input swing V

V

I

V

QOcom

IOsw

V

QOsw

IOoffset

V

QOoffset

V

IIcom

V

QIcom

IIsw

V

QIsw

Note: ( ) : These data are actual spread, not guaranteed.

2.7 3.0 3.6 V 4, 8, 20, 31,

2.7 3.0 5.25 V 11
— 42.5 60.0 mA VCC = 3.0V

V

= 3.0V

CCCOMP

— 38.0 55.0 mA VCC = 3.0V

V

= 3.0V

CCCOMP

— 10.5 15.0 mA VCC = 3.0V

V

= 3.0V

CCCOMP

— 1.0 10.0 µAVCC = 3.0V

V

= 3.0V

CCCOMP

— 1.5 (5.0) µsec VCC = 3.0V

(Rx.)

— 0.2 (0.5) µsec VCC = 3.0V

(Tx.)

2.3 — — V VCC = 3.0V 1

RX1
RX2
TX

— — 0.8 V VCC = 3.0V 1

RX1
RX2
TX

/

1.1 1.3 1.5 V VCC = 3.0V 25, 26

m

/

2.4 3.0 — Vp-p VCC = 3.0V

/

–60 0 +60 mV VCC = 3.0V

/

(0.8) 1.0 (1.2) V VCC = 3.0V 14, 15

/

— 2.0 (2.4) Vp-p VCC = 3.0V

V

CCCOMP

V

CCCOMP

V

IOUT

V

QOUT

V

IOUTD

V

QOUTDC

V

IIN

V

QIN

– V

– V

– V

= 3.0V

= 3.0V

– V

– V

– V

IINB

QINB

IOUTB

QOUTB

IOUTBD

QOUTBDC

Applicable
pins Note

34, 41, 45

4, 8, 20, 31,
34, 41, 45, 11

4, 8, 20, 31,
34, 41, 45, 11

4, 8, 20, 31,
34, 41, 45, 11

4, 8, 20, 31,
34, 41, 45, 11

from PS
mode

from PS
mode

2
7

2
7

27, 28
25, 26

27, 28

25, 26
27, 28

16, 17
14, 15

16, 17