HB288800A5, HB288640A5, HB288448A5, HB288320A5, HB288256A5, HB288192A5, HB288160A5,
HB288128A5, HB288096A5, HB288064A5, HB288032A5 are Flash ATA card. This card complies with PC
card ATA standard and is suitable for the usage of data storage memory medium for PC or any other electric
equipment. This card is equipped with Hitachi 256 Mega bit Flash memory. This card is suitable for ISA
(Industry Standard Architecture) bus interface standard , and read/write unit is 1 sector (512 bytes) sequential
access. By using this card it is possible to operate good performance for the system which have PC card slots.
Features
• PC card ATA standard specification
68 pin two pieces connector and Type II (5 mm)
• 3.3 V/5 V single power supply operation
• ISA standard and Read/Write unit is 512 bytes (sector) sequential access
Sector Read/Write transfer rate: 8MB/sec burst
This signal is used to configure this device as a
Master or a Slave when configured in the True IDE
mode. When this pin is grounded, this device is
configured as a Master. When the pin is open, this
device is configured as a Slave.
I/O41, 40, 39, 38,
37, 66, 65, 64, 6,
5, 4, 3, 2, 32, 31,
30
—1, 34, 35, 68Ground
O60This signal is not used and should not be connected
I44This signal is not used.
Data bus is D15 to D0. D0 is the LSB of the even byte
of the word. D8 is the LSB of the odd byte of the
word.
at the host.
This signal is asserted low by this card when the card
is selected and responding to an I/O read cycle at the
address that is on the address bus during -CE and
-IORD are low. This signal is used for the input data
buffer control.
This signal is not used and should not be connected
at the host.
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until I/O
card interface setting up.
-IORD is used for control of read data in I/O task file
area. This card does not respond to -IORD until True
IDE interface setting up.
-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until I/O
card interface setting up.
-IOWR is used for control of data write in I/O task file
area. This card does not respond to -IOWR until True
IDE interface setting up.
I9-OE is used for the control of reading register’s data in
attribute area or task file area.
-OE is used for the control of reading register’s data in
attribute area.
To enable True IDE mode this input should be
grounded by the host.
O16The signal is RDY/-BSY pin. RDY/-BSY pin turns low
level during the card internal initialization operation at
VCC applied or reset applied, so next access to the
card should be after the signal turned high level.
This signal is active low -IREQ pin. The signal of low
level indicates that the card is requesting software
service to host, and high level indicates that the card
is not requesting.
This signal is the active high Interrupt Request to the
host.
I61-REG is used during memory cycles to distinguish
between task file and attribute memory accesses.
High for task file, Low for attribute memory is
accessed.
-REG is constantly low when task file or attribute
memory is accessed.
This input signal is not used and should be connected
to VCC.
I58This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. During the card internal initialization
RDY/-BSY is low. After the card internal initialization
RDY/-BSY is high.
This signal is active high RESET pin. If this signal is
asserted high, the card internal initialization begins to
operate. In this mode, RDY/-BSY signal can not be
used, so using Status Register the Ready/Busy status
can be confirmed.
This signal is active low -RESET pin. If this signal is
asserted low, all the register’s in this card are reset.
In this mode, RDY/-BSY signal can not be used, so
using status register the Ready/Busy status can be
confirmed.
—17, 51+5 V, +3.3 V power.
O43, 57These signals are intended to notify VCC requirement
to host. -VS1 is held grounded and -VS2 is
nonconnected in this card.
O59This signal is active low -WAIT pin. In this card this
signal is constantly high level.
This output signal may be used as IORDY. In this
card this signal is constantly high impedance.
I15-WE is used for the control of writing register’s data in
attribute memory area or task file area.
-WE is used for the control of writing register’s data in
attribute memory area.
This input signal is not used and should be connected
to VCC by the host.
O33WP is held low because this card does not have write
protect switch.
-IOIS16 is asserted when task file registers are
accessed in 16-bit mode.
This output signal is asserted low when this device is
expecting a word data transfer cycle. Initial mode is
16-bit. If the user issues a Set Feature Command to
put the device in Byte access mode, the card permits
8-bit accesses.
When CIS-ROM region or Configuration register region is accessed, read and write operations are executed
under the condition of -REG = "L" as follows. That region can be accessed by Byte/Word/Odd-byte modes
which are defined by PC card standard specifications.
There are two cases of Task File register mapping, one is mapped I/O address area, the other is mapped Memory address
area. Each case of Task File register read and write operations are executed under the condition as follows. That area can
be accessed by Byte/Word/Odd Byte mode which are defined by PC card standard specifications.
(1) I/O address map
Task File Register Read Access Mode (1)
Mode-REG -CE2-CE1A0-IORD -IOWR -OE-WED8 to D15 D0 to D7
The card can be configured in a True IDE mode of operation. This card is configured in this mode only when the -OE
input signal is asserted GND by the host. In this True IDE mode Attribute Registers are not accessible from the host.
Only I/O operation to the task file and data register are allowed. If this card is configured during power on
sequence, data register are accessed in word (16-bit). The card permits 8-bit accesses if the user issues a Set
Feature Command to put the device in 8-bit mode.
True IDE Mode Read I/O Function
Mode-CE2-CE1A0 to A2 -IORD-IOWRD8 to D15 D0 to D7
Invalid modeLL×××High-ZHigh-Z
Standby modeHH×××High-ZHigh-Z
Data register accessHL0LHodd byteeven byte
Alternate status accessLH6HLHHigh-Zstatus out
Other task file accessHL1-7HLHHigh-Zdata
Note: ×: L or H
True IDE Mode Write I/O Function
Mode-CE2-CE1A0 to A2 -IORD-IOWRD8 to D15 D0 to D7
Invalid modeLL×××don’t caredon’t care
Standby modeHH×××don’t caredon’t care
Data register accessHL0HLodd byteeven byte
Control register accessLH6HHLdon’t carecontrol in
Other task file accessHL1-7HHLdon’t caredata
This card supports four Configuration registers for the purpose of the configuration and observation of this
card. These registers can be used in memory card mode and I/O card mode. In True IDE mode, these
registers can not be used.
1. Configuration Option register (Address 200H)
This register is used for the configuration of the card configuration status and for the issuing soft reset to the
card.
bit7bit6bit5bit4bit3bit2bit1bit0
SRESETLevlREQINDEX
Note: initial value: 00H
NameR/WFunction
SRESET
(HOST->)
LevlREQ
(HOST->)
INDEX
(HOST->)
R/WSetting this bit to "1", places the card in the reset state (Card Hard Reset). This
operation is equal to Hard Reset, except this bit is not cleared. Then this bit set to "0",
places the card in the reset state of Hard Reset (This bit is set to "0" by Hard Reset) .
Card configuration status is reset and the card internal initialized operation starts when
Card Hard Reset is executed, so next access to the card should be the same sequence
as the power on sequence.
R/WThis bit sets to "0" when pulse mode interrupt is selected, and "1" when level mode
interrupt is selected.
R/WThis bits is used for select operation mode of the card as follows.
When Power on, Card Hard Reset and Soft Reset, this data is "000000" for the purpose
of Memory card interface recognition.
INDEX bit assignment
INDEX bit
5 4 32 1 0 Card modeTask File register addressMapping mode
0 0 00 0 0 Memory card0H to FH, 400H to 7FFHmemory mapped
0 0 00 0 1 I/O cardxx0H to xxFHcontiguous I/O mapped
0 0 00 1 0 I/O card1F0H to 1F7H, 3F6H to 3F7Hprimary I/O mapped
0 0 00 1 1 I/O card170H to 177H, 376H to 377Hsecondary I/O mapped
RThis bit indicates that CRDY/-BSY bit on Pin Replacement register is set to "1". When
CHGED bit is set to "1", -STSCHG pin is held "L" at the condition of SIGCHG bit set to
"1" and the card configured for the I/O interface.
R/WThis bit is set or reset by the host for enabling and disabling the status-change signal (-
STSCHG pin). When the card is configured I/O card interface and this bit is set to "1", STSCHG pin is controlled by CHGED bit. If this bit is set to "0", -STSCHG pin is kept
"H".
R/WThe host sets this field to "1" when it can provide I/O cycles only with on 8 bit data bus
(D7 to D0).
R/WWhen this bit is set to "1", the card enters sleep state (Power Down mode). When this
bit is reset to "0", the card transfers to idle state (active mode). RRDY/-BSY bit on Pin
Replacement Register becomes BUSY when this bit is changed. RRDY/-BSY will not
become Ready until the power state requested has been entered. This card
automatically powers down when it is idle, and powers back up when it receives a
command.
RThis bit indicates the internal state of the interrupt request. This bit state is available
whether I/O card interface has been configured or not. This signal remains true until the
condition which caused the interrupt request has been serviced. If interrupts are
disabled by the -IEN bit in the Device Control Register, this bit is a zero.
This register is used for identification of the card from the other cards. Host can read and write this register.
This register should be set by host before this card's Configuration Option register set.
bit7bit6bit5bit4bit3bit2bit1bit0
000DRV#0000
Note: initial value: 00H
R/WThis bit is set to "1" when the RRDY/-BSY bit changes state. This bit may also be
written by the host.
R/WWhen read, this bit indicates +READY pin states. When written, this bit is used for
CRDY/-BSY bit masking.
NameR/WFunction
DRV#
(HOST->)
R/WThis fields are used for the configuration of the plural cards. When host configures the
plural cards, written the card’s copy number in this field. In this way, host can perform
the card’s master/slave organization.
CIS informations are defined as follows. By reading attribute address from "0000 H", card CIS informations
can be confirmed.
Address Data 76 543210Description of contentsCIS function
000H01H CISTPL_DEVICEDevice info tupleTuple code
002H04H TPL_LINKLink length is 4 byteLink to next tuple
004HDFH Device typeW
006H4AH EXT Speed
mantissa
008H01H 1x2k units2k byte of address spaceDevice size
00AHFFH List end markerEnd of deviceEND marker
00CH1CH CISTPL_DEVICE_OCOther conditions device info
00EH04H TPL_LINKLink length is 4 bytesLink to next tuple
010H02H EXT ReservedV
012HD9H Device typeW
014H01H 1x2k units2k byte of address spaceDevice size
016HFFH List end markerEnd of deviceEND marker
018H18H CISTPL_JEDEC_CJEDEC ID common memory Tuple code
01AH02H TPL_LINKLink length is 2 bytesLink to next tuple
01CHDFH PCMCIA’s manufacturer’s JEDEC
ID code
01EH01H PCMCIA JEDEC device code2nd byte of JEDEC ID
020H20H CISTPL_MANFIDManufacturer’s ID codeTuple code
022H04H TPL_LINKLink length is 4 bytesLink to next tuple
024H07H Low byte of PCMCIA
manufacturer’s code
026H00H High byte of PCMCIA
manufacturer’s code
028H00H Low byte of product codeHITACHI code for PC CARD
02AH00H High byte of product codeHigh byte of product code
Device speed Device type = DH: I/O device
P
S
Speed
exponent
MWAIT 3 V, wait is not usedOther conditions info field
CC
Device speed Device type = DH: I/O device
P
S
WPS = 1: No WP
Device speed = 7: ext speed
400 ns if no waitExtended speed
tuple
WPS = 1: No WP
Device speed = 1: 250 ns
Manufacturer’s ID codeJEDEC ID of PC Card ATA
HITACHI JEDEC
manufacturer’s ID
Code of 0 because other byte
is JEDEC 1 byte
manufacture’s ID
Address Data 76 543210Description of contentsCIS function
02CH15HCISTPL_VERS_1Level 1 version/product infoTuple code
02EH15H TPL_LINKLink length is 15h bytesLink to next tuple
030H04H TPPLV1_MAJORPCMCIA2.0/JEIDA4.1Major version
032H01H TPPLV1_MINORPCMCIA2.0/JEIDA4.1Minor version
034H48H‘ H ’Info string 1
036H49H‘ I ’
038H54H‘ T ’
03AH41H‘ A ’
03CH43H‘ C ’
03EH48H‘ H ’
040H49H‘ I ’
042H00HNull terminator
044H46H‘ F ’Info string 2
046H4CH‘ L ’
048H41H‘ A ’
04AH53H‘ S ’
04CH48H‘ H ’
04EH00HNull terminator
050H35H‘ 5 ’Vender specific strings
052H2EH‘ . ’
054H30H‘ 0 ’
056H00HNull terminator
058HFFH List end markerEnd of deviceEND marker
05AH21H CISTPL_FUNCIDFunction ID tupleTuple code
05CH02HTPL_LINKLink length is 2 bytesLink to next tuple
05EH04H TPLFID_FUNCTION = 04HDisk function, may be silicon,
may be removable
060H01H ReservedR PR = 0: No BIOS ROM
P = 1: Configure card at
power on
PC card function code
System initialization byte
20
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