Hisilicon HI3516D User Manual

Hi3516D Professional HD IP Camera SoC

Brief Data Sheet

Issue 01 Date 2014-12-22

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HiSilicon Technologies Co., Ltd.

Address: Huawei Industrial Base

Bantian, Longgang Shenzhen 518129

People's Republic of China

Website: Email:

http://www.hisilicon.com support@hisilicon.com

Hi3516D

Hi3516D Professional HD IP Camera SoC

z ISP tuning tools for the PC

Key Specifications

Processor Core

z A7@600 MHz, 32 KB I-cache, 32 KB D-cache/128 KB

L2 cache

z Neon acceleration, integrated FPU

Video Encoding

z H.264 BP/MP/HP z H.265 main profile z MJPEG/JPEG baseline encoding

Video Encoding Performance

z A maximum of 5-megapixel resolution for H.264/H.265

encoding

z Real-time H.264/H.265 encoding of multiple streams:

− 1080p@30 fps+720p@30 fps+VGA@30 fps

− 3-megapixel@30 fps+VGA@30 fps

− 5-megapixel@15 fps

z JPEG snapshot at 5-megapixel@8 fps z Supporting the CBR/VBR bit rate control mode, ranging

from 16 kbit/s to 40 Mbit/s

z Encoding frame rate ranging from 1/16 fps to 60 fps z Encoding of eight ROIs

Intelligent Video Analysis

z Integrated IVE, supporting various intelligent analysis

applications such as motion detection, boundary security and video diagnosis

Video and Graphics Processing

z 3D denoising, image enhancement, and dynamic contrast

enhancement

z Anti-flicker for output videos and graphics z 1/15.99x to 16x video scaling z 1/2x to 2x graphics scaling z OSD overlay pre-processing for eight regions z Video graphics overlaying of two layers (video layer and

graphics layer)

ISP

z Adjustable 3A functions (AE, AWB, and AF) z Noise reduction in FPN mode z Highlight compensation, backlight compensation, gamma

correction, and color enhancement

z Defect pixel correction, denoising, and digital image

stabilizer

z Anti-fog z Lens distortion correction z Picture rotation by 90° or 270° z Mirroring and flipping z Digital WDR, frame base/line base WDR, and tone

mapping

Audio Encoding/Decoding

z Voice encoding/decoding in compliance with multiple

protocols by using software

z G.711, ADPCM, and G.726 protocols z AEC, ANR, and ALC

Security Engine

z Various encryption and decryption algorithms using

hardware, such as AES, DES, and 3DES

z Digital watermark

Video Interfaces

z Input

− 8-/10-/12-/14-bit RGB Bayer DC timing VI, a

maximum of 150 MHz clock frequency

− BT.601, BT.656 or BT.1120 VI interface

− MIPI, LVDS/sub-LVDS, and HiSPI

− Compatibility with mainstream HD CMOS sensors

provided by Sony, Aptina, OmniVision, and Panasonic

− Compatibility with the electrical specifications of

parallel and differential interfaces of various sensors

− Programmable sensor clock output

− Maximum input resolution of 5 megapixels

z Output

− One PAL/NTSC output for automatic load detection

− One BT.1120/BT.656 VO interface for connecting to

an external HDMI or SDI, up to 1080p@60 fps output

Audio Interfaces

z Integrated audio CODEC, supporting 16-bit audio inputs

and outputs

z I

S interface for connecting to an external audio CODEC

Peripheral Interfaces

z POR z One integrated high-precision RTC z One dual-channel SAR ADC z Four UART interfaces z One IR interface, three I

interfaces, 14 x 8 + 3 GPIO interfaces

z Eight PWM interfaces (four independent interfaces and

four multiplexed with other pins)

z Two SDIO 3.0 interfaces, supporting SDXC z One USB 2.0 host/device port z RGMII/RMII/MII in 100/1000 Mbit/s full-duplex or half-

duplex mode, PHY clock output, and TSO network acceleration

C interfaces, four SPI master

External Memory Interfaces

z DDR3/3L SDRAM interface

− One 16-bit DDR3/3L interface with the maximum

frequency of 600 MHz (1.2 Gbit/s)

− Maximum capacity of 4 Gbits for a 16-bit DDR

Issue 01 (2014-12-22)

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