Hisense RSAG2.908.6823 Schematic

5
MB circuit:6484
4
3
2
1
POWER TREE
D D
C C
B B
A A
Hisense Electric Co.,LTD
Title
Title
5
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev C
C
C Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
MT5655
MT5655
MT5655
1
1.0
1.0
113Friday, April 10, 2015
113Friday, April 10, 2015
113Friday, April 10, 2015
1.0
5
MB circuit:6484
4
3
2
1
Block Diagram
NAND FLASH
UM3 or U1
EMMC
D D
UD1
DDR3
Flash
SPISerial
UM2.UM4
SDIOx1
UD2
DDR3
C C
JL1
LVDS Port
V By One
LVDS Port
mini_LVDS A Port
MT5655
UM1
CI
Embedded DEMOD
USB_P0_P1_P2
HDMI_P0_P1
Serial TS
Tuner IF+/IF-
USBx3
HDMIx2
Tuner CVBS1
B B
Audio DAC
UA4
SPEAKER AMP
TPS5711
JA1.JA2
SPEAKER OUT
I2S
Embedded RMII PHY
MII/RMII
USB_P3
CVBS2 IN
RGB IN
LINE OUT
LINE IN
SCART1 AV OUT
x 3
Audio ADC x4
CVBS3
MPXP share with CVBS0
LINE IN
PA2,PA11,PV7
PV7,PA6,PA7,PA8
PC1
CAM Card
TUNER& External Demod
JT1,JT2
LINE IN
HDMI_P2
A A
UW2
Ethernet
5
PU4 USBx1
HDMI X1
PH3
IRM1
IR
4
J2
I2C1
J3
UART0
PV5
VGA
PV7
SCART2
3
PV3
YPbPr0
PV8
AV1
Hisense Electric Co.,LTD
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev C
C
C Date: Sheet
Date: Sheet
2
Date: Sheet
MT5655
MT5655
MT5655
1
1.0
1.0
213Friday, April 10, 2015
213Friday, April 10, 2015
213Friday, April 10, 2015
1.0
5
MB circuit:6484
4
3
2
1
GPIO LIST
PIN NAME
CI_A0 CI_A1 CI_A2 CI_A3 CI_A4
D D
CI_A5 CI_A6 CI_A7 CI_A8 CI_A9 CI_A10 CI_A11 CI_A12 CI_A13 CI_A14 CI_MCLKI CI_MIVAL CI_MISTRT CI_MDI0 CI_MDI1 CI_MDI2 CI_MDI3 CI_MDI4 CI_MDI5
C C
CI_MDI6 CI_MDI7 CI_D0 CI_D1 CI_D2 CI_D3 CI_D4 CI_D5 CI_D6 CI_D7 CI_MDO0 CI_MDO1 CI_MDO2 CI_MDO3 CI_MDO4 CI_MDO5 CI_MDO6 CI_MDO7 GPIO_42
B B
GPIO_43 GPIO_44 GPIO_45 GPIO_46 GPIO_47
Function define
CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface CI Interface
3D ENABLE PANEL_3D_EN
BACKLIGHT OPWM 3D SYNC OUT 3D SYNC IN PANEL_3D_LR_SYNC IN
GPIO Function
CI_A0 CI_A1 CI_A2 CI_A3 CI_A4 CI_A5 CI_A6 CI_A7 CI_A8 CI_A9 CI_A10 CI_A11 CI_A12 CI_A13 CI_A14 CI_MCLKI CI_MIVAL CI_MISTRT CI_MDI0 CI_MDI1 CI_MDI2 CI_MDI3 CI_MDI4 CI_MDI5 CI_MDI6 CI_MDI7 CI_D0 CI_D1 CI_D2 CI_D3 CI_D4 CI_D5 CI_D6 CI_D7 CI_MDO0 CI_MDO1 CI_MDO2 CI_MDO3 CI_MDO4 CI_MDO5 CI_MDO6 CI_MDO7
3D_blink1BACKLIGHT OPWM 3D_blink2 GPIO45 GPIO46 PANEL_IN_3D_LR_SYNC
(GPIO_0) (GPIO_1) (GPIO_2) (GPIO_3) (GPIO_4) (GPIO_5) (GPIO_6) (GPIO_7) (GPIO_8) (GPIO_9) (GPIO_10) (GPIO_11) (GPIO_12) (GPIO_13) (GPIO_14) (GPIO_15) (GPIO_16) (GPIO_17) (GPIO_18) (GPIO_19) (GPIO_20) (GPIO_21) (GPIO_22) (GPIO_23) (GPIO_24) (GPIO_25) (GPIO_26) (GPIO_27) (GPIO_28) (GPIO_29) (GPIO_30) (GPIO_31) (GPIO_32) (GPIO_33) (GPIO_34) (GPIO_35) (GPIO_36) (GPIO_37) (GPIO_38) (GPIO_39) (GPIO_40) (GPIO_41)
PIN NAME
ADIN0_SRV ADIN1_SRV ADIN2_SRV ADIN3_SRV ADIN4_SRV ADIN5_SRV ADIN6_SRV ADIN7_SRV
PIN NAME
OPCTRL0 OPCTRL1 OPCTRL2 OPCTRL3 OPCTRL4 OPCTRL5 OPCTRL6 OPCTRL7 OPCTRL8 OPCTRL9 OPCTRL10 OPCTRL11 OPCTRL12
PIN NAME GPIO FunctionFunction define
LED_PWM0 LED_PWM1
PIN NAME
OPWM0 OPWM1 OPWM2
Function define
KEY_PAD Headphone Detect MHL Over Current Protect MHL_OC KEY_PAD Enable AMP_MUTE AMP_MUTE
Function define
Wifi Reset Wifi detect WIFI_DEV_wake Reset TUNER
Strapping Strap[3]
LED PWM LED PWM RESET AMP Wifi Power Enable LVDS Power Control Audio Mute Backlight Control MHL_PWR_EN MHL_PWR_EN
Strapping Strapping
Function define
SYSTEM EEPROM write protect
Backlight DIMMING
TUNER SWITCH
GPIO Function
KEY_PAD0 HP_DET
KEY_PAD1
PANEL_I2C_WPEnable panel I2C
GPIO Function
REG_ON
TUNER-RST
LED_0
LED_1
AMP_RESET
WAKEUP_PWR_EN
LVDS_PWR_EN MUTE_CTL BL_ON/OFF
FB_PWR_ENDRAM Standby Power Control
Strap[1] Strap[2]
GPIO Function
SYS_EEPROM_WP BL_DIMMING SW_TUNER
A A
Hisense Electric Co.,LTD
Title
Title
5
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev C
C
C Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
MT5655
MT5655
MT5655
1
1.0
1.0
313Friday, April 10, 2015
313Friday, April 10, 2015
313Friday, April 10, 2015
1.0
5
MB circuit:6484
MAIN POWER
XP1
1 2 3
4
BL_ENDIMMING
6
12VS
8 10 12 14
12VS
C1
100u/16V/NC
POWER ON/OFF
12V-->5V需使用TPS54628
8
1
3
C14
N30
VIN
EN
VRG5
SS4GND
TPS54628
9
EPAD
VBST
6
SW
7
2
VFB
5
C5
100n/16V
L1
2.2 uH
3D_SG/PWM2
R538
0R/NC
5 7
9 11 13
12VS
POWER ON/OFF
VCC_A VCC_A
D D
PANEL_3D_EN 3D_LR/PWM1
DIMMING 3D_SG/PWM2
预留blinking接口电路,默认NC
12V-->5V
R13
C4
C3
C2
10u/16V
10u/16V/NC
100n/16V
C12
100n/16V
C13
1u/25V
10k
8.2n/50V
MMBT3904LT1
R14 130k
22p/50V
R15 27k
R9 1k
C6
R16 140k
4
5VS
R11 1k
3
R10
1
V3
4.7k
2
R12 47k
5A
C7
C8
C9
22u/6.3V
22u/6.3V
22u/6.3V
closed to L
Vout=0.765*(1+R14/R15//R16)=5.15V
LO = > POWER_ON HI = > POWER_OFF
OPWRSB
5VS12VS
C10
C11
22u/6.3V
100n/16V
BL_ON/OFF
POWER SWITCH
12VS
C47
100n/16V
5VS
R509
4.7k
R33
OPWRSB
LO = > POWER_ON HI = > POWER_OFF
1
4.7k
3.3VS
R3 10k
BL_DIMMING
C48
1u/16V
R510
4.7k
3
V6 MMBT3904LT1
2
R1
4.7k
3.3VS
3
5V
R2 1k
1
V1
MMBT3904LT1
2 3
R7 10k
R5
1
4.7k
N40
1
S1
2
S2
3
R31
S3
4
20k
G
AO4459
R32
20k
3
V46
1
MMBT3904LT1
2
5V
R6
4.7k
V2
MMBT3904LT1
2 3
8
D1
7
D1
6
D2
5
D2
R4 1k
12V
R8 1k
C501
2.2u/10V
VCCK
BL_EN
5VS
100n/16V
C50
DIMMING
R36
4.7k
C51
1u/16V
1
R34 20k
R35 10k
3
V5 MMBT3904LT1
2
1 2 3 4
N42
S1 S2 S3 G
AO4459
2
5V
8
D1
7
D1
6
D2
5
D2
8
8,12
12 12
12
1
OPWRSB5 3D_SG/PWM28 3D_LR/PWM1 PANEL_3D_EN FB_PWR_EN
BL_DIMMING BL_ON/OFF
GND5,6,7,8,9,10,11,12,13
OPWRSB 3D_SG/PWM2 3D_LR/PWM1
PANEL_3D_EN
FB_PWR_EN BL_DIMMING BL_ON/OFF
Core Power 1.0V
C C
12V
C17
C16
10u/16V
10u/16V/NC
C18
100n/16V
C19
100n/16V
Buck Converter 6A Solution
N33
8
VIN
1
EN
3
VRG5
SS4GND
VBST
VFB
EPAD
TPS54628
9
SW
R17 10k
C20
1u/25V
C21
8.2n/50V
DIGITAL POWER DVDD3V3
5V
L112
BLM18PG121SN1
C30
10u/16V
C31
10u/16V/NC
100n/16V
C33
100n/16V
C32
C34
1u/25V
N35
8
VIN
R25
1
10k
EN
3
VRG5
SS4GND
C35
8.2n/50V
VBST
EPAD
TPS54328
9
6
SW
7
2
VFB
5
C36
100n/16V
2.2 uH
L3
R28
73.2k
R27 22k
C39
C49
22u/6.3V
22p/50V
closed to L
R29 140k/NC
Vout=0.765*(1+R28/R7//R29)=3.31V
3A
C40
22u/6.3V
DVDD3V3 AVDD3V3
C41
C42
22u/6.3V
100n/16V
C27
22u/6.3V
C28
22u/6.3V
VCCK
C29
100n/16V
5A
C24
C25
22u/6.3V
22p/50V/NC
R21 27k
Vout=0.765*(1+R19/R20//R21)=1.23V
C26
22u/6.3V
closed to L
C22
100n/16V
L2
2.2 uH R19
8.2k
R20 27k
6
7
2
5
DRAM Power
1、需要快速开关机时,L7上件;DDR-PWREN网络上件;
5V
5VS
L6
BLM18PG121SN1/NC
L7 BLM18PG121SN1
B B
5V
FB_PWR_EN
靠近IC端
A A
100R
R548
C52
10u/16V
R37
12
10k
R38 1k
R39 47k
2、不需要快速开关机,L6、R40上件;DDR-PWREN网络断开;
N36
C53
10u/16V
VD11
1N4148W
DDR_PWREN
C54
100n/16V
C56
100n/16V
R40
10k/NC
C55
1u/25V
C57
8.2n/50V
8
VIN
1
EN
3
VRG5
SS4GND
VBST
EPAD
9
TPS54228
6
SW
7
2
VFB
5
L5
2.2 uH
C58
100n/25V
R41
C59
36k
22p/50V/NC
R42
R43
140k/NC
37.4k
VOUT = 0.765 (1+R41/R42//R43)=1.50V
C60 22u/6.3V
E1
C61 22u/6.3V
NC11NC2
RSAG7.308.0219
2
C62 22u/6.3V
DDR_1.5V
C63
100n/16V
STANDBY POWER 3V3SB
5VS
2.2u/10V
C44
C43
100n/16V
N12
1
VIN
3
EN
TLV70233DBVR
预留C504,兼容其他IC使用,使用70233时需NC
2
VOUT
GND
AVDD1V2
VCCK
BLM18PG121SN1
S4
C45
10u/16V
S2
3.3VS
C46
100n/16V
S3
5
4
NC
C504
100n/16V/NC
S1
AVDD1V2
L48
C499
C500
10u/10V
100n/16V
5
D4
4
3
D4
D4
D4
2
Hisense Electric Co.,LTD
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev C
C
C Date: Sheet
Date: Sheet
Date: Sheet
MT5655
MT5655
MT5655
1
422Friday, April 10, 2015
422Friday, April 10, 2015
422Friday, April 10, 2015
1.0
1.0
1.0
5
MB circuit:6484
N3-6
OSDA0 OSCL0
XTALI XTALO
AVDD33_REG_STB
VCC3IO_EMMC
AVDD33_RGB_STB
D D
C70
1u/16V
AVSS33_RGB AVDD33_PLL_STB
R52 0R
C71
4.7u/10V
AE26
OSDA0
AH26
OSCL0
B28
XTALI
B27
XTALO
J22
AVDD33_REG_STB
J1
VCC3IO_EMMC
H24
AVDD33_RGB_STB
K21
AVSS33_RGB
J23
AVDD33_PLL_STB
U25
AVDD10_LDO EMMC_CLK
AVDD10_ELDO
C66
4.7u/10V
Y26
AVDD10_LDO
AVDD10_ELDO
close to main chip
MT5655
24MHz CRYSTAL
R50 1M
Z1
R51
HC-49SM24MHZ
C67
33p/50V
晶体频偏需要小于
C525
100n/16V
R58 82k/NC
12
0R
C68
33p/50V
30PPM
R60、R61、R62、C73、C516上件,其他NC
C72
10u/10V/NC
R59 82k/NC
MMBT3904LT1 /NC
XTALI XTALO
C C
NOTE:
RESET Circuit
VD1
1N4148W/NC
1 2
3.3VS
R60 16k
3
1
V7
2
100n/16V
SYSTEM EEPROM
I2C ADDRESS "A0"
LO = > WP HI = > WRITE
SYS_EEPROM_WP
OSCL0 OSDA0
close to main chip
R61 1k
R62
C73
22k
U0TX U0RX
POWE#
POOE# POCE1# POCE0#
PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1
PDD0 PARB# PACLE PAALE
EMMC_CLK EMMC_RST
OPWRSB ORESET#
FSRC_WR
R54 0R
ORESETB
C516
100n/16V
T25
U0TX
T24
U0RX
J2
POWE_B
N7 M7 L7 P3
PDD7
N1
PDD6
N2
PDD5
N4
PDD4
M3
PDD3
L1
PDD2
N6 P6 N5 L3
PACLE
K3
PAALE
P4 P7
EMMC_RST
R26
OPWRSB
L25
ORESETB
R533
L26
OIRI
100R
AH27
FSRC_WR
E-Fuse
R55
R56
2.2k
4.7k
UART0
U0RX U0TX
Analog Power
3.3VS 3.3VS 3.3VS
B B
C74
10u/16V
STRAPPING
ICE mode + 24M + serial boot ICE moce + 24M + ROM to 60bit ECC Nand boot
ICE moce + 24M + ROM to eMMC boot from eMMC pins(share pins w/s NAND)
Boundary scan mode
A A
OLT mode scan mode
cpu model mode
3.3VS
C75
100n/16V
AVDD33_RGB_STBAVDD33_REG_STB AVDD33_PLL_STB
C76
100n/16V
R70 10k/NC
R71 10k/NC
R72 10k/NC
LED_PWM0
LED_PWM1
OPCTRL3
LED_PWM0 LED_PWM1 OPCTRL3STRAPPING
001 0
0 1
1 1
R73
10k
R74 10k
R75
10k
1 0 00
0 1 11
OIRI
R53
4.7k
DVDD3V3
R57
2.2k
For ESD
R65 100R
R66 100R
RV88
AVLC18S02015
0 0
11 0
4
TP1
1
8 7 6 5
3.3VS
R67
4.7k
AVLC18S02015
VCC WP SCL
24LC128
R68
4.7k
RV89
N50
C77
100n/16V
3
VCC3IO_EMMC
R99 10k/NC
R98 10k/NC
R97 10k/NC
R96 10k/NC
R95 10k/NC
R94 10k/NC
R93 10k/NC
R92 10k/NC
R91 10k/NC
EMMC
R799
C84 100n/16V/NC
C89 100n/16V
TP2
1
C78 15p/50V/NC
DAT3
VDDI_C2
DAT5
DAT5
DAT6
DAT7
DAT0 DAT1 DAT2 DAT3 DAT4 DAT5 DAT6 DAT7
DAT4 DAT7
E10 F10
G10
K10 P10
A10 A11 A12 A13 A14
B10 B11 B12 B13 B14
C10 C11 C12 C13 C14
D12 D13 D14
E12 E13 E14
F12 F13 F14
G12 G13 G14
N87 H26M31001HPR
M5
CMD
M6
CLK
A3
DAT0
A4
DAT1
A5
DAT2
B2
DAT3
B3
DAT4
B4
DAT5
B5
DAT6
B6
DAT7
H5
Data Strobe
A7
RFU_0
C5
RFU_1
E5
RFU_2
E8
RFU_3
E9
RFU_4 RFU_5 RFU_6
G3
RFU_7 RFU_8
K6
RFU_9
K7
RFU_10 RFU_11
P7
RFU_12 RFU_13
A1
NC_0
A2
NC_1
A8
NC_2
A9
NC_3 NC_4 NC_5 NC_6 NC_7 NC_8
B1
NC_9
B7
NC_10
B8
NC_11
B9
NC_12 NC_13 NC_14 NC_15 NC_16 NC_17
C1
NC_18
C3
NC_19
C7
NC_20
C8
NC_21
C9
NC_22 NC_23 NC_24 NC_25 NC_26 NC_27
D1
NC_28
D2
NC_29
D3
NC_30
D4
NC_31 NC_32 NC_33 NC_34
E1
NC_35
E2
NC_36
E3
NC_37 NC_38 NC_39 NC_40
F1
NC_41
F2
NC_42
F3
NC_43 NC_44 NC_45 NC_46
G1
NC_47
G2
NC_48 NC_49 NC_50 NC_51
H1
NC_52
保证
CLK
走线包地且均匀打孔
POWE_B
R80 47R
EMMC_CLK
R81 47R
PAALE
R82 47R
PACLE
R83 47R
PDD2
R84 47R
PDD3
R85 47R
PDD4
R86 47R
PDD5
R87 47R
PDD6
R88 47R
PDD7
R89 47R
三星的
eMMC在HS400
模式下需要增加
1
A0
2
A1
3
A2
Vss4SDA
1 2 3 4
XP3
6
5
CKX-3.5-111
3
R
4
WR
2
WL
1
L
5
GND
XS13
立式回流端子
此部分网络只是为PCB出线预留 无实际意义
EMMC VCC/VCCQ Power
BLM18PG121SN1
C82
C83
100n/16V
100n/16V
引脚放置
C522
C88
1u/10V
100n/16V
引脚放置
VCC3IO_EMMC
DVDD3V3
DVDD3V3
C80 10u/10V
VCC3IO_EMMC
C85
10u/10V
靠近
靠近
eMMC Flash
L40
C81 1u/10V
eMMC Flash
C86
C87
1u/10V
1u/10V
2
VDD_0 VDD_1 VDD_2 VDD_3 VDD_4
VDDF_0 VDDF_1 VDDF_2 VDDF_3
VDDI
VSS_0 VSS_1 VSS_2 VSS_3
VSS_4 VSSQ_0 VSSQ_1 VSSQ_2 VSSQ_0 VSSQ_3 VSSQ_5
Rest_n
NC_53
NC_54
NC_55
NC_56
NC_57
NC_58
NC_59
NC_60
NC_61
NC_62
NC_63
NC_64
NC_65
NC_66
NC_67
NC_68
NC_69
NC_70
NC_71
NC_72
NC_73
NC_74
NC_75
NC_76
NC_77
NC_78
NC_79
NC_80
NC_81
NC_82
NC_83
NC_84
NC_85
NC_86
NC_87
NC_88
NC_89
NC_90
NC_91
NC_92
NC_93
NC_94
NC_95
NC_96
NC_97
NC_98
NC_99 NC_100 NC_101 NC_102 NC_103 NC_104 NC_105
C6 M4 N4 P3 P5
E6 F5 J10 K9
C2 E7
G5 H10 J5 K8 A6 C4 N2 N5 P4 P6
K5
H2 H3 H12 H13 H14 J1 J2 J3 J12 J13 J14 K1 K2 K3 K12 K13 K14 L1 L2 L3 L12 L13 L14 M1 M2 M3 M7 M8 M9 M10 M11 M12 M13 M14 N1 N3 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P8 P9 P11 P12 P13 P14
VCC3IO_EMMC
VDDI_C2
GND
DVDD3V3
C79 100n/16V
R104
R105 22R
C90
1u/10V/NC
VCC3IO_EMMC
4.7k
EMMC_RST
4,6,7,8,9,10,11,12,13
4
7,8,10,13
12 12 12 12 13
1
GND
OPWRSB
U0RX6 U0TX6 OSCL0 OSDA07,8,10,13 OPCTRL3 LED_PWM1 LED_PWM0
SYS_EEPROM_WP
OIRI
OPWRSB U0RX U0TX OSCL0 OSDA0 OPCTRL3 LED_PWM1 LED_PWM0
SYS_EEPROM_WP
OIRI
5
Hisense Electric Co.,LTD
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev C
C
C Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
MT5655
MT5655
MT5655
1
1.0
1.0
513Wednesday, December 23, 2015
513Wednesday, December 23, 2015
513Wednesday, December 23, 2015
1.0
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